arch/frv/mb93090-mb00/pci-vdk.c

   1 /* pci-vdk.c: MB93090-MB00 (VDK) PCI support
   2  *
   3  * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/kernel.h>
  14 #include <linux/sched.h>
  15 #include <linux/pci.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/delay.h>
  19 #include <linux/slab.h>
  20
  21 #include <asm/segment.h>
  22 #include <asm/io.h>
  23 #include <asm/mb-regs.h>
  24 #include <asm/mb86943a.h>
  25 #include "pci-frv.h"
  26
  27 unsigned int __nongpreldata pci_probe = 1;
  28
  29 int  __nongpreldata pcibios_last_bus = -1;
  30 struct pci_bus *__nongpreldata pci_root_bus;
  31 struct pci_ops *__nongpreldata pci_root_ops;
  32
  33 /*
  34  * The accessible PCI window does not cover the entire CPU address space, but
  35  * there are devices we want to access outside of that window, so we need to
  36  * insert specific PCI bus resources instead of using the platform-level bus
  37  * resources directly for the PCI root bus.
  38  *
  39  * These are configured and inserted by pcibios_init() and are attached to the
  40  * root bus by pcibios_fixup_bus().
  41  */
  42 static struct resource pci_ioport_resource = {
  43         .name   = "PCI IO",
  44         .start  = 0,
  45         .end    = IO_SPACE_LIMIT,
  46         .flags  = IORESOURCE_IO,
  47 };
  48
  49 static struct resource pci_iomem_resource = {
  50         .name   = "PCI mem",
  51         .start  = 0,
  52         .end    = -1,
  53         .flags  = IORESOURCE_MEM,
  54 };
  55
  56 /*
  57  * Functions for accessing PCI configuration space
  58  */
  59
  60 #define CONFIG_CMD(bus, dev, where) \
  61         (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
  62
  63 #define __set_PciCfgAddr(A) writel((A), (volatile void __iomem *) __region_CS1 + 0x80)
  64
  65 #define __get_PciCfgDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 3))
  66 #define __get_PciCfgDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 2))
  67 #define __get_PciCfgDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x88)
  68
  69 #define __set_PciCfgDataB(A,V) \
  70         writeb((V), (volatile void __iomem *) __region_CS1 + 0x88 + (3 - ((A) & 3)))
  71
  72 #define __set_PciCfgDataW(A,V) \
  73         writew((V), (volatile void __iomem *) __region_CS1 + 0x88 + (2 - ((A) & 2)))
  74
  75 #define __set_PciCfgDataL(A,V) \
  76         writel((V), (volatile void __iomem *) __region_CS1 + 0x88)
  77
  78 #define __get_PciBridgeDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x800 + (A))
  79 #define __get_PciBridgeDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x800 + (A))
  80 #define __get_PciBridgeDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x800 + (A))
  81
  82 #define __set_PciBridgeDataB(A,V) writeb((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
  83 #define __set_PciBridgeDataW(A,V) writew((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
  84 #define __set_PciBridgeDataL(A,V) writel((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
  85
  86 static inline int __query(const struct pci_dev *dev)
  87 {
  88 //      return dev->bus->number==0 && (dev->devfn==PCI_DEVFN(0,0));
  89 //      return dev->bus->number==1;
  90 //      return dev->bus->number==0 &&
  91 //              (dev->devfn==PCI_DEVFN(2,0) || dev->devfn==PCI_DEVFN(3,0));
  92         return 0;
  93 }
  94
  95 /*****************************************************************************/
  96 /*
  97  *
  98  */
  99 static int pci_frv_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
 100                                u32 *val)
 101 {
 102         u32 _value;
 103
 104         if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
 105                 _value = __get_PciBridgeDataL(where & ~3);
 106         }
 107         else {
 108                 __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
 109                 _value = __get_PciCfgDataL(where & ~3);
 110         }
 111
 112         switch (size) {
 113         case 1:
 114                 _value = _value >> ((where & 3) * 8);
 115                 break;
 116
 117         case 2:
 118                 _value = _value >> ((where & 2) * 8);
 119                 break;
 120
 121         case 4:
 122                 break;
 123
 124         default:
 125                 BUG();
 126         }
 127
 128         *val = _value;
 129         return PCIBIOS_SUCCESSFUL;
 130 }
 131
 132 static int pci_frv_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
 133                                 u32 value)
 134 {
 135         switch (size) {
 136         case 1:
 137                 if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
 138                         __set_PciBridgeDataB(where, value);
 139                 }
 140                 else {
 141                         __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
 142                         __set_PciCfgDataB(where, value);
 143                 }
 144                 break;
 145
 146         case 2:
 147                 if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
 148                         __set_PciBridgeDataW(where, value);
 149                 }
 150                 else {
 151                         __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
 152                         __set_PciCfgDataW(where, value);
 153                 }
 154                 break;
 155
 156         case 4:
 157                 if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
 158                         __set_PciBridgeDataL(where, value);
 159                 }
 160                 else {
 161                         __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
 162                         __set_PciCfgDataL(where, value);
 163                 }
 164                 break;
 165
 166         default:
 167                 BUG();
 168         }
 169
 170         return PCIBIOS_SUCCESSFUL;
 171 }
 172
 173 static struct pci_ops pci_direct_frv = {
 174         pci_frv_read_config,
 175         pci_frv_write_config,
 176 };
 177
 178 /*
 179  * Before we decide to use direct hardware access mechanisms, we try to do some
 180  * trivial checks to ensure it at least _seems_ to be working -- we just test
 181  * whether bus 00 contains a host bridge (this is similar to checking
 182  * techniques used in XFree86, but ours should be more reliable since we
 183  * attempt to make use of direct access hints provided by the PCI BIOS).
 184  *
 185  * This should be close to trivial, but it isn't, because there are buggy
 186  * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
 187  */
 188 static int __init pci_sanity_check(struct pci_ops *o)
 189 {
 190         struct pci_bus bus;             /* Fake bus and device */
 191         u32 id;
 192
 193         bus.number      = 0;
 194
 195         if (o->read(&bus, 0, PCI_VENDOR_ID, 4, &id) == PCIBIOS_SUCCESSFUL) {
 196                 printk("PCI: VDK Bridge device:vendor: %08x\n", id);
 197                 if (id == 0x200e10cf)
 198                         return 1;
 199         }
 200
 201         printk("PCI: VDK Bridge: Sanity check failed\n");
 202         return 0;
 203 }
 204
 205 static struct pci_ops * __init pci_check_direct(void)
 206 {
 207         unsigned long flags;
 208
 209         local_irq_save(flags);
 210
 211         /* check if access works */
 212         if (pci_sanity_check(&pci_direct_frv)) {
 213                 local_irq_restore(flags);
 214                 printk("PCI: Using configuration frv\n");
 215 //              request_mem_region(0xBE040000, 256, "FRV bridge");
 216 //              request_mem_region(0xBFFFFFF4, 12, "PCI frv");
 217                 return &pci_direct_frv;
 218         }
 219
 220         local_irq_restore(flags);
 221         return NULL;
 222 }
 223
 224 /*
 225  * Discover remaining PCI buses in case there are peer host bridges.
 226  * We use the number of last PCI bus provided by the PCI BIOS.
 227  */
 228 static void __init pcibios_fixup_peer_bridges(void)
 229 {
 230         struct pci_bus bus;
 231         struct pci_dev dev;
 232         int n;
 233         u16 l;
 234
 235         if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
 236                 return;
 237         printk("PCI: Peer bridge fixup\n");
 238         for (n=0; n <= pcibios_last_bus; n++) {
 239                 if (pci_find_bus(0, n))
 240                         continue;
 241                 bus.number = n;
 242                 bus.ops = pci_root_ops;
 243                 dev.bus = &bus;
 244                 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
 245                         if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
 246                             l != 0x0000 && l != 0xffff) {
 247                                 printk("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
 248                                 printk("PCI: Discovered peer bus %02x\n", n);
 249                                 pci_scan_bus(n, pci_root_ops, NULL);
 250                                 break;
 251                         }
 252         }
 253 }
 254
 255 /*
 256  * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
 257  */
 258
 259 static void __init pci_fixup_umc_ide(struct pci_dev *d)
 260 {
 261         /*
 262          * UM8886BF IDE controller sets region type bits incorrectly,
 263          * therefore they look like memory despite of them being I/O.
 264          */
 265         int i;
 266
 267         printk("PCI: Fixing base address flags for device %s\n", pci_name(d));
 268         for(i=0; i<4; i++)
 269                 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
 270 }
 271
 272 static void __init pci_fixup_ide_bases(struct pci_dev *d)
 273 {
 274         int i;
 275
 276         /*
 277          * PCI IDE controllers use non-standard I/O port decoding, respect it.
 278          */
 279         if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
 280                 return;
 281         printk("PCI: IDE base address fixup for %s\n", pci_name(d));
 282         for(i=0; i<4; i++) {
 283                 struct resource *r = &d->resource[i];
 284                 if ((r->start & ~0x80) == 0x374) {
 285                         r->start |= 2;
 286                         r->end = r->start;
 287                 }
 288         }
 289 }
 290
 291 static void __init pci_fixup_ide_trash(struct pci_dev *d)
 292 {
 293         int i;
 294
 295         /*
 296          * There exist PCI IDE controllers which have utter garbage
 297          * in first four base registers. Ignore that.
 298          */
 299         printk("PCI: IDE base address trash cleared for %s\n", pci_name(d));
 300         for(i=0; i<4; i++)
 301                 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
 302 }
 303
 304 static void __devinit  pci_fixup_latency(struct pci_dev *d)
 305 {
 306         /*
 307          *  SiS 5597 and 5598 chipsets require latency timer set to
 308          *  at most 32 to avoid lockups.
 309          */
 310         DBG("PCI: Setting max latency to 32\n");
 311         pcibios_max_latency = 32;
 312 }
 313
 314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
 315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
 316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
 317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
 318 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
 319
 320 /*
 321  *  Called after each bus is probed, but before its children
 322  *  are examined.
 323  */
 324
 325 void __init pcibios_fixup_bus(struct pci_bus *bus)
 326 {
 327 #if 0
 328         printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);
 329 #endif
 330
 331         if (bus->number == 0) {
 332                 bus->resource[0] = &pci_ioport_resource;
 333                 bus->resource[1] = &pci_iomem_resource;
 334         }
 335
 336         pci_read_bridge_bases(bus);
 337
 338         if (bus->number == 0) {
 339                 struct list_head *ln;
 340                 struct pci_dev *dev;
 341                 for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
 342                         dev = pci_dev_b(ln);
 343                         if (dev->devfn == 0) {
 344                                 dev->resource[0].start = 0;
 345                                 dev->resource[0].end = 0;
 346                         }
 347                 }
 348         }
 349 }
 350
 351 /*
 352  * Initialization. Try all known PCI access methods. Note that we support
 353  * using both PCI BIOS and direct access: in such cases, we use I/O ports
 354  * to access config space, but we still keep BIOS order of cards to be
 355  * compatible with 2.0.X. This should go away some day.
 356  */
 357
 358 int __init pcibios_init(void)
 359 {
 360         struct pci_ops *dir = NULL;
 361
 362         if (!mb93090_mb00_detected)
 363                 return -ENXIO;
 364
 365         __reg_MB86943_sl_ctl |= MB86943_SL_CTL_DRCT_MASTER_SWAP | MB86943_SL_CTL_DRCT_SLAVE_SWAP;
 366
 367         __reg_MB86943_ecs_base(1)       = ((__region_CS2 + 0x01000000) >> 9) | 0x08000000;
 368         __reg_MB86943_ecs_base(2)       = ((__region_CS2 + 0x00000000) >> 9) | 0x08000000;
 369
 370         *(volatile uint32_t *) (__region_CS1 + 0x848) = 0xe0000000;
 371         *(volatile uint32_t *) (__region_CS1 + 0x8b8) = 0x00000000;
 372
 373         __reg_MB86943_sl_pci_io_base    = (__region_CS2 + 0x04000000) >> 9;
 374         __reg_MB86943_sl_pci_mem_base   = (__region_CS2 + 0x08000000) >> 9;
 375         __reg_MB86943_pci_sl_io_base    = __region_CS2 + 0x04000000;
 376         __reg_MB86943_pci_sl_mem_base   = __region_CS2 + 0x08000000;
 377         mb();
 378
 379         /* enable PCI arbitration */
 380         __reg_MB86943_pci_arbiter       = MB86943_PCIARB_EN;
 381
 382         pci_ioport_resource.start       = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
 383         pci_ioport_resource.end         = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
 384         pci_ioport_resource.end         += pci_ioport_resource.start;
 385
 386         printk("PCI IO window:  %08llx-%08llx\n",
 387                (unsigned long long) pci_ioport_resource.start,
 388                (unsigned long long) pci_ioport_resource.end);
 389
 390         pci_iomem_resource.start        = (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00;
 391         pci_iomem_resource.end          = (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff;
 392         pci_iomem_resource.end          += pci_iomem_resource.start;
 393
 394         /* Reserve somewhere to write to flush posted writes.  This is used by
 395          * __flush_PCI_writes() from asm/io.h to force the write FIFO in the
 396          * CPU-PCI bridge to flush as this doesn't happen automatically when a
 397          * read is performed on the MB93090 development kit motherboard.
 398          */
 399         pci_iomem_resource.start        += 0x400;
 400
 401         printk("PCI MEM window: %08llx-%08llx\n",
 402                (unsigned long long) pci_iomem_resource.start,
 403                (unsigned long long) pci_iomem_resource.end);
 404         printk("PCI DMA memory: %08lx-%08lx\n",
 405                dma_coherent_mem_start, dma_coherent_mem_end);
 406
 407         if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
 408                 panic("Unable to insert PCI IOMEM resource\n");
 409         if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
 410                 panic("Unable to insert PCI IOPORT resource\n");
 411
 412         if (!pci_probe)
 413                 return -ENXIO;
 414
 415         dir = pci_check_direct();
 416         if (dir)
 417                 pci_root_ops = dir;
 418         else {
 419                 printk("PCI: No PCI bus detected\n");
 420                 return -ENXIO;
 421         }
 422
 423         printk("PCI: Probing PCI hardware\n");
 424         pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL);
 425
 426         pcibios_irq_init();
 427         pcibios_fixup_peer_bridges();
 428         pcibios_fixup_irqs();
 429         pcibios_resource_survey();
 430
 431         return 0;
 432 }
 433
 434 arch_initcall(pcibios_init);
 435
 436 char * __init pcibios_setup(char *str)
 437 {
 438         if (!strcmp(str, "off")) {
 439                 pci_probe = 0;
 440                 return NULL;
 441         } else if (!strncmp(str, "lastbus=", 8)) {
 442                 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
 443                 return NULL;
 444         }
 445         return str;
 446 }
 447
 448 int pcibios_enable_device(struct pci_dev *dev, int mask)
 449 {
 450         int err;
 451
 452         if ((err = pci_enable_resources(dev, mask)) < 0)
 453                 return err;
 454         if (!dev->msi_enabled)
 455                 pcibios_enable_irq(dev);
 456         return 0;
 457 }