1 /* tlb-miss.S: TLB miss handlers
3 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/sys.h>
13 #include <linux/linkage.h>
15 #include <asm/pgtable.h>
16 #include <asm/highmem.h>
17 #include <asm/spr-regs.h>
19 .section .text.tlbmiss
22 .globl __entry_insn_mmu_miss
23 __entry_insn_mmu_miss:
27 .globl __entry_insn_mmu_exception
28 __entry_insn_mmu_exception:
32 .globl __entry_data_mmu_miss
33 __entry_data_mmu_miss:
37 .globl __entry_data_mmu_exception
38 __entry_data_mmu_exception:
42 ###############################################################################
44 # handle a lookup failure of one sort or another in a kernel TLB handler
46 # GR29 - faulting address
49 ###############################################################################
50 .type __tlb_kernel_fault,@function
52 # see if we're supposed to re-enable single-step mode upon return
53 sethi.p %hi(__break_tlb_miss_return_break),gr30
54 setlo %lo(__break_tlb_miss_return_break),gr30
57 subcc gr31,gr30,gr0,icc0
58 beq icc0,#0,__tlb_kernel_fault_sstep
62 movgs gr29,scr2 /* save EAR0 value */
63 sethi.p %hi(__kernel_current_task),gr29
64 setlo %lo(__kernel_current_task),gr29
65 ldi.p @(gr29,#0),gr29 /* restore GR29 */
67 bra __entry_kernel_handle_mmu_fault
69 # we've got to re-enable single-stepping
70 __tlb_kernel_fault_sstep:
71 sethi.p %hi(__break_tlb_miss_real_return_info),gr30
72 setlo %lo(__break_tlb_miss_real_return_info),gr30
79 movgs gr29,scr2 /* save EAR0 value */
80 sethi.p %hi(__kernel_current_task),gr29
81 setlo %lo(__kernel_current_task),gr29
82 ldi.p @(gr29,#0),gr29 /* restore GR29 */
83 bra __entry_kernel_handle_mmu_fault_sstep
85 .size __tlb_kernel_fault, .-__tlb_kernel_fault
87 ###############################################################################
89 # handle a lookup failure of one sort or another in a user TLB handler
91 # GR28 - faulting address
94 ###############################################################################
95 .type __tlb_user_fault,@function
97 # see if we're supposed to re-enable single-step mode upon return
98 sethi.p %hi(__break_tlb_miss_return_break),gr30
99 setlo %lo(__break_tlb_miss_return_break),gr30
101 subcc gr31,gr30,gr0,icc0
102 beq icc0,#0,__tlb_user_fault_sstep
106 bra __entry_uspace_handle_mmu_fault
108 # we've got to re-enable single-stepping
109 __tlb_user_fault_sstep:
110 sethi.p %hi(__break_tlb_miss_real_return_info),gr30
111 setlo %lo(__break_tlb_miss_real_return_info),gr30
117 bra __entry_uspace_handle_mmu_fault_sstep
119 .size __tlb_user_fault, .-__tlb_user_fault
121 ###############################################################################
123 # Kernel instruction TLB miss handler
125 # GR1 - kernel stack pointer
126 # GR28 - saved exception frame pointer
127 # GR29 - faulting address
129 # SCR0 - base of virtual range covered by cached PGE from last ITLB miss (or 0xffffffff)
130 # DAMR3 - mapped page directory
131 # DAMR4 - mapped page table as matched by SCR0
133 ###############################################################################
134 .globl __entry_kernel_insn_tlb_miss
135 .type __entry_kernel_insn_tlb_miss,@function
136 __entry_kernel_insn_tlb_miss:
138 sethi.p %hi(0xe1200004),gr30
139 setlo %lo(0xe1200004),gr30
141 sethi.p %hi(0xffc00100),gr30
142 setlo %lo(0xffc00100),gr30
147 movsg ccr,gr30 /* save CCR */
150 # see if the cached page table mapping is appropriate
151 srlicc.p gr31,#26,gr0,icc0
153 srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
154 bne icc0,#0,__itlb_k_PTD_miss
157 # access the PTD with EAR0[25:14]
158 # - DAMLR4 points to the virtual address of the appropriate page table
159 # - the PTD holds 4096 PTEs
160 # - the PTD must be accessed uncached
161 # - the PTE must be marked accessed if it was valid
166 ldi @(gr31,#0),gr30 /* fetch the PTE */
167 andicc gr30,#_PAGE_PRESENT,gr0,icc0
168 ori.p gr30,#_PAGE_ACCESSED,gr30
169 beq icc0,#0,__tlb_kernel_fault /* jump if PTE invalid */
170 sti.p gr30,@(gr31,#0) /* update the PTE */
171 andi gr30,#~_PAGE_ACCESSED,gr30
173 # we're using IAMR1 as an extra TLB entry
174 # - punt the entry here (if valid) to the real TLB and then replace with the new PTE
175 # - need to check DAMR1 lest we cause an multiple-DAT-hit exception
176 # - IAMPR1 has no WP bit, and we mustn't lose WP information
178 andicc gr31,#xAMPRx_V,gr0,icc0
179 setlos.p 0xfffff000,gr31
180 beq icc0,#0,__itlb_k_nopunt /* punt not required */
183 movgs gr31,tplr /* set TPLR.CXN */
184 tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
187 ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
189 movsg iamlr1,gr31 /* set TPLR.CXN */
191 tlbpr gr31,gr0,#2,#0 /* save to the TLB */
192 movsg tpxr,gr31 /* check the TLB write error flag */
193 andicc.p gr31,#TPXR_E,gr0,icc0
194 setlos #0xfffff000,gr31
195 bne icc0,#0,__tlb_kernel_fault
199 # assemble the new TLB entry
203 movgs gr29,iamlr1 /* xAMLR = address | context number */
208 # return, restoring registers
211 sethi.p %hi(__kernel_current_task),gr29
212 setlo %lo(__kernel_current_task),gr29
215 beq icc0,#3,0 /* prevent icache prefetch */
217 # the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
218 # appropriate page table and map that instead
219 # - access the PGD with EAR0[31:26]
220 # - DAMLR3 points to the virtual address of the page directory
221 # - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
223 srli gr29,#26,gr31 /* calculate PGE offset */
224 slli gr31,#8,gr31 /* and clear bottom bits */
227 ld @(gr31,gr30),gr30 /* access the PGE */
229 andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
230 andicc gr30,#xAMPRx_SS,gr0,icc1
232 # map this PTD instead and record coverage address
233 ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
234 beq icc0,#0,__tlb_kernel_fault /* jump if PGE not present */
236 bne icc1,#0,__itlb_k_bigpage
240 # we can now resume normal service
242 srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
243 bra __itlb_k_PTD_mapped
249 .size __entry_kernel_insn_tlb_miss, .-__entry_kernel_insn_tlb_miss
251 ###############################################################################
253 # Kernel data TLB miss handler
255 # GR1 - kernel stack pointer
256 # GR28 - saved exception frame pointer
257 # GR29 - faulting address
259 # SCR1 - base of virtual range covered by cached PGE from last DTLB miss (or 0xffffffff)
260 # DAMR3 - mapped page directory
261 # DAMR5 - mapped page table as matched by SCR1
263 ###############################################################################
264 .globl __entry_kernel_data_tlb_miss
265 .type __entry_kernel_data_tlb_miss,@function
266 __entry_kernel_data_tlb_miss:
268 sethi.p %hi(0xe1200004),gr30
269 setlo %lo(0xe1200004),gr30
271 sethi.p %hi(0xffc00100),gr30
272 setlo %lo(0xffc00100),gr30
277 movsg ccr,gr30 /* save CCR */
280 # see if the cached page table mapping is appropriate
281 srlicc.p gr31,#26,gr0,icc0
283 srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
284 bne icc0,#0,__dtlb_k_PTD_miss
287 # access the PTD with EAR0[25:14]
288 # - DAMLR5 points to the virtual address of the appropriate page table
289 # - the PTD holds 4096 PTEs
290 # - the PTD must be accessed uncached
291 # - the PTE must be marked accessed if it was valid
296 ldi @(gr31,#0),gr30 /* fetch the PTE */
297 andicc gr30,#_PAGE_PRESENT,gr0,icc0
298 ori.p gr30,#_PAGE_ACCESSED,gr30
299 beq icc0,#0,__tlb_kernel_fault /* jump if PTE invalid */
300 sti.p gr30,@(gr31,#0) /* update the PTE */
301 andi gr30,#~_PAGE_ACCESSED,gr30
303 # we're using DAMR1 as an extra TLB entry
304 # - punt the entry here (if valid) to the real TLB and then replace with the new PTE
305 # - need to check IAMR1 lest we cause an multiple-DAT-hit exception
307 andicc gr31,#xAMPRx_V,gr0,icc0
308 setlos.p 0xfffff000,gr31
309 beq icc0,#0,__dtlb_k_nopunt /* punt not required */
312 movgs gr31,tplr /* set TPLR.CXN */
313 tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
316 ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
318 movsg damlr1,gr31 /* set TPLR.CXN */
320 tlbpr gr31,gr0,#2,#0 /* save to the TLB */
321 movsg tpxr,gr31 /* check the TLB write error flag */
322 andicc.p gr31,#TPXR_E,gr0,icc0
323 setlos #0xfffff000,gr31
324 bne icc0,#0,__tlb_kernel_fault
328 # assemble the new TLB entry
332 movgs gr29,iamlr1 /* xAMLR = address | context number */
337 # return, restoring registers
340 sethi.p %hi(__kernel_current_task),gr29
341 setlo %lo(__kernel_current_task),gr29
344 beq icc0,#3,0 /* prevent icache prefetch */
346 # the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
347 # appropriate page table and map that instead
348 # - access the PGD with EAR0[31:26]
349 # - DAMLR3 points to the virtual address of the page directory
350 # - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
352 srli gr29,#26,gr31 /* calculate PGE offset */
353 slli gr31,#8,gr31 /* and clear bottom bits */
356 ld @(gr31,gr30),gr30 /* access the PGE */
358 andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
359 andicc gr30,#xAMPRx_SS,gr0,icc1
361 # map this PTD instead and record coverage address
362 ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
363 beq icc0,#0,__tlb_kernel_fault /* jump if PGE not present */
365 bne icc1,#0,__dtlb_k_bigpage
369 # we can now resume normal service
371 srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
372 bra __dtlb_k_PTD_mapped
378 .size __entry_kernel_data_tlb_miss, .-__entry_kernel_data_tlb_miss
380 ###############################################################################
382 # Userspace instruction TLB miss handler (with PGE prediction)
384 # GR28 - faulting address
386 # SCR0 - base of virtual range covered by cached PGE from last ITLB miss (or 0xffffffff)
387 # DAMR3 - mapped page directory
388 # DAMR4 - mapped page table as matched by SCR0
390 ###############################################################################
391 .globl __entry_user_insn_tlb_miss
392 .type __entry_user_insn_tlb_miss,@function
393 __entry_user_insn_tlb_miss:
395 sethi.p %hi(0xe1200004),gr30
396 setlo %lo(0xe1200004),gr30
398 sethi.p %hi(0xffc00100),gr30
399 setlo %lo(0xffc00100),gr30
404 movsg ccr,gr30 /* save CCR */
407 # see if the cached page table mapping is appropriate
408 srlicc.p gr31,#26,gr0,icc0
410 srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
411 bne icc0,#0,__itlb_u_PTD_miss
414 # access the PTD with EAR0[25:14]
415 # - DAMLR4 points to the virtual address of the appropriate page table
416 # - the PTD holds 4096 PTEs
417 # - the PTD must be accessed uncached
418 # - the PTE must be marked accessed if it was valid
423 ldi @(gr31,#0),gr30 /* fetch the PTE */
424 andicc gr30,#_PAGE_PRESENT,gr0,icc0
425 ori.p gr30,#_PAGE_ACCESSED,gr30
426 beq icc0,#0,__tlb_user_fault /* jump if PTE invalid */
427 sti.p gr30,@(gr31,#0) /* update the PTE */
428 andi gr30,#~_PAGE_ACCESSED,gr30
430 # we're using IAMR1/DAMR1 as an extra TLB entry
431 # - punt the entry here (if valid) to the real TLB and then replace with the new PTE
433 andicc gr31,#xAMPRx_V,gr0,icc0
434 setlos.p 0xfffff000,gr31
435 beq icc0,#0,__itlb_u_nopunt /* punt not required */
439 movsg damlr1,gr31 /* set TPLR.CXN */
441 tlbpr gr31,gr0,#2,#0 /* save to the TLB */
442 movsg tpxr,gr31 /* check the TLB write error flag */
443 andicc.p gr31,#TPXR_E,gr0,icc0
444 setlos #0xfffff000,gr31
445 bne icc0,#0,__tlb_user_fault
449 # assemble the new TLB entry
453 movgs gr28,iamlr1 /* xAMLR = address | context number */
458 # return, restoring registers
462 beq icc0,#3,0 /* prevent icache prefetch */
464 # the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
465 # appropriate page table and map that instead
466 # - access the PGD with EAR0[31:26]
467 # - DAMLR3 points to the virtual address of the page directory
468 # - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
470 srli gr28,#26,gr31 /* calculate PGE offset */
471 slli gr31,#8,gr31 /* and clear bottom bits */
474 ld @(gr31,gr30),gr30 /* access the PGE */
476 andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
477 andicc gr30,#xAMPRx_SS,gr0,icc1
479 # map this PTD instead and record coverage address
480 ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
481 beq icc0,#0,__tlb_user_fault /* jump if PGE not present */
483 bne icc1,#0,__itlb_u_bigpage
487 # we can now resume normal service
489 srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
490 bra __itlb_u_PTD_mapped
496 .size __entry_user_insn_tlb_miss, .-__entry_user_insn_tlb_miss
498 ###############################################################################
500 # Userspace data TLB miss handler
502 # GR28 - faulting address
504 # SCR1 - base of virtual range covered by cached PGE from last DTLB miss (or 0xffffffff)
505 # DAMR3 - mapped page directory
506 # DAMR5 - mapped page table as matched by SCR1
508 ###############################################################################
509 .globl __entry_user_data_tlb_miss
510 .type __entry_user_data_tlb_miss,@function
511 __entry_user_data_tlb_miss:
513 sethi.p %hi(0xe1200004),gr30
514 setlo %lo(0xe1200004),gr30
516 sethi.p %hi(0xffc00100),gr30
517 setlo %lo(0xffc00100),gr30
522 movsg ccr,gr30 /* save CCR */
525 # see if the cached page table mapping is appropriate
526 srlicc.p gr31,#26,gr0,icc0
528 srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
529 bne icc0,#0,__dtlb_u_PTD_miss
532 # access the PTD with EAR0[25:14]
533 # - DAMLR5 points to the virtual address of the appropriate page table
534 # - the PTD holds 4096 PTEs
535 # - the PTD must be accessed uncached
536 # - the PTE must be marked accessed if it was valid
543 ldi @(gr31,#0),gr30 /* fetch the PTE */
544 andicc gr30,#_PAGE_PRESENT,gr0,icc0
545 ori.p gr30,#_PAGE_ACCESSED,gr30
546 beq icc0,#0,__tlb_user_fault /* jump if PTE invalid */
547 sti.p gr30,@(gr31,#0) /* update the PTE */
548 andi gr30,#~_PAGE_ACCESSED,gr30
550 # we're using DAMR1 as an extra TLB entry
551 # - punt the entry here (if valid) to the real TLB and then replace with the new PTE
553 andicc gr31,#xAMPRx_V,gr0,icc0
554 setlos.p 0xfffff000,gr31
555 beq icc0,#0,__dtlb_u_nopunt /* punt not required */
559 movsg damlr1,gr31 /* set TPLR.CXN */
561 tlbpr gr31,gr0,#2,#0 /* save to the TLB */
562 movsg tpxr,gr31 /* check the TLB write error flag */
563 andicc.p gr31,#TPXR_E,gr0,icc0
564 setlos #0xfffff000,gr31
565 bne icc0,#0,__tlb_user_fault
569 # assemble the new TLB entry
573 movgs gr28,iamlr1 /* xAMLR = address | context number */
578 # return, restoring registers
582 beq icc0,#3,0 /* prevent icache prefetch */
584 # the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
585 # appropriate page table and map that instead
586 # - first of all, check the insn PGE cache - we may well get a hit there
587 # - access the PGD with EAR0[31:26]
588 # - DAMLR3 points to the virtual address of the page directory
589 # - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
591 movsg scr0,gr31 /* consult the insn-PGE-cache key */
593 srlicc gr31,#26,gr0,icc0
594 srli gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
595 bne icc0,#0,__dtlb_u_iPGE_miss
597 # what we're looking for is covered by the insn-PGE-cache
601 bra __dtlb_u_using_iPTD
604 srli gr28,#26,gr31 /* calculate PGE offset */
605 slli gr31,#8,gr31 /* and clear bottom bits */
608 ld @(gr31,gr30),gr30 /* access the PGE */
610 andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
611 andicc gr30,#xAMPRx_SS,gr0,icc1
613 # map this PTD instead and record coverage address
614 ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
615 beq icc0,#0,__tlb_user_fault /* jump if PGE not present */
617 bne icc1,#0,__dtlb_u_bigpage
621 # we can now resume normal service
623 srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
624 bra __dtlb_u_PTD_mapped
630 .size __entry_user_data_tlb_miss, .-__entry_user_data_tlb_miss
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