2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/interrupt.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/sysdev.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
33 #include <asm/atomic.h>
36 #include <asm/mpspec.h>
38 #include <asm/arch_hooks.h>
40 #include <asm/i8253.h>
43 #include <mach_apic.h>
44 #include <mach_apicdef.h>
52 #if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F
53 # error SPURIOUS_APIC_VECTOR definition error
57 * Knob to control our willingness to enable the local APIC.
59 * -1=force-disable, +1=force-enable
61 static int enable_local_apic __initdata
= 0;
63 /* Local APIC timer verification ok */
64 static int local_apic_timer_verify_ok
;
65 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
66 static int local_apic_timer_disabled
;
69 * Debug level, exported for io_apic.c
73 static unsigned int calibration_result
;
75 static int lapic_next_event(unsigned long delta
,
76 struct clock_event_device
*evt
);
77 static void lapic_timer_setup(enum clock_event_mode mode
,
78 struct clock_event_device
*evt
);
79 static void lapic_timer_broadcast(cpumask_t mask
);
80 static void apic_pm_activate(void);
83 * The local apic timer can be used for any function which is CPU local.
85 static struct clock_event_device lapic_clockevent
= {
87 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
88 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
90 .set_mode
= lapic_timer_setup
,
91 .set_next_event
= lapic_next_event
,
92 .broadcast
= lapic_timer_broadcast
,
96 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
98 /* Local APIC was disabled by the BIOS and enabled by the kernel */
99 static int enabled_via_apicbase
;
102 * Get the LAPIC version
104 static inline int lapic_get_version(void)
106 return GET_APIC_VERSION(apic_read(APIC_LVR
));
110 * Check, if the APIC is integrated or a seperate chip
112 static inline int lapic_is_integrated(void)
114 return APIC_INTEGRATED(lapic_get_version());
118 * Check, whether this is a modern or a first generation APIC
120 static int modern_apic(void)
122 /* AMD systems use old APIC versions, so check the CPU */
123 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
124 boot_cpu_data
.x86
>= 0xf)
126 return lapic_get_version() >= 0x14;
130 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
132 void enable_NMI_through_LVT0 (void * dummy
)
134 unsigned int v
= APIC_DM_NMI
;
136 /* Level triggered for 82489DX */
137 if (!lapic_is_integrated())
138 v
|= APIC_LVT_LEVEL_TRIGGER
;
139 apic_write_around(APIC_LVT0
, v
);
143 * get_physical_broadcast - Get number of physical broadcast IDs
145 int get_physical_broadcast(void)
147 return modern_apic() ? 0xff : 0xf;
151 * lapic_get_maxlvt - get the maximum number of local vector table entries
153 int lapic_get_maxlvt(void)
155 unsigned int v
= apic_read(APIC_LVR
);
157 /* 82489DXs do not report # of LVT entries. */
158 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
165 /* Clock divisor is set to 16 */
166 #define APIC_DIVISOR 16
169 * This function sets up the local APIC timer, with a timeout of
170 * 'clocks' APIC bus clock. During calibration we actually call
171 * this function twice on the boot CPU, once with a bogus timeout
172 * value, second time for real. The other (noncalibrating) CPUs
173 * call this function only once, with the real, calibrated value.
175 * We do reads before writes even if unnecessary, to get around the
176 * P5 APIC double write bug.
178 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
180 unsigned int lvtt_value
, tmp_value
;
182 lvtt_value
= LOCAL_TIMER_VECTOR
;
184 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
185 if (!lapic_is_integrated())
186 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
189 lvtt_value
|= APIC_LVT_MASKED
;
191 apic_write_around(APIC_LVTT
, lvtt_value
);
196 tmp_value
= apic_read(APIC_TDCR
);
197 apic_write_around(APIC_TDCR
, (tmp_value
198 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
202 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
206 * Program the next event, relative to now
208 static int lapic_next_event(unsigned long delta
,
209 struct clock_event_device
*evt
)
211 apic_write_around(APIC_TMICT
, delta
);
216 * Setup the lapic timer in periodic or oneshot mode
218 static void lapic_timer_setup(enum clock_event_mode mode
,
219 struct clock_event_device
*evt
)
224 /* Lapic used for broadcast ? */
225 if (!local_apic_timer_verify_ok
)
228 local_irq_save(flags
);
231 case CLOCK_EVT_MODE_PERIODIC
:
232 case CLOCK_EVT_MODE_ONESHOT
:
233 __setup_APIC_LVTT(calibration_result
,
234 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
236 case CLOCK_EVT_MODE_UNUSED
:
237 case CLOCK_EVT_MODE_SHUTDOWN
:
238 v
= apic_read(APIC_LVTT
);
239 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
240 apic_write_around(APIC_LVTT
, v
);
244 local_irq_restore(flags
);
248 * Local APIC timer broadcast function
250 static void lapic_timer_broadcast(cpumask_t mask
)
253 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
258 * Setup the local APIC timer for this CPU. Copy the initilized values
259 * of the boot CPU and register the clock event in the framework.
261 static void __devinit
setup_APIC_timer(void)
263 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
265 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
266 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
268 clockevents_register_device(levt
);
272 * Detect systems with known broken BIOS implementations
274 static int __init
lapic_check_broken_bios(struct dmi_system_id
*d
)
276 printk(KERN_NOTICE
"%s detected: disabling lapic timer.\n",
278 local_apic_timer_disabled
= 1;
282 static struct dmi_system_id __initdata broken_bios_dmi_table
[] = {
285 * BIOS exports only C1 state, but uses deeper power
286 * modes behind the kernels back.
288 .callback
= lapic_check_broken_bios
,
289 .ident
= "HP nx6325",
291 DMI_MATCH(DMI_PRODUCT_NAME
, "HP Compaq nx6325"),
298 * In this functions we calibrate APIC bus clocks to the external timer.
300 * We want to do the calibration only once since we want to have local timer
301 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
304 * This was previously done by reading the PIT/HPET and waiting for a wrap
305 * around to find out, that a tick has elapsed. I have a box, where the PIT
306 * readout is broken, so it never gets out of the wait loop again. This was
307 * also reported by others.
309 * Monitoring the jiffies value is inaccurate and the clockevents
310 * infrastructure allows us to do a simple substitution of the interrupt
313 * The calibration routine also uses the pm_timer when possible, as the PIT
314 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
315 * back to normal later in the boot process).
318 #define LAPIC_CAL_LOOPS (HZ/10)
320 static __initdata
volatile int lapic_cal_loops
= -1;
321 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
322 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
323 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
324 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
327 * Temporary interrupt handler.
329 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
331 unsigned long long tsc
= 0;
332 long tapic
= apic_read(APIC_TMCCT
);
333 unsigned long pm
= acpi_pm_read_early();
338 switch (lapic_cal_loops
++) {
340 lapic_cal_t1
= tapic
;
341 lapic_cal_tsc1
= tsc
;
343 lapic_cal_j1
= jiffies
;
346 case LAPIC_CAL_LOOPS
:
347 lapic_cal_t2
= tapic
;
348 lapic_cal_tsc2
= tsc
;
349 if (pm
< lapic_cal_pm1
)
350 pm
+= ACPI_PM_OVRRUN
;
352 lapic_cal_j2
= jiffies
;
358 * Setup the boot APIC
360 * Calibrate and verify the result.
362 void __init
setup_boot_APIC_clock(void)
364 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
365 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
366 const long pm_thresh
= pm_100ms
/100;
367 void (*real_handler
)(struct clock_event_device
*dev
);
368 unsigned long deltaj
;
370 int pm_referenced
= 0;
372 /* Detect know broken systems */
373 dmi_check_system(broken_bios_dmi_table
);
376 * The local apic timer can be disabled via the kernel
377 * commandline or from the dmi quirk above. Register the lapic
378 * timer as a dummy clock event source on SMP systems, so the
379 * broadcast mechanism is used. On UP systems simply ignore it.
381 if (local_apic_timer_disabled
) {
382 /* No broadcast on UP ! */
383 if (num_possible_cpus() > 1)
388 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
389 "calibrating APIC timer ...\n");
393 /* Replace the global interrupt handler */
394 real_handler
= global_clock_event
->event_handler
;
395 global_clock_event
->event_handler
= lapic_cal_handler
;
398 * Setup the APIC counter to 1e9. There is no way the lapic
399 * can underflow in the 100ms detection time frame
401 __setup_APIC_LVTT(1000000000, 0, 0);
403 /* Let the interrupts run */
406 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
411 /* Restore the real event handler */
412 global_clock_event
->event_handler
= real_handler
;
414 /* Build delta t1-t2 as apic timer counts down */
415 delta
= lapic_cal_t1
- lapic_cal_t2
;
416 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
418 /* Check, if the PM timer is available */
419 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
420 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
426 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
428 if (deltapm
> (pm_100ms
- pm_thresh
) &&
429 deltapm
< (pm_100ms
+ pm_thresh
)) {
430 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
432 res
= (((u64
) deltapm
) * mult
) >> 22;
433 do_div(res
, 1000000);
434 printk(KERN_WARNING
"APIC calibration not consistent "
435 "with PM Timer: %ldms instead of 100ms\n",
437 /* Correct the lapic counter value */
438 res
= (((u64
) delta
) * pm_100ms
);
439 do_div(res
, deltapm
);
440 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
441 "%lu (%ld)\n", (unsigned long) res
, delta
);
447 /* Calculate the scaled math multiplication factor */
448 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
, 32);
449 lapic_clockevent
.max_delta_ns
=
450 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
451 lapic_clockevent
.min_delta_ns
=
452 clockevent_delta2ns(0xF, &lapic_clockevent
);
454 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
456 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
457 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
458 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
462 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
463 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
465 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
466 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
469 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
471 calibration_result
/ (1000000 / HZ
),
472 calibration_result
% (1000000 / HZ
));
474 local_apic_timer_verify_ok
= 1;
476 /* We trust the pm timer based calibration */
477 if (!pm_referenced
) {
478 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
481 * Setup the apic timer manually
483 levt
->event_handler
= lapic_cal_handler
;
484 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
485 lapic_cal_loops
= -1;
487 /* Let the interrupts run */
490 while(lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
495 /* Stop the lapic timer */
496 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
501 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
502 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
504 /* Check, if the jiffies result is consistent */
505 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
506 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
508 local_apic_timer_verify_ok
= 0;
512 if (!local_apic_timer_verify_ok
) {
514 "APIC timer disabled due to verification failure.\n");
515 /* No broadcast on UP ! */
516 if (num_possible_cpus() == 1)
520 * If nmi_watchdog is set to IO_APIC, we need the
521 * PIT/HPET going. Otherwise register lapic as a dummy
524 if (nmi_watchdog
!= NMI_IO_APIC
)
525 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
528 /* Setup the lapic or request the broadcast */
532 void __devinit
setup_secondary_APIC_clock(void)
538 * The guts of the apic timer interrupt
540 static void local_apic_timer_interrupt(void)
542 int cpu
= smp_processor_id();
543 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
546 * Normally we should not be here till LAPIC has been initialized but
547 * in some cases like kdump, its possible that there is a pending LAPIC
548 * timer interrupt from previous kernel's context and is delivered in
549 * new kernel the moment interrupts are enabled.
551 * Interrupts are enabled early and LAPIC is setup much later, hence
552 * its possible that when we get here evt->event_handler is NULL.
553 * Check for event_handler being NULL and discard the interrupt as
556 if (!evt
->event_handler
) {
558 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
560 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
564 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
566 evt
->event_handler(evt
);
570 * Local APIC timer interrupt. This is the most natural way for doing
571 * local interrupts, but local timer interrupts can be emulated by
572 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
574 * [ if a single-CPU system runs an SMP kernel then we call the local
575 * interrupt as well. Thus we cannot inline the local irq ... ]
578 void fastcall
smp_apic_timer_interrupt(struct pt_regs
*regs
)
580 struct pt_regs
*old_regs
= set_irq_regs(regs
);
583 * NOTE! We'd better ACK the irq immediately,
584 * because timer handling can be slow.
588 * update_process_times() expects us to have done irq_enter().
589 * Besides, if we don't timer interrupts ignore the global
590 * interrupt lock, which is the WrongThing (tm) to do.
593 local_apic_timer_interrupt();
596 set_irq_regs(old_regs
);
599 int setup_profiling_timer(unsigned int multiplier
)
605 * Local APIC start and shutdown
609 * clear_local_APIC - shutdown the local APIC
611 * This is called, when a CPU is disabled and before rebooting, so the state of
612 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
613 * leftovers during boot.
615 void clear_local_APIC(void)
617 int maxlvt
= lapic_get_maxlvt();
621 * Masking an LVT entry can trigger a local APIC error
622 * if the vector is zero. Mask LVTERR first to prevent this.
625 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
626 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
629 * Careful: we have to set masks only first to deassert
630 * any level-triggered sources.
632 v
= apic_read(APIC_LVTT
);
633 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
634 v
= apic_read(APIC_LVT0
);
635 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
636 v
= apic_read(APIC_LVT1
);
637 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
639 v
= apic_read(APIC_LVTPC
);
640 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
643 /* lets not touch this if we didn't frob it */
644 #ifdef CONFIG_X86_MCE_P4THERMAL
646 v
= apic_read(APIC_LVTTHMR
);
647 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
651 * Clean APIC state for other OSs:
653 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
654 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
655 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
657 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
659 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
661 #ifdef CONFIG_X86_MCE_P4THERMAL
663 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
665 /* Integrated APIC (!82489DX) ? */
666 if (lapic_is_integrated()) {
668 /* Clear ESR due to Pentium errata 3AP and 11AP */
669 apic_write(APIC_ESR
, 0);
675 * disable_local_APIC - clear and disable the local APIC
677 void disable_local_APIC(void)
684 * Disable APIC (implies clearing of registers
687 value
= apic_read(APIC_SPIV
);
688 value
&= ~APIC_SPIV_APIC_ENABLED
;
689 apic_write_around(APIC_SPIV
, value
);
692 * When LAPIC was disabled by the BIOS and enabled by the kernel,
693 * restore the disabled state.
695 if (enabled_via_apicbase
) {
698 rdmsr(MSR_IA32_APICBASE
, l
, h
);
699 l
&= ~MSR_IA32_APICBASE_ENABLE
;
700 wrmsr(MSR_IA32_APICBASE
, l
, h
);
705 * If Linux enabled the LAPIC against the BIOS default disable it down before
706 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
707 * not power-off. Additionally clear all LVT entries before disable_local_APIC
708 * for the case where Linux didn't enable the LAPIC.
710 void lapic_shutdown(void)
717 local_irq_save(flags
);
720 if (enabled_via_apicbase
)
721 disable_local_APIC();
723 local_irq_restore(flags
);
727 * This is to verify that we're looking at a real local APIC.
728 * Check these against your board if the CPUs aren't getting
729 * started for no apparent reason.
731 int __init
verify_local_APIC(void)
733 unsigned int reg0
, reg1
;
736 * The version register is read-only in a real APIC.
738 reg0
= apic_read(APIC_LVR
);
739 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
740 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
741 reg1
= apic_read(APIC_LVR
);
742 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
745 * The two version reads above should print the same
746 * numbers. If the second one is different, then we
747 * poke at a non-APIC.
753 * Check if the version looks reasonably.
755 reg1
= GET_APIC_VERSION(reg0
);
756 if (reg1
== 0x00 || reg1
== 0xff)
758 reg1
= lapic_get_maxlvt();
759 if (reg1
< 0x02 || reg1
== 0xff)
763 * The ID register is read/write in a real APIC.
765 reg0
= apic_read(APIC_ID
);
766 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
769 * The next two are just to see if we have sane values.
770 * They're only really relevant if we're in Virtual Wire
771 * compatibility mode, but most boxes are anymore.
773 reg0
= apic_read(APIC_LVT0
);
774 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
775 reg1
= apic_read(APIC_LVT1
);
776 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
782 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
784 void __init
sync_Arb_IDs(void)
787 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
795 apic_wait_icr_idle();
797 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
798 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
803 * An initial setup of the virtual wire mode.
805 void __init
init_bsp_APIC(void)
810 * Don't do the setup now if we have a SMP BIOS as the
811 * through-I/O-APIC virtual wire mode might be active.
813 if (smp_found_config
|| !cpu_has_apic
)
817 * Do not trust the local APIC being empty at bootup.
824 value
= apic_read(APIC_SPIV
);
825 value
&= ~APIC_VECTOR_MASK
;
826 value
|= APIC_SPIV_APIC_ENABLED
;
828 /* This bit is reserved on P4/Xeon and should be cleared */
829 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
830 (boot_cpu_data
.x86
== 15))
831 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
833 value
|= APIC_SPIV_FOCUS_DISABLED
;
834 value
|= SPURIOUS_APIC_VECTOR
;
835 apic_write_around(APIC_SPIV
, value
);
838 * Set up the virtual wire mode.
840 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
842 if (!lapic_is_integrated()) /* 82489DX */
843 value
|= APIC_LVT_LEVEL_TRIGGER
;
844 apic_write_around(APIC_LVT1
, value
);
848 * setup_local_APIC - setup the local APIC
850 void __devinit
setup_local_APIC(void)
852 unsigned long oldvalue
, value
, maxlvt
, integrated
;
855 /* Pound the ESR really hard over the head with a big hammer - mbligh */
857 apic_write(APIC_ESR
, 0);
858 apic_write(APIC_ESR
, 0);
859 apic_write(APIC_ESR
, 0);
860 apic_write(APIC_ESR
, 0);
863 integrated
= lapic_is_integrated();
866 * Double-check whether this APIC is really registered.
868 if (!apic_id_registered())
872 * Intel recommends to set DFR, LDR and TPR before enabling
873 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
874 * document number 292116). So here it goes...
879 * Set Task Priority to 'accept all'. We never change this
882 value
= apic_read(APIC_TASKPRI
);
883 value
&= ~APIC_TPRI_MASK
;
884 apic_write_around(APIC_TASKPRI
, value
);
887 * After a crash, we no longer service the interrupts and a pending
888 * interrupt from previous kernel might still have ISR bit set.
890 * Most probably by now CPU has serviced that pending interrupt and
891 * it might not have done the ack_APIC_irq() because it thought,
892 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
893 * does not clear the ISR bit and cpu thinks it has already serivced
894 * the interrupt. Hence a vector might get locked. It was noticed
895 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
897 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
898 value
= apic_read(APIC_ISR
+ i
*0x10);
899 for (j
= 31; j
>= 0; j
--) {
906 * Now that we are all set up, enable the APIC
908 value
= apic_read(APIC_SPIV
);
909 value
&= ~APIC_VECTOR_MASK
;
913 value
|= APIC_SPIV_APIC_ENABLED
;
916 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
917 * certain networking cards. If high frequency interrupts are
918 * happening on a particular IOAPIC pin, plus the IOAPIC routing
919 * entry is masked/unmasked at a high rate as well then sooner or
920 * later IOAPIC line gets 'stuck', no more interrupts are received
921 * from the device. If focus CPU is disabled then the hang goes
924 * [ This bug can be reproduced easily with a level-triggered
925 * PCI Ne2000 networking cards and PII/PIII processors, dual
929 * Actually disabling the focus CPU check just makes the hang less
930 * frequent as it makes the interrupt distributon model be more
931 * like LRU than MRU (the short-term load is more even across CPUs).
932 * See also the comment in end_level_ioapic_irq(). --macro
935 /* Enable focus processor (bit==0) */
936 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
939 * Set spurious IRQ vector
941 value
|= SPURIOUS_APIC_VECTOR
;
942 apic_write_around(APIC_SPIV
, value
);
947 * set up through-local-APIC on the BP's LINT0. This is not
948 * strictly necessery in pure symmetric-IO mode, but sometimes
949 * we delegate interrupts to the 8259A.
952 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
954 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
955 if (!smp_processor_id() && (pic_mode
|| !value
)) {
956 value
= APIC_DM_EXTINT
;
957 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
960 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
961 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
964 apic_write_around(APIC_LVT0
, value
);
967 * only the BP should see the LINT1 NMI signal, obviously.
969 if (!smp_processor_id())
972 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
973 if (!integrated
) /* 82489DX */
974 value
|= APIC_LVT_LEVEL_TRIGGER
;
975 apic_write_around(APIC_LVT1
, value
);
977 if (integrated
&& !esr_disable
) { /* !82489DX */
978 maxlvt
= lapic_get_maxlvt();
979 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
980 apic_write(APIC_ESR
, 0);
981 oldvalue
= apic_read(APIC_ESR
);
983 /* enables sending errors */
984 value
= ERROR_APIC_VECTOR
;
985 apic_write_around(APIC_LVTERR
, value
);
987 * spec says clear errors after enabling vector.
990 apic_write(APIC_ESR
, 0);
991 value
= apic_read(APIC_ESR
);
992 if (value
!= oldvalue
)
993 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
994 "vector: 0x%08lx after: 0x%08lx\n",
999 * Something untraceble is creating bad interrupts on
1000 * secondary quads ... for the moment, just leave the
1001 * ESR disabled - we can't do anything useful with the
1002 * errors anyway - mbligh
1004 printk(KERN_INFO
"Leaving ESR disabled.\n");
1006 printk(KERN_INFO
"No ESR for 82489DX.\n");
1009 /* Disable the local apic timer */
1010 value
= apic_read(APIC_LVTT
);
1011 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1012 apic_write_around(APIC_LVTT
, value
);
1014 setup_apic_nmi_watchdog(NULL
);
1019 * Detect and initialize APIC
1021 static int __init
detect_init_APIC (void)
1025 /* Disabled by kernel option? */
1026 if (enable_local_apic
< 0)
1029 switch (boot_cpu_data
.x86_vendor
) {
1030 case X86_VENDOR_AMD
:
1031 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1032 (boot_cpu_data
.x86
== 15))
1035 case X86_VENDOR_INTEL
:
1036 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1037 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1044 if (!cpu_has_apic
) {
1046 * Over-ride BIOS and try to enable the local APIC only if
1047 * "lapic" specified.
1049 if (enable_local_apic
<= 0) {
1050 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1051 "you can enable it with \"lapic\"\n");
1055 * Some BIOSes disable the local APIC in the APIC_BASE
1056 * MSR. This can only be done in software for Intel P6 or later
1057 * and AMD K7 (Model > 1) or later.
1059 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1060 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1062 "Local APIC disabled by BIOS -- reenabling.\n");
1063 l
&= ~MSR_IA32_APICBASE_BASE
;
1064 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1065 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1066 enabled_via_apicbase
= 1;
1070 * The APIC feature bit should now be enabled
1073 features
= cpuid_edx(1);
1074 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1075 printk(KERN_WARNING
"Could not enable APIC!\n");
1078 set_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1079 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1081 /* The BIOS may have set up the APIC at some other address */
1082 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1083 if (l
& MSR_IA32_APICBASE_ENABLE
)
1084 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1086 if (nmi_watchdog
!= NMI_NONE
)
1087 nmi_watchdog
= NMI_LOCAL_APIC
;
1089 printk(KERN_INFO
"Found and enabled local APIC!\n");
1096 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1101 * init_apic_mappings - initialize APIC mappings
1103 void __init
init_apic_mappings(void)
1105 unsigned long apic_phys
;
1108 * If no local APIC can be found then set up a fake all
1109 * zeroes page to simulate the local APIC and another
1110 * one for the IO-APIC.
1112 if (!smp_found_config
&& detect_init_APIC()) {
1113 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1114 apic_phys
= __pa(apic_phys
);
1116 apic_phys
= mp_lapic_addr
;
1118 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1119 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1123 * Fetch the APIC ID of the BSP in case we have a
1124 * default configuration (or the MP table is broken).
1126 if (boot_cpu_physical_apicid
== -1U)
1127 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1129 #ifdef CONFIG_X86_IO_APIC
1131 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
1134 for (i
= 0; i
< nr_ioapics
; i
++) {
1135 if (smp_found_config
) {
1136 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
1139 "WARNING: bogus zero IO-APIC "
1140 "address found in MPTABLE, "
1141 "disabling IO/APIC support!\n");
1142 smp_found_config
= 0;
1143 skip_ioapic_setup
= 1;
1144 goto fake_ioapic_page
;
1148 ioapic_phys
= (unsigned long)
1149 alloc_bootmem_pages(PAGE_SIZE
);
1150 ioapic_phys
= __pa(ioapic_phys
);
1152 set_fixmap_nocache(idx
, ioapic_phys
);
1153 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
1154 __fix_to_virt(idx
), ioapic_phys
);
1162 * This initializes the IO-APIC and APIC hardware if this is
1165 int __init
APIC_init_uniprocessor (void)
1167 if (enable_local_apic
< 0)
1168 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1170 if (!smp_found_config
&& !cpu_has_apic
)
1174 * Complain if the BIOS pretends there is one.
1176 if (!cpu_has_apic
&&
1177 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1178 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1179 boot_cpu_physical_apicid
);
1180 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1184 verify_local_APIC();
1189 * Hack: In case of kdump, after a crash, kernel might be booting
1190 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1191 * might be zero if read from MP tables. Get it from LAPIC.
1193 #ifdef CONFIG_CRASH_DUMP
1194 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1196 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
1200 #ifdef CONFIG_X86_IO_APIC
1201 if (smp_found_config
)
1202 if (!skip_ioapic_setup
&& nr_ioapics
)
1211 * APIC command line parameters
1213 static int __init
parse_lapic(char *arg
)
1215 enable_local_apic
= 1;
1218 early_param("lapic", parse_lapic
);
1220 static int __init
parse_nolapic(char *arg
)
1222 enable_local_apic
= -1;
1223 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1226 early_param("nolapic", parse_nolapic
);
1228 static int __init
parse_disable_lapic_timer(char *arg
)
1230 local_apic_timer_disabled
= 1;
1233 early_param("nolapic_timer", parse_disable_lapic_timer
);
1235 static int __init
apic_set_verbosity(char *str
)
1237 if (strcmp("debug", str
) == 0)
1238 apic_verbosity
= APIC_DEBUG
;
1239 else if (strcmp("verbose", str
) == 0)
1240 apic_verbosity
= APIC_VERBOSE
;
1244 __setup("apic=", apic_set_verbosity
);
1248 * Local APIC interrupts
1252 * This interrupt should _never_ happen with our APIC/SMP architecture
1254 void smp_spurious_interrupt(struct pt_regs
*regs
)
1260 * Check if this really is a spurious interrupt and ACK it
1261 * if it is a vectored one. Just in case...
1262 * Spurious interrupts should not be ACKed.
1264 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1265 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1268 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1269 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1270 "should never happen.\n", smp_processor_id());
1275 * This interrupt should never happen with our APIC/SMP architecture
1277 void smp_error_interrupt(struct pt_regs
*regs
)
1279 unsigned long v
, v1
;
1282 /* First tickle the hardware, only then report what went on. -- REW */
1283 v
= apic_read(APIC_ESR
);
1284 apic_write(APIC_ESR
, 0);
1285 v1
= apic_read(APIC_ESR
);
1287 atomic_inc(&irq_err_count
);
1289 /* Here is what the APIC error bits mean:
1292 2: Send accept error
1293 3: Receive accept error
1295 5: Send illegal vector
1296 6: Received illegal vector
1297 7: Illegal register address
1299 printk (KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1300 smp_processor_id(), v
, v1
);
1305 * Initialize APIC interrupts
1307 void __init
apic_intr_init(void)
1312 /* self generated IPI for local APIC timer */
1313 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
1315 /* IPI vectors for APIC spurious and error interrupts */
1316 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
1317 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
1319 /* thermal monitor LVT interrupt */
1320 #ifdef CONFIG_X86_MCE_P4THERMAL
1321 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
1326 * connect_bsp_APIC - attach the APIC to the interrupt system
1328 void __init
connect_bsp_APIC(void)
1332 * Do not trust the local APIC being empty at bootup.
1336 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1337 * local APIC to INT and NMI lines.
1339 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1340 "enabling APIC mode.\n");
1348 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1349 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1351 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1354 void disconnect_bsp_APIC(int virt_wire_setup
)
1358 * Put the board back into PIC mode (has an effect only on
1359 * certain older boards). Note that APIC interrupts, including
1360 * IPIs, won't work beyond this point! The only exception are
1363 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1364 "entering PIC mode.\n");
1368 /* Go back to Virtual Wire compatibility mode */
1369 unsigned long value
;
1371 /* For the spurious interrupt use vector F, and enable it */
1372 value
= apic_read(APIC_SPIV
);
1373 value
&= ~APIC_VECTOR_MASK
;
1374 value
|= APIC_SPIV_APIC_ENABLED
;
1376 apic_write_around(APIC_SPIV
, value
);
1378 if (!virt_wire_setup
) {
1380 * For LVT0 make it edge triggered, active high,
1381 * external and enabled
1383 value
= apic_read(APIC_LVT0
);
1384 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1385 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1386 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1387 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1388 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1389 apic_write_around(APIC_LVT0
, value
);
1392 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
1396 * For LVT1 make it edge triggered, active high, nmi and
1399 value
= apic_read(APIC_LVT1
);
1401 APIC_MODE_MASK
| APIC_SEND_PENDING
|
1402 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1403 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1404 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1405 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1406 apic_write_around(APIC_LVT1
, value
);
1417 /* r/w apic fields */
1418 unsigned int apic_id
;
1419 unsigned int apic_taskpri
;
1420 unsigned int apic_ldr
;
1421 unsigned int apic_dfr
;
1422 unsigned int apic_spiv
;
1423 unsigned int apic_lvtt
;
1424 unsigned int apic_lvtpc
;
1425 unsigned int apic_lvt0
;
1426 unsigned int apic_lvt1
;
1427 unsigned int apic_lvterr
;
1428 unsigned int apic_tmict
;
1429 unsigned int apic_tdcr
;
1430 unsigned int apic_thmr
;
1433 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1435 unsigned long flags
;
1438 if (!apic_pm_state
.active
)
1441 maxlvt
= lapic_get_maxlvt();
1443 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1444 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1445 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1446 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1447 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1448 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1450 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1451 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1452 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1453 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1454 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1455 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1456 #ifdef CONFIG_X86_MCE_P4THERMAL
1458 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1461 local_irq_save(flags
);
1462 disable_local_APIC();
1463 local_irq_restore(flags
);
1467 static int lapic_resume(struct sys_device
*dev
)
1470 unsigned long flags
;
1473 if (!apic_pm_state
.active
)
1476 maxlvt
= lapic_get_maxlvt();
1478 local_irq_save(flags
);
1481 * Make sure the APICBASE points to the right address
1483 * FIXME! This will be wrong if we ever support suspend on
1484 * SMP! We'll need to do this as part of the CPU restore!
1486 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1487 l
&= ~MSR_IA32_APICBASE_BASE
;
1488 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1489 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1491 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1492 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1493 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1494 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1495 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1496 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1497 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1498 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1499 #ifdef CONFIG_X86_MCE_P4THERMAL
1501 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1504 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1505 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1506 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1507 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1508 apic_write(APIC_ESR
, 0);
1509 apic_read(APIC_ESR
);
1510 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1511 apic_write(APIC_ESR
, 0);
1512 apic_read(APIC_ESR
);
1513 local_irq_restore(flags
);
1518 * This device has no shutdown method - fully functioning local APICs
1519 * are needed on every CPU up until machine_halt/restart/poweroff.
1522 static struct sysdev_class lapic_sysclass
= {
1523 set_kset_name("lapic"),
1524 .resume
= lapic_resume
,
1525 .suspend
= lapic_suspend
,
1528 static struct sys_device device_lapic
= {
1530 .cls
= &lapic_sysclass
,
1533 static void __devinit
apic_pm_activate(void)
1535 apic_pm_state
.active
= 1;
1538 static int __init
init_lapic_sysfs(void)
1544 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1546 error
= sysdev_class_register(&lapic_sysclass
);
1548 error
= sysdev_register(&device_lapic
);
1551 device_initcall(init_lapic_sysfs
);
1553 #else /* CONFIG_PM */
1555 static void apic_pm_activate(void) { }
1557 #endif /* CONFIG_PM */