2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/bootmem.h>
23 #include <linux/smp_lock.h>
24 #include <linux/interrupt.h>
25 #include <linux/mc146818rtc.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/sysdev.h>
28 #include <linux/cpu.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/arch_hooks.h>
38 #include <asm/i8253.h>
40 #include <mach_apic.h>
41 #include <mach_apicdef.h>
47 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
48 * IPIs in place of local APIC timers
50 static cpumask_t timer_bcast_ipi
;
53 * Knob to control our willingness to enable the local APIC.
55 int enable_local_apic __initdata
= 0; /* -1=force-disable, +1=force-enable */
63 static void apic_pm_activate(void);
66 * 'what should we do if we get a hw irq event on an illegal vector'.
67 * each architecture has to answer this themselves.
69 void ack_bad_irq(unsigned int irq
)
71 printk("unexpected IRQ trap at vector %02x\n", irq
);
73 * Currently unexpected vectors happen only on SMP and APIC.
74 * We _must_ ack these because every local APIC has only N
75 * irq slots per priority level, and a 'hanging, unacked' IRQ
76 * holds up an irq slot - in excessive cases (when multiple
77 * unexpected vectors occur) that might lock up the APIC
79 * But only ack when the APIC is enabled -AK
85 void __init
apic_intr_init(void)
90 /* self generated IPI for local APIC timer */
91 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
93 /* IPI vectors for APIC spurious and error interrupts */
94 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
95 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
97 /* thermal monitor LVT interrupt */
98 #ifdef CONFIG_X86_MCE_P4THERMAL
99 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
103 /* Using APIC to generate smp_local_timer_interrupt? */
104 int using_apic_timer
= 0;
106 static int enabled_via_apicbase
;
108 void enable_NMI_through_LVT0 (void * dummy
)
112 ver
= apic_read(APIC_LVR
);
113 ver
= GET_APIC_VERSION(ver
);
114 v
= APIC_DM_NMI
; /* unmask and set to NMI */
115 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
116 v
|= APIC_LVT_LEVEL_TRIGGER
;
117 apic_write_around(APIC_LVT0
, v
);
120 int get_physical_broadcast(void)
122 unsigned int lvr
, version
;
123 lvr
= apic_read(APIC_LVR
);
124 version
= GET_APIC_VERSION(lvr
);
125 if (!APIC_INTEGRATED(version
) || version
>= 0x14)
133 unsigned int v
, ver
, maxlvt
;
135 v
= apic_read(APIC_LVR
);
136 ver
= GET_APIC_VERSION(v
);
137 /* 82489DXs do not report # of LVT entries. */
138 maxlvt
= APIC_INTEGRATED(ver
) ? GET_APIC_MAXLVT(v
) : 2;
142 void clear_local_APIC(void)
147 maxlvt
= get_maxlvt();
150 * Masking an LVT entry on a P6 can trigger a local APIC error
151 * if the vector is zero. Mask LVTERR first to prevent this.
154 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
155 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
158 * Careful: we have to set masks only first to deassert
159 * any level-triggered sources.
161 v
= apic_read(APIC_LVTT
);
162 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
163 v
= apic_read(APIC_LVT0
);
164 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
165 v
= apic_read(APIC_LVT1
);
166 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
168 v
= apic_read(APIC_LVTPC
);
169 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
172 /* lets not touch this if we didn't frob it */
173 #ifdef CONFIG_X86_MCE_P4THERMAL
175 v
= apic_read(APIC_LVTTHMR
);
176 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
180 * Clean APIC state for other OSs:
182 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
183 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
184 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
186 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
188 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
190 #ifdef CONFIG_X86_MCE_P4THERMAL
192 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
194 v
= GET_APIC_VERSION(apic_read(APIC_LVR
));
195 if (APIC_INTEGRATED(v
)) { /* !82489DX */
196 if (maxlvt
> 3) /* Due to Pentium errata 3AP and 11AP. */
197 apic_write(APIC_ESR
, 0);
202 void __init
connect_bsp_APIC(void)
206 * Do not trust the local APIC being empty at bootup.
210 * PIC mode, enable APIC mode in the IMCR, i.e.
211 * connect BSP's local APIC to INT and NMI lines.
213 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
214 "enabling APIC mode.\n");
221 void disconnect_bsp_APIC(int virt_wire_setup
)
225 * Put the board back into PIC mode (has an effect
226 * only on certain older boards). Note that APIC
227 * interrupts, including IPIs, won't work beyond
228 * this point! The only exception are INIT IPIs.
230 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
231 "entering PIC mode.\n");
236 /* Go back to Virtual Wire compatibility mode */
239 /* For the spurious interrupt use vector F, and enable it */
240 value
= apic_read(APIC_SPIV
);
241 value
&= ~APIC_VECTOR_MASK
;
242 value
|= APIC_SPIV_APIC_ENABLED
;
244 apic_write_around(APIC_SPIV
, value
);
246 if (!virt_wire_setup
) {
247 /* For LVT0 make it edge triggered, active high, external and enabled */
248 value
= apic_read(APIC_LVT0
);
249 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
250 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
251 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
252 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
253 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
254 apic_write_around(APIC_LVT0
, value
);
258 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
261 /* For LVT1 make it edge triggered, active high, nmi and enabled */
262 value
= apic_read(APIC_LVT1
);
264 APIC_MODE_MASK
| APIC_SEND_PENDING
|
265 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
266 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
267 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
268 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
269 apic_write_around(APIC_LVT1
, value
);
273 void disable_local_APIC(void)
280 * Disable APIC (implies clearing of registers
283 value
= apic_read(APIC_SPIV
);
284 value
&= ~APIC_SPIV_APIC_ENABLED
;
285 apic_write_around(APIC_SPIV
, value
);
287 if (enabled_via_apicbase
) {
289 rdmsr(MSR_IA32_APICBASE
, l
, h
);
290 l
&= ~MSR_IA32_APICBASE_ENABLE
;
291 wrmsr(MSR_IA32_APICBASE
, l
, h
);
296 * This is to verify that we're looking at a real local APIC.
297 * Check these against your board if the CPUs aren't getting
298 * started for no apparent reason.
300 int __init
verify_local_APIC(void)
302 unsigned int reg0
, reg1
;
305 * The version register is read-only in a real APIC.
307 reg0
= apic_read(APIC_LVR
);
308 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
309 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
310 reg1
= apic_read(APIC_LVR
);
311 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
314 * The two version reads above should print the same
315 * numbers. If the second one is different, then we
316 * poke at a non-APIC.
322 * Check if the version looks reasonably.
324 reg1
= GET_APIC_VERSION(reg0
);
325 if (reg1
== 0x00 || reg1
== 0xff)
328 if (reg1
< 0x02 || reg1
== 0xff)
332 * The ID register is read/write in a real APIC.
334 reg0
= apic_read(APIC_ID
);
335 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
338 * The next two are just to see if we have sane values.
339 * They're only really relevant if we're in Virtual Wire
340 * compatibility mode, but most boxes are anymore.
342 reg0
= apic_read(APIC_LVT0
);
343 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
344 reg1
= apic_read(APIC_LVT1
);
345 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
350 void __init
sync_Arb_IDs(void)
352 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
353 unsigned int ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
354 if (ver
>= 0x14) /* P4 or higher */
359 apic_wait_icr_idle();
361 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
362 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
366 extern void __error_in_apic_c (void);
369 * An initial setup of the virtual wire mode.
371 void __init
init_bsp_APIC(void)
373 unsigned long value
, ver
;
376 * Don't do the setup now if we have a SMP BIOS as the
377 * through-I/O-APIC virtual wire mode might be active.
379 if (smp_found_config
|| !cpu_has_apic
)
382 value
= apic_read(APIC_LVR
);
383 ver
= GET_APIC_VERSION(value
);
386 * Do not trust the local APIC being empty at bootup.
393 value
= apic_read(APIC_SPIV
);
394 value
&= ~APIC_VECTOR_MASK
;
395 value
|= APIC_SPIV_APIC_ENABLED
;
397 /* This bit is reserved on P4/Xeon and should be cleared */
398 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 15))
399 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
401 value
|= APIC_SPIV_FOCUS_DISABLED
;
402 value
|= SPURIOUS_APIC_VECTOR
;
403 apic_write_around(APIC_SPIV
, value
);
406 * Set up the virtual wire mode.
408 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
410 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
411 value
|= APIC_LVT_LEVEL_TRIGGER
;
412 apic_write_around(APIC_LVT1
, value
);
415 void __devinit
setup_local_APIC(void)
417 unsigned long oldvalue
, value
, ver
, maxlvt
;
420 /* Pound the ESR really hard over the head with a big hammer - mbligh */
422 apic_write(APIC_ESR
, 0);
423 apic_write(APIC_ESR
, 0);
424 apic_write(APIC_ESR
, 0);
425 apic_write(APIC_ESR
, 0);
428 value
= apic_read(APIC_LVR
);
429 ver
= GET_APIC_VERSION(value
);
431 if ((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f)
435 * Double-check whether this APIC is really registered.
437 if (!apic_id_registered())
441 * Intel recommends to set DFR, LDR and TPR before enabling
442 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
443 * document number 292116). So here it goes...
448 * Set Task Priority to 'accept all'. We never change this
451 value
= apic_read(APIC_TASKPRI
);
452 value
&= ~APIC_TPRI_MASK
;
453 apic_write_around(APIC_TASKPRI
, value
);
456 * After a crash, we no longer service the interrupts and a pending
457 * interrupt from previous kernel might still have ISR bit set.
459 * Most probably by now CPU has serviced that pending interrupt and
460 * it might not have done the ack_APIC_irq() because it thought,
461 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
462 * does not clear the ISR bit and cpu thinks it has already serivced
463 * the interrupt. Hence a vector might get locked. It was noticed
464 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
466 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
467 value
= apic_read(APIC_ISR
+ i
*0x10);
468 for (j
= 31; j
>= 0; j
--) {
475 * Now that we are all set up, enable the APIC
477 value
= apic_read(APIC_SPIV
);
478 value
&= ~APIC_VECTOR_MASK
;
482 value
|= APIC_SPIV_APIC_ENABLED
;
485 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
486 * certain networking cards. If high frequency interrupts are
487 * happening on a particular IOAPIC pin, plus the IOAPIC routing
488 * entry is masked/unmasked at a high rate as well then sooner or
489 * later IOAPIC line gets 'stuck', no more interrupts are received
490 * from the device. If focus CPU is disabled then the hang goes
493 * [ This bug can be reproduced easily with a level-triggered
494 * PCI Ne2000 networking cards and PII/PIII processors, dual
498 * Actually disabling the focus CPU check just makes the hang less
499 * frequent as it makes the interrupt distributon model be more
500 * like LRU than MRU (the short-term load is more even across CPUs).
501 * See also the comment in end_level_ioapic_irq(). --macro
504 /* Enable focus processor (bit==0) */
505 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
507 /* Disable focus processor (bit==1) */
508 value
|= APIC_SPIV_FOCUS_DISABLED
;
511 * Set spurious IRQ vector
513 value
|= SPURIOUS_APIC_VECTOR
;
514 apic_write_around(APIC_SPIV
, value
);
519 * set up through-local-APIC on the BP's LINT0. This is not
520 * strictly necessery in pure symmetric-IO mode, but sometimes
521 * we delegate interrupts to the 8259A.
524 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
526 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
527 if (!smp_processor_id() && (pic_mode
|| !value
)) {
528 value
= APIC_DM_EXTINT
;
529 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
532 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
533 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
536 apic_write_around(APIC_LVT0
, value
);
539 * only the BP should see the LINT1 NMI signal, obviously.
541 if (!smp_processor_id())
544 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
545 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
546 value
|= APIC_LVT_LEVEL_TRIGGER
;
547 apic_write_around(APIC_LVT1
, value
);
549 if (APIC_INTEGRATED(ver
) && !esr_disable
) { /* !82489DX */
550 maxlvt
= get_maxlvt();
551 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
552 apic_write(APIC_ESR
, 0);
553 oldvalue
= apic_read(APIC_ESR
);
555 value
= ERROR_APIC_VECTOR
; // enables sending errors
556 apic_write_around(APIC_LVTERR
, value
);
558 * spec says clear errors after enabling vector.
561 apic_write(APIC_ESR
, 0);
562 value
= apic_read(APIC_ESR
);
563 if (value
!= oldvalue
)
564 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
565 "vector: 0x%08lx after: 0x%08lx\n",
570 * Something untraceble is creating bad interrupts on
571 * secondary quads ... for the moment, just leave the
572 * ESR disabled - we can't do anything useful with the
573 * errors anyway - mbligh
575 printk("Leaving ESR disabled.\n");
577 printk("No ESR for 82489DX.\n");
580 if (nmi_watchdog
== NMI_LOCAL_APIC
)
581 setup_apic_nmi_watchdog();
586 * If Linux enabled the LAPIC against the BIOS default
587 * disable it down before re-entering the BIOS on shutdown.
588 * Otherwise the BIOS may get confused and not power-off.
589 * Additionally clear all LVT entries before disable_local_APIC
590 * for the case where Linux didn't enable the LAPIC.
592 void lapic_shutdown(void)
599 local_irq_save(flags
);
602 if (enabled_via_apicbase
)
603 disable_local_APIC();
605 local_irq_restore(flags
);
612 /* r/w apic fields */
613 unsigned int apic_id
;
614 unsigned int apic_taskpri
;
615 unsigned int apic_ldr
;
616 unsigned int apic_dfr
;
617 unsigned int apic_spiv
;
618 unsigned int apic_lvtt
;
619 unsigned int apic_lvtpc
;
620 unsigned int apic_lvt0
;
621 unsigned int apic_lvt1
;
622 unsigned int apic_lvterr
;
623 unsigned int apic_tmict
;
624 unsigned int apic_tdcr
;
625 unsigned int apic_thmr
;
628 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
632 if (!apic_pm_state
.active
)
635 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
636 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
637 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
638 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
639 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
640 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
641 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
642 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
643 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
644 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
645 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
646 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
647 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
649 local_irq_save(flags
);
650 disable_local_APIC();
651 local_irq_restore(flags
);
655 static int lapic_resume(struct sys_device
*dev
)
660 if (!apic_pm_state
.active
)
663 local_irq_save(flags
);
666 * Make sure the APICBASE points to the right address
668 * FIXME! This will be wrong if we ever support suspend on
669 * SMP! We'll need to do this as part of the CPU restore!
671 rdmsr(MSR_IA32_APICBASE
, l
, h
);
672 l
&= ~MSR_IA32_APICBASE_BASE
;
673 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
674 wrmsr(MSR_IA32_APICBASE
, l
, h
);
676 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
677 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
678 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
679 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
680 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
681 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
682 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
683 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
684 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
685 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
686 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
687 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
688 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
689 apic_write(APIC_ESR
, 0);
691 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
692 apic_write(APIC_ESR
, 0);
694 local_irq_restore(flags
);
699 * This device has no shutdown method - fully functioning local APICs
700 * are needed on every CPU up until machine_halt/restart/poweroff.
703 static struct sysdev_class lapic_sysclass
= {
704 set_kset_name("lapic"),
705 .resume
= lapic_resume
,
706 .suspend
= lapic_suspend
,
709 static struct sys_device device_lapic
= {
711 .cls
= &lapic_sysclass
,
714 static void __devinit
apic_pm_activate(void)
716 apic_pm_state
.active
= 1;
719 static int __init
init_lapic_sysfs(void)
725 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
727 error
= sysdev_class_register(&lapic_sysclass
);
729 error
= sysdev_register(&device_lapic
);
732 device_initcall(init_lapic_sysfs
);
734 #else /* CONFIG_PM */
736 static void apic_pm_activate(void) { }
738 #endif /* CONFIG_PM */
741 * Detect and enable local APICs on non-SMP boards.
742 * Original code written by Keir Fraser.
745 static int __init
apic_set_verbosity(char *str
)
747 if (strcmp("debug", str
) == 0)
748 apic_verbosity
= APIC_DEBUG
;
749 else if (strcmp("verbose", str
) == 0)
750 apic_verbosity
= APIC_VERBOSE
;
752 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
753 " use apic=verbose or apic=debug\n", str
);
758 __setup("apic=", apic_set_verbosity
);
760 static int __init
detect_init_APIC (void)
764 /* Disabled by kernel option? */
765 if (enable_local_apic
< 0)
768 switch (boot_cpu_data
.x86_vendor
) {
770 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
771 (boot_cpu_data
.x86
== 15))
774 case X86_VENDOR_INTEL
:
775 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
776 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
785 * Over-ride BIOS and try to enable the local
786 * APIC only if "lapic" specified.
788 if (enable_local_apic
<= 0) {
789 printk("Local APIC disabled by BIOS -- "
790 "you can enable it with \"lapic\"\n");
794 * Some BIOSes disable the local APIC in the
795 * APIC_BASE MSR. This can only be done in
796 * software for Intel P6 or later and AMD K7
797 * (Model > 1) or later.
799 rdmsr(MSR_IA32_APICBASE
, l
, h
);
800 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
801 printk("Local APIC disabled by BIOS -- reenabling.\n");
802 l
&= ~MSR_IA32_APICBASE_BASE
;
803 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
804 wrmsr(MSR_IA32_APICBASE
, l
, h
);
805 enabled_via_apicbase
= 1;
809 * The APIC feature bit should now be enabled
812 features
= cpuid_edx(1);
813 if (!(features
& (1 << X86_FEATURE_APIC
))) {
814 printk("Could not enable APIC!\n");
817 set_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
818 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
820 /* The BIOS may have set up the APIC at some other address */
821 rdmsr(MSR_IA32_APICBASE
, l
, h
);
822 if (l
& MSR_IA32_APICBASE_ENABLE
)
823 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
825 if (nmi_watchdog
!= NMI_NONE
)
826 nmi_watchdog
= NMI_LOCAL_APIC
;
828 printk("Found and enabled local APIC!\n");
835 printk("No local APIC present or hardware disabled\n");
839 void __init
init_apic_mappings(void)
841 unsigned long apic_phys
;
844 * If no local APIC can be found then set up a fake all
845 * zeroes page to simulate the local APIC and another
846 * one for the IO-APIC.
848 if (!smp_found_config
&& detect_init_APIC()) {
849 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
850 apic_phys
= __pa(apic_phys
);
852 apic_phys
= mp_lapic_addr
;
854 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
855 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
859 * Fetch the APIC ID of the BSP in case we have a
860 * default configuration (or the MP table is broken).
862 if (boot_cpu_physical_apicid
== -1U)
863 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
865 #ifdef CONFIG_X86_IO_APIC
867 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
870 for (i
= 0; i
< nr_ioapics
; i
++) {
871 if (smp_found_config
) {
872 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
875 "WARNING: bogus zero IO-APIC "
876 "address found in MPTABLE, "
877 "disabling IO/APIC support!\n");
878 smp_found_config
= 0;
879 skip_ioapic_setup
= 1;
880 goto fake_ioapic_page
;
884 ioapic_phys
= (unsigned long)
885 alloc_bootmem_pages(PAGE_SIZE
);
886 ioapic_phys
= __pa(ioapic_phys
);
888 set_fixmap_nocache(idx
, ioapic_phys
);
889 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
890 __fix_to_virt(idx
), ioapic_phys
);
898 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
899 * per second. We assume that the caller has already set up the local
902 * The APIC timer is not exactly sync with the external timer chip, it
903 * closely follows bus clocks.
907 * The timer chip is already set up at HZ interrupts per second here,
908 * but we do not accept timer interrupts yet. We only allow the BP
911 static unsigned int __devinit
get_8254_timer_count(void)
917 spin_lock_irqsave(&i8253_lock
, flags
);
919 outb_p(0x00, PIT_MODE
);
920 count
= inb_p(PIT_CH0
);
921 count
|= inb_p(PIT_CH0
) << 8;
923 spin_unlock_irqrestore(&i8253_lock
, flags
);
928 /* next tick in 8254 can be caught by catching timer wraparound */
929 static void __devinit
wait_8254_wraparound(void)
931 unsigned int curr_count
, prev_count
;
933 curr_count
= get_8254_timer_count();
935 prev_count
= curr_count
;
936 curr_count
= get_8254_timer_count();
938 /* workaround for broken Mercury/Neptune */
939 if (prev_count
>= curr_count
+ 0x100)
940 curr_count
= get_8254_timer_count();
942 } while (prev_count
>= curr_count
);
946 * Default initialization for 8254 timers. If we use other timers like HPET,
947 * we override this later
949 void (*wait_timer_tick
)(void) __devinitdata
= wait_8254_wraparound
;
952 * This function sets up the local APIC timer, with a timeout of
953 * 'clocks' APIC bus clock. During calibration we actually call
954 * this function twice on the boot CPU, once with a bogus timeout
955 * value, second time for real. The other (noncalibrating) CPUs
956 * call this function only once, with the real, calibrated value.
958 * We do reads before writes even if unnecessary, to get around the
959 * P5 APIC double write bug.
962 #define APIC_DIVISOR 16
964 static void __setup_APIC_LVTT(unsigned int clocks
)
966 unsigned int lvtt_value
, tmp_value
, ver
;
967 int cpu
= smp_processor_id();
969 ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
970 lvtt_value
= APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
971 if (!APIC_INTEGRATED(ver
))
972 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
974 if (cpu_isset(cpu
, timer_bcast_ipi
))
975 lvtt_value
|= APIC_LVT_MASKED
;
977 apic_write_around(APIC_LVTT
, lvtt_value
);
982 tmp_value
= apic_read(APIC_TDCR
);
983 apic_write_around(APIC_TDCR
, (tmp_value
984 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
987 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
990 static void __devinit
setup_APIC_timer(unsigned int clocks
)
994 local_irq_save(flags
);
997 * Wait for IRQ0's slice:
1001 __setup_APIC_LVTT(clocks
);
1003 local_irq_restore(flags
);
1007 * In this function we calibrate APIC bus clocks to the external
1008 * timer. Unfortunately we cannot use jiffies and the timer irq
1009 * to calibrate, since some later bootup code depends on getting
1010 * the first irq? Ugh.
1012 * We want to do the calibration only once since we
1013 * want to have local timer irqs syncron. CPUs connected
1014 * by the same APIC bus have the very same bus frequency.
1015 * And we want to have irqs off anyways, no accidental
1016 * APIC irq that way.
1019 static int __init
calibrate_APIC_clock(void)
1021 unsigned long long t1
= 0, t2
= 0;
1025 const int LOOPS
= HZ
/10;
1027 apic_printk(APIC_VERBOSE
, "calibrating APIC timer ...\n");
1030 * Put whatever arbitrary (but long enough) timeout
1031 * value into the APIC clock, we just want to get the
1032 * counter running for calibration.
1034 __setup_APIC_LVTT(1000000000);
1037 * The timer chip counts down to zero. Let's wait
1038 * for a wraparound to start exact measurement:
1039 * (the current tick might have been already half done)
1045 * We wrapped around just now. Let's start:
1049 tt1
= apic_read(APIC_TMCCT
);
1052 * Let's wait LOOPS wraprounds:
1054 for (i
= 0; i
< LOOPS
; i
++)
1057 tt2
= apic_read(APIC_TMCCT
);
1062 * The APIC bus clock counter is 32 bits only, it
1063 * might have overflown, but note that we use signed
1064 * longs, thus no extra care needed.
1066 * underflown to be exact, as the timer counts down ;)
1069 result
= (tt1
-tt2
)*APIC_DIVISOR
/LOOPS
;
1072 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
1074 ((long)(t2
-t1
)/LOOPS
)/(1000000/HZ
),
1075 ((long)(t2
-t1
)/LOOPS
)%(1000000/HZ
));
1077 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
1079 result
/(1000000/HZ
),
1080 result
%(1000000/HZ
));
1085 static unsigned int calibration_result
;
1087 void __init
setup_boot_APIC_clock(void)
1089 unsigned long flags
;
1090 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n");
1091 using_apic_timer
= 1;
1093 local_irq_save(flags
);
1095 calibration_result
= calibrate_APIC_clock();
1097 * Now set up the timer for real.
1099 setup_APIC_timer(calibration_result
);
1101 local_irq_restore(flags
);
1104 void __devinit
setup_secondary_APIC_clock(void)
1106 setup_APIC_timer(calibration_result
);
1109 void disable_APIC_timer(void)
1111 if (using_apic_timer
) {
1114 v
= apic_read(APIC_LVTT
);
1115 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
1119 void enable_APIC_timer(void)
1121 int cpu
= smp_processor_id();
1123 if (using_apic_timer
&&
1124 !cpu_isset(cpu
, timer_bcast_ipi
)) {
1127 v
= apic_read(APIC_LVTT
);
1128 apic_write_around(APIC_LVTT
, v
& ~APIC_LVT_MASKED
);
1132 void switch_APIC_timer_to_ipi(void *cpumask
)
1134 cpumask_t mask
= *(cpumask_t
*)cpumask
;
1135 int cpu
= smp_processor_id();
1137 if (cpu_isset(cpu
, mask
) &&
1138 !cpu_isset(cpu
, timer_bcast_ipi
)) {
1139 disable_APIC_timer();
1140 cpu_set(cpu
, timer_bcast_ipi
);
1143 EXPORT_SYMBOL(switch_APIC_timer_to_ipi
);
1145 void switch_ipi_to_APIC_timer(void *cpumask
)
1147 cpumask_t mask
= *(cpumask_t
*)cpumask
;
1148 int cpu
= smp_processor_id();
1150 if (cpu_isset(cpu
, mask
) &&
1151 cpu_isset(cpu
, timer_bcast_ipi
)) {
1152 cpu_clear(cpu
, timer_bcast_ipi
);
1153 enable_APIC_timer();
1156 EXPORT_SYMBOL(switch_ipi_to_APIC_timer
);
1161 * Local timer interrupt handler. It does both profiling and
1162 * process statistics/rescheduling.
1164 * We do profiling in every local tick, statistics/rescheduling
1165 * happen only every 'profiling multiplier' ticks. The default
1166 * multiplier is 1 and it can be changed by writing the new multiplier
1167 * value into /proc/profile.
1170 inline void smp_local_timer_interrupt(struct pt_regs
* regs
)
1172 profile_tick(CPU_PROFILING
, regs
);
1174 update_process_times(user_mode_vm(regs
));
1178 * We take the 'long' return path, and there every subsystem
1179 * grabs the apropriate locks (kernel lock/ irq lock).
1181 * we might want to decouple profiling from the 'long path',
1182 * and do the profiling totally in assembly.
1184 * Currently this isn't too much of an issue (performance wise),
1185 * we can take more than 100K local irqs per second on a 100 MHz P5.
1190 * Local APIC timer interrupt. This is the most natural way for doing
1191 * local interrupts, but local timer interrupts can be emulated by
1192 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1194 * [ if a single-CPU system runs an SMP kernel then we call the local
1195 * interrupt as well. Thus we cannot inline the local irq ... ]
1198 fastcall
void smp_apic_timer_interrupt(struct pt_regs
*regs
)
1200 int cpu
= smp_processor_id();
1203 * the NMI deadlock-detector uses this.
1205 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
1208 * NOTE! We'd better ACK the irq immediately,
1209 * because timer handling can be slow.
1213 * update_process_times() expects us to have done irq_enter().
1214 * Besides, if we don't timer interrupts ignore the global
1215 * interrupt lock, which is the WrongThing (tm) to do.
1218 smp_local_timer_interrupt(regs
);
1223 static void up_apic_timer_interrupt_call(struct pt_regs
*regs
)
1225 int cpu
= smp_processor_id();
1228 * the NMI deadlock-detector uses this.
1230 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
1232 smp_local_timer_interrupt(regs
);
1236 void smp_send_timer_broadcast_ipi(struct pt_regs
*regs
)
1240 cpus_and(mask
, cpu_online_map
, timer_bcast_ipi
);
1241 if (!cpus_empty(mask
)) {
1243 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
1246 * We can directly call the apic timer interrupt handler
1247 * in UP case. Minus all irq related functions
1249 up_apic_timer_interrupt_call(regs
);
1254 int setup_profiling_timer(unsigned int multiplier
)
1260 * This interrupt should _never_ happen with our APIC/SMP architecture
1262 fastcall
void smp_spurious_interrupt(struct pt_regs
*regs
)
1268 * Check if this really is a spurious interrupt and ACK it
1269 * if it is a vectored one. Just in case...
1270 * Spurious interrupts should not be ACKed.
1272 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1273 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1276 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1277 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, should never happen.\n",
1278 smp_processor_id());
1283 * This interrupt should never happen with our APIC/SMP architecture
1286 fastcall
void smp_error_interrupt(struct pt_regs
*regs
)
1288 unsigned long v
, v1
;
1291 /* First tickle the hardware, only then report what went on. -- REW */
1292 v
= apic_read(APIC_ESR
);
1293 apic_write(APIC_ESR
, 0);
1294 v1
= apic_read(APIC_ESR
);
1296 atomic_inc(&irq_err_count
);
1298 /* Here is what the APIC error bits mean:
1301 2: Send accept error
1302 3: Receive accept error
1304 5: Send illegal vector
1305 6: Received illegal vector
1306 7: Illegal register address
1308 printk (KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1309 smp_processor_id(), v
, v1
);
1314 * This initializes the IO-APIC and APIC hardware if this is
1317 int __init
APIC_init_uniprocessor (void)
1319 if (enable_local_apic
< 0)
1320 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1322 if (!smp_found_config
&& !cpu_has_apic
)
1326 * Complain if the BIOS pretends there is one.
1328 if (!cpu_has_apic
&& APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1329 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1330 boot_cpu_physical_apicid
);
1331 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1335 verify_local_APIC();
1339 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
1343 #ifdef CONFIG_X86_IO_APIC
1344 if (smp_found_config
)
1345 if (!skip_ioapic_setup
&& nr_ioapics
)
1348 setup_boot_APIC_clock();