2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/delay.h>
23 #include <linux/bootmem.h>
24 #include <linux/smp_lock.h>
25 #include <linux/interrupt.h>
26 #include <linux/mc146818rtc.h>
27 #include <linux/kernel_stat.h>
28 #include <linux/sysdev.h>
29 #include <linux/cpu.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/arch_hooks.h>
38 #include <asm/i8253.h>
40 #include <mach_apic.h>
45 * Knob to control our willingness to enable the local APIC.
47 int enable_local_apic __initdata
= 0; /* -1=force-disable, +1=force-enable */
55 static void apic_pm_activate(void);
58 * 'what should we do if we get a hw irq event on an illegal vector'.
59 * each architecture has to answer this themselves.
61 void ack_bad_irq(unsigned int irq
)
63 printk("unexpected IRQ trap at vector %02x\n", irq
);
65 * Currently unexpected vectors happen only on SMP and APIC.
66 * We _must_ ack these because every local APIC has only N
67 * irq slots per priority level, and a 'hanging, unacked' IRQ
68 * holds up an irq slot - in excessive cases (when multiple
69 * unexpected vectors occur) that might lock up the APIC
75 void __init
apic_intr_init(void)
80 /* self generated IPI for local APIC timer */
81 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
83 /* IPI vectors for APIC spurious and error interrupts */
84 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
85 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
87 /* thermal monitor LVT interrupt */
88 #ifdef CONFIG_X86_MCE_P4THERMAL
89 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
93 /* Using APIC to generate smp_local_timer_interrupt? */
94 int using_apic_timer
= 0;
96 static DEFINE_PER_CPU(int, prof_multiplier
) = 1;
97 static DEFINE_PER_CPU(int, prof_old_multiplier
) = 1;
98 static DEFINE_PER_CPU(int, prof_counter
) = 1;
100 static int enabled_via_apicbase
;
102 void enable_NMI_through_LVT0 (void * dummy
)
106 ver
= apic_read(APIC_LVR
);
107 ver
= GET_APIC_VERSION(ver
);
108 v
= APIC_DM_NMI
; /* unmask and set to NMI */
109 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
110 v
|= APIC_LVT_LEVEL_TRIGGER
;
111 apic_write_around(APIC_LVT0
, v
);
114 int get_physical_broadcast(void)
116 unsigned int lvr
, version
;
117 lvr
= apic_read(APIC_LVR
);
118 version
= GET_APIC_VERSION(lvr
);
119 if (!APIC_INTEGRATED(version
) || version
>= 0x14)
127 unsigned int v
, ver
, maxlvt
;
129 v
= apic_read(APIC_LVR
);
130 ver
= GET_APIC_VERSION(v
);
131 /* 82489DXs do not report # of LVT entries. */
132 maxlvt
= APIC_INTEGRATED(ver
) ? GET_APIC_MAXLVT(v
) : 2;
136 void clear_local_APIC(void)
141 maxlvt
= get_maxlvt();
144 * Masking an LVT entry on a P6 can trigger a local APIC error
145 * if the vector is zero. Mask LVTERR first to prevent this.
148 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
149 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
152 * Careful: we have to set masks only first to deassert
153 * any level-triggered sources.
155 v
= apic_read(APIC_LVTT
);
156 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
157 v
= apic_read(APIC_LVT0
);
158 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
159 v
= apic_read(APIC_LVT1
);
160 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
162 v
= apic_read(APIC_LVTPC
);
163 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
166 /* lets not touch this if we didn't frob it */
167 #ifdef CONFIG_X86_MCE_P4THERMAL
169 v
= apic_read(APIC_LVTTHMR
);
170 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
174 * Clean APIC state for other OSs:
176 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
177 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
178 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
180 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
182 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
184 #ifdef CONFIG_X86_MCE_P4THERMAL
186 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
188 v
= GET_APIC_VERSION(apic_read(APIC_LVR
));
189 if (APIC_INTEGRATED(v
)) { /* !82489DX */
190 if (maxlvt
> 3) /* Due to Pentium errata 3AP and 11AP. */
191 apic_write(APIC_ESR
, 0);
196 void __init
connect_bsp_APIC(void)
200 * Do not trust the local APIC being empty at bootup.
204 * PIC mode, enable APIC mode in the IMCR, i.e.
205 * connect BSP's local APIC to INT and NMI lines.
207 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
208 "enabling APIC mode.\n");
215 void disconnect_bsp_APIC(int virt_wire_setup
)
219 * Put the board back into PIC mode (has an effect
220 * only on certain older boards). Note that APIC
221 * interrupts, including IPIs, won't work beyond
222 * this point! The only exception are INIT IPIs.
224 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
225 "entering PIC mode.\n");
230 /* Go back to Virtual Wire compatibility mode */
233 /* For the spurious interrupt use vector F, and enable it */
234 value
= apic_read(APIC_SPIV
);
235 value
&= ~APIC_VECTOR_MASK
;
236 value
|= APIC_SPIV_APIC_ENABLED
;
238 apic_write_around(APIC_SPIV
, value
);
240 if (!virt_wire_setup
) {
241 /* For LVT0 make it edge triggered, active high, external and enabled */
242 value
= apic_read(APIC_LVT0
);
243 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
244 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
245 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
246 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
247 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
248 apic_write_around(APIC_LVT0
, value
);
252 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
255 /* For LVT1 make it edge triggered, active high, nmi and enabled */
256 value
= apic_read(APIC_LVT1
);
258 APIC_MODE_MASK
| APIC_SEND_PENDING
|
259 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
260 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
261 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
262 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
263 apic_write_around(APIC_LVT1
, value
);
267 void disable_local_APIC(void)
274 * Disable APIC (implies clearing of registers
277 value
= apic_read(APIC_SPIV
);
278 value
&= ~APIC_SPIV_APIC_ENABLED
;
279 apic_write_around(APIC_SPIV
, value
);
281 if (enabled_via_apicbase
) {
283 rdmsr(MSR_IA32_APICBASE
, l
, h
);
284 l
&= ~MSR_IA32_APICBASE_ENABLE
;
285 wrmsr(MSR_IA32_APICBASE
, l
, h
);
290 * This is to verify that we're looking at a real local APIC.
291 * Check these against your board if the CPUs aren't getting
292 * started for no apparent reason.
294 int __init
verify_local_APIC(void)
296 unsigned int reg0
, reg1
;
299 * The version register is read-only in a real APIC.
301 reg0
= apic_read(APIC_LVR
);
302 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
303 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
304 reg1
= apic_read(APIC_LVR
);
305 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
308 * The two version reads above should print the same
309 * numbers. If the second one is different, then we
310 * poke at a non-APIC.
316 * Check if the version looks reasonably.
318 reg1
= GET_APIC_VERSION(reg0
);
319 if (reg1
== 0x00 || reg1
== 0xff)
322 if (reg1
< 0x02 || reg1
== 0xff)
326 * The ID register is read/write in a real APIC.
328 reg0
= apic_read(APIC_ID
);
329 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
332 * The next two are just to see if we have sane values.
333 * They're only really relevant if we're in Virtual Wire
334 * compatibility mode, but most boxes are anymore.
336 reg0
= apic_read(APIC_LVT0
);
337 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
338 reg1
= apic_read(APIC_LVT1
);
339 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
344 void __init
sync_Arb_IDs(void)
346 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
347 unsigned int ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
348 if (ver
>= 0x14) /* P4 or higher */
353 apic_wait_icr_idle();
355 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
356 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
360 extern void __error_in_apic_c (void);
363 * An initial setup of the virtual wire mode.
365 void __init
init_bsp_APIC(void)
367 unsigned long value
, ver
;
370 * Don't do the setup now if we have a SMP BIOS as the
371 * through-I/O-APIC virtual wire mode might be active.
373 if (smp_found_config
|| !cpu_has_apic
)
376 value
= apic_read(APIC_LVR
);
377 ver
= GET_APIC_VERSION(value
);
380 * Do not trust the local APIC being empty at bootup.
387 value
= apic_read(APIC_SPIV
);
388 value
&= ~APIC_VECTOR_MASK
;
389 value
|= APIC_SPIV_APIC_ENABLED
;
391 /* This bit is reserved on P4/Xeon and should be cleared */
392 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 15))
393 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
395 value
|= APIC_SPIV_FOCUS_DISABLED
;
396 value
|= SPURIOUS_APIC_VECTOR
;
397 apic_write_around(APIC_SPIV
, value
);
400 * Set up the virtual wire mode.
402 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
404 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
405 value
|= APIC_LVT_LEVEL_TRIGGER
;
406 apic_write_around(APIC_LVT1
, value
);
409 void __devinit
setup_local_APIC(void)
411 unsigned long oldvalue
, value
, ver
, maxlvt
;
413 /* Pound the ESR really hard over the head with a big hammer - mbligh */
415 apic_write(APIC_ESR
, 0);
416 apic_write(APIC_ESR
, 0);
417 apic_write(APIC_ESR
, 0);
418 apic_write(APIC_ESR
, 0);
421 value
= apic_read(APIC_LVR
);
422 ver
= GET_APIC_VERSION(value
);
424 if ((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f)
428 * Double-check whether this APIC is really registered.
430 if (!apic_id_registered())
434 * Intel recommends to set DFR, LDR and TPR before enabling
435 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
436 * document number 292116). So here it goes...
441 * Set Task Priority to 'accept all'. We never change this
444 value
= apic_read(APIC_TASKPRI
);
445 value
&= ~APIC_TPRI_MASK
;
446 apic_write_around(APIC_TASKPRI
, value
);
449 * Now that we are all set up, enable the APIC
451 value
= apic_read(APIC_SPIV
);
452 value
&= ~APIC_VECTOR_MASK
;
456 value
|= APIC_SPIV_APIC_ENABLED
;
459 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
460 * certain networking cards. If high frequency interrupts are
461 * happening on a particular IOAPIC pin, plus the IOAPIC routing
462 * entry is masked/unmasked at a high rate as well then sooner or
463 * later IOAPIC line gets 'stuck', no more interrupts are received
464 * from the device. If focus CPU is disabled then the hang goes
467 * [ This bug can be reproduced easily with a level-triggered
468 * PCI Ne2000 networking cards and PII/PIII processors, dual
472 * Actually disabling the focus CPU check just makes the hang less
473 * frequent as it makes the interrupt distributon model be more
474 * like LRU than MRU (the short-term load is more even across CPUs).
475 * See also the comment in end_level_ioapic_irq(). --macro
478 /* Enable focus processor (bit==0) */
479 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
481 /* Disable focus processor (bit==1) */
482 value
|= APIC_SPIV_FOCUS_DISABLED
;
485 * Set spurious IRQ vector
487 value
|= SPURIOUS_APIC_VECTOR
;
488 apic_write_around(APIC_SPIV
, value
);
493 * set up through-local-APIC on the BP's LINT0. This is not
494 * strictly necessery in pure symmetric-IO mode, but sometimes
495 * we delegate interrupts to the 8259A.
498 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
500 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
501 if (!smp_processor_id() && (pic_mode
|| !value
)) {
502 value
= APIC_DM_EXTINT
;
503 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
506 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
507 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
510 apic_write_around(APIC_LVT0
, value
);
513 * only the BP should see the LINT1 NMI signal, obviously.
515 if (!smp_processor_id())
518 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
519 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
520 value
|= APIC_LVT_LEVEL_TRIGGER
;
521 apic_write_around(APIC_LVT1
, value
);
523 if (APIC_INTEGRATED(ver
) && !esr_disable
) { /* !82489DX */
524 maxlvt
= get_maxlvt();
525 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
526 apic_write(APIC_ESR
, 0);
527 oldvalue
= apic_read(APIC_ESR
);
529 value
= ERROR_APIC_VECTOR
; // enables sending errors
530 apic_write_around(APIC_LVTERR
, value
);
532 * spec says clear errors after enabling vector.
535 apic_write(APIC_ESR
, 0);
536 value
= apic_read(APIC_ESR
);
537 if (value
!= oldvalue
)
538 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
539 "vector: 0x%08lx after: 0x%08lx\n",
544 * Something untraceble is creating bad interrupts on
545 * secondary quads ... for the moment, just leave the
546 * ESR disabled - we can't do anything useful with the
547 * errors anyway - mbligh
549 printk("Leaving ESR disabled.\n");
551 printk("No ESR for 82489DX.\n");
554 if (nmi_watchdog
== NMI_LOCAL_APIC
)
555 setup_apic_nmi_watchdog();
560 * If Linux enabled the LAPIC against the BIOS default
561 * disable it down before re-entering the BIOS on shutdown.
562 * Otherwise the BIOS may get confused and not power-off.
564 void lapic_shutdown(void)
566 if (!cpu_has_apic
|| !enabled_via_apicbase
)
570 disable_local_APIC();
578 /* r/w apic fields */
579 unsigned int apic_id
;
580 unsigned int apic_taskpri
;
581 unsigned int apic_ldr
;
582 unsigned int apic_dfr
;
583 unsigned int apic_spiv
;
584 unsigned int apic_lvtt
;
585 unsigned int apic_lvtpc
;
586 unsigned int apic_lvt0
;
587 unsigned int apic_lvt1
;
588 unsigned int apic_lvterr
;
589 unsigned int apic_tmict
;
590 unsigned int apic_tdcr
;
591 unsigned int apic_thmr
;
594 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
598 if (!apic_pm_state
.active
)
601 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
602 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
603 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
604 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
605 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
606 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
607 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
608 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
609 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
610 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
611 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
612 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
613 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
615 local_irq_save(flags
);
616 disable_local_APIC();
617 local_irq_restore(flags
);
621 static int lapic_resume(struct sys_device
*dev
)
626 if (!apic_pm_state
.active
)
629 local_irq_save(flags
);
632 * Make sure the APICBASE points to the right address
634 * FIXME! This will be wrong if we ever support suspend on
635 * SMP! We'll need to do this as part of the CPU restore!
637 rdmsr(MSR_IA32_APICBASE
, l
, h
);
638 l
&= ~MSR_IA32_APICBASE_BASE
;
639 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
640 wrmsr(MSR_IA32_APICBASE
, l
, h
);
642 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
643 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
644 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
645 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
646 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
647 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
648 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
649 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
650 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
651 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
652 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
653 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
654 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
655 apic_write(APIC_ESR
, 0);
657 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
658 apic_write(APIC_ESR
, 0);
660 local_irq_restore(flags
);
665 * This device has no shutdown method - fully functioning local APICs
666 * are needed on every CPU up until machine_halt/restart/poweroff.
669 static struct sysdev_class lapic_sysclass
= {
670 set_kset_name("lapic"),
671 .resume
= lapic_resume
,
672 .suspend
= lapic_suspend
,
675 static struct sys_device device_lapic
= {
677 .cls
= &lapic_sysclass
,
680 static void __devinit
apic_pm_activate(void)
682 apic_pm_state
.active
= 1;
685 static int __init
init_lapic_sysfs(void)
691 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
693 error
= sysdev_class_register(&lapic_sysclass
);
695 error
= sysdev_register(&device_lapic
);
698 device_initcall(init_lapic_sysfs
);
700 #else /* CONFIG_PM */
702 static void apic_pm_activate(void) { }
704 #endif /* CONFIG_PM */
707 * Detect and enable local APICs on non-SMP boards.
708 * Original code written by Keir Fraser.
711 static int __init
apic_set_verbosity(char *str
)
713 if (strcmp("debug", str
) == 0)
714 apic_verbosity
= APIC_DEBUG
;
715 else if (strcmp("verbose", str
) == 0)
716 apic_verbosity
= APIC_VERBOSE
;
718 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
719 " use apic=verbose or apic=debug", str
);
724 __setup("apic=", apic_set_verbosity
);
726 static int __init
detect_init_APIC (void)
730 /* Disabled by kernel option? */
731 if (enable_local_apic
< 0)
734 switch (boot_cpu_data
.x86_vendor
) {
736 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
737 (boot_cpu_data
.x86
== 15))
740 case X86_VENDOR_INTEL
:
741 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
742 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
751 * Over-ride BIOS and try to enable the local
752 * APIC only if "lapic" specified.
754 if (enable_local_apic
<= 0) {
755 printk("Local APIC disabled by BIOS -- "
756 "you can enable it with \"lapic\"\n");
760 * Some BIOSes disable the local APIC in the
761 * APIC_BASE MSR. This can only be done in
762 * software for Intel P6 or later and AMD K7
763 * (Model > 1) or later.
765 rdmsr(MSR_IA32_APICBASE
, l
, h
);
766 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
767 printk("Local APIC disabled by BIOS -- reenabling.\n");
768 l
&= ~MSR_IA32_APICBASE_BASE
;
769 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
770 wrmsr(MSR_IA32_APICBASE
, l
, h
);
771 enabled_via_apicbase
= 1;
775 * The APIC feature bit should now be enabled
778 features
= cpuid_edx(1);
779 if (!(features
& (1 << X86_FEATURE_APIC
))) {
780 printk("Could not enable APIC!\n");
783 set_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
784 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
786 /* The BIOS may have set up the APIC at some other address */
787 rdmsr(MSR_IA32_APICBASE
, l
, h
);
788 if (l
& MSR_IA32_APICBASE_ENABLE
)
789 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
791 if (nmi_watchdog
!= NMI_NONE
)
792 nmi_watchdog
= NMI_LOCAL_APIC
;
794 printk("Found and enabled local APIC!\n");
801 printk("No local APIC present or hardware disabled\n");
805 void __init
init_apic_mappings(void)
807 unsigned long apic_phys
;
810 * If no local APIC can be found then set up a fake all
811 * zeroes page to simulate the local APIC and another
812 * one for the IO-APIC.
814 if (!smp_found_config
&& detect_init_APIC()) {
815 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
816 apic_phys
= __pa(apic_phys
);
818 apic_phys
= mp_lapic_addr
;
820 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
821 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
825 * Fetch the APIC ID of the BSP in case we have a
826 * default configuration (or the MP table is broken).
828 if (boot_cpu_physical_apicid
== -1U)
829 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
831 #ifdef CONFIG_X86_IO_APIC
833 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
836 for (i
= 0; i
< nr_ioapics
; i
++) {
837 if (smp_found_config
) {
838 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
841 "WARNING: bogus zero IO-APIC "
842 "address found in MPTABLE, "
843 "disabling IO/APIC support!\n");
844 smp_found_config
= 0;
845 skip_ioapic_setup
= 1;
846 goto fake_ioapic_page
;
850 ioapic_phys
= (unsigned long)
851 alloc_bootmem_pages(PAGE_SIZE
);
852 ioapic_phys
= __pa(ioapic_phys
);
854 set_fixmap_nocache(idx
, ioapic_phys
);
855 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
856 __fix_to_virt(idx
), ioapic_phys
);
864 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
865 * per second. We assume that the caller has already set up the local
868 * The APIC timer is not exactly sync with the external timer chip, it
869 * closely follows bus clocks.
873 * The timer chip is already set up at HZ interrupts per second here,
874 * but we do not accept timer interrupts yet. We only allow the BP
877 static unsigned int __devinit
get_8254_timer_count(void)
883 spin_lock_irqsave(&i8253_lock
, flags
);
885 outb_p(0x00, PIT_MODE
);
886 count
= inb_p(PIT_CH0
);
887 count
|= inb_p(PIT_CH0
) << 8;
889 spin_unlock_irqrestore(&i8253_lock
, flags
);
894 /* next tick in 8254 can be caught by catching timer wraparound */
895 static void __devinit
wait_8254_wraparound(void)
897 unsigned int curr_count
, prev_count
;
899 curr_count
= get_8254_timer_count();
901 prev_count
= curr_count
;
902 curr_count
= get_8254_timer_count();
904 /* workaround for broken Mercury/Neptune */
905 if (prev_count
>= curr_count
+ 0x100)
906 curr_count
= get_8254_timer_count();
908 } while (prev_count
>= curr_count
);
912 * Default initialization for 8254 timers. If we use other timers like HPET,
913 * we override this later
915 void (*wait_timer_tick
)(void) __devinitdata
= wait_8254_wraparound
;
918 * This function sets up the local APIC timer, with a timeout of
919 * 'clocks' APIC bus clock. During calibration we actually call
920 * this function twice on the boot CPU, once with a bogus timeout
921 * value, second time for real. The other (noncalibrating) CPUs
922 * call this function only once, with the real, calibrated value.
924 * We do reads before writes even if unnecessary, to get around the
925 * P5 APIC double write bug.
928 #define APIC_DIVISOR 16
930 static void __setup_APIC_LVTT(unsigned int clocks
)
932 unsigned int lvtt_value
, tmp_value
, ver
;
934 ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
935 lvtt_value
= APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
936 if (!APIC_INTEGRATED(ver
))
937 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
938 apic_write_around(APIC_LVTT
, lvtt_value
);
943 tmp_value
= apic_read(APIC_TDCR
);
944 apic_write_around(APIC_TDCR
, (tmp_value
945 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
948 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
951 static void __devinit
setup_APIC_timer(unsigned int clocks
)
955 local_irq_save(flags
);
958 * Wait for IRQ0's slice:
962 __setup_APIC_LVTT(clocks
);
964 local_irq_restore(flags
);
968 * In this function we calibrate APIC bus clocks to the external
969 * timer. Unfortunately we cannot use jiffies and the timer irq
970 * to calibrate, since some later bootup code depends on getting
971 * the first irq? Ugh.
973 * We want to do the calibration only once since we
974 * want to have local timer irqs syncron. CPUs connected
975 * by the same APIC bus have the very same bus frequency.
976 * And we want to have irqs off anyways, no accidental
980 static int __init
calibrate_APIC_clock(void)
982 unsigned long long t1
= 0, t2
= 0;
986 const int LOOPS
= HZ
/10;
988 apic_printk(APIC_VERBOSE
, "calibrating APIC timer ...\n");
991 * Put whatever arbitrary (but long enough) timeout
992 * value into the APIC clock, we just want to get the
993 * counter running for calibration.
995 __setup_APIC_LVTT(1000000000);
998 * The timer chip counts down to zero. Let's wait
999 * for a wraparound to start exact measurement:
1000 * (the current tick might have been already half done)
1006 * We wrapped around just now. Let's start:
1010 tt1
= apic_read(APIC_TMCCT
);
1013 * Let's wait LOOPS wraprounds:
1015 for (i
= 0; i
< LOOPS
; i
++)
1018 tt2
= apic_read(APIC_TMCCT
);
1023 * The APIC bus clock counter is 32 bits only, it
1024 * might have overflown, but note that we use signed
1025 * longs, thus no extra care needed.
1027 * underflown to be exact, as the timer counts down ;)
1030 result
= (tt1
-tt2
)*APIC_DIVISOR
/LOOPS
;
1033 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
1035 ((long)(t2
-t1
)/LOOPS
)/(1000000/HZ
),
1036 ((long)(t2
-t1
)/LOOPS
)%(1000000/HZ
));
1038 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
1040 result
/(1000000/HZ
),
1041 result
%(1000000/HZ
));
1046 static unsigned int calibration_result
;
1048 void __init
setup_boot_APIC_clock(void)
1050 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n");
1051 using_apic_timer
= 1;
1053 local_irq_disable();
1055 calibration_result
= calibrate_APIC_clock();
1057 * Now set up the timer for real.
1059 setup_APIC_timer(calibration_result
);
1064 void __devinit
setup_secondary_APIC_clock(void)
1066 setup_APIC_timer(calibration_result
);
1069 void __devinit
disable_APIC_timer(void)
1071 if (using_apic_timer
) {
1074 v
= apic_read(APIC_LVTT
);
1075 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
1079 void enable_APIC_timer(void)
1081 if (using_apic_timer
) {
1084 v
= apic_read(APIC_LVTT
);
1085 apic_write_around(APIC_LVTT
, v
& ~APIC_LVT_MASKED
);
1090 * the frequency of the profiling timer can be changed
1091 * by writing a multiplier value into /proc/profile.
1093 int setup_profiling_timer(unsigned int multiplier
)
1098 * Sanity check. [at least 500 APIC cycles should be
1099 * between APIC interrupts as a rule of thumb, to avoid
1102 if ( (!multiplier
) || (calibration_result
/multiplier
< 500))
1106 * Set the new multiplier for each CPU. CPUs don't start using the
1107 * new values until the next timer interrupt in which they do process
1108 * accounting. At that time they also adjust their APIC timers
1111 for (i
= 0; i
< NR_CPUS
; ++i
)
1112 per_cpu(prof_multiplier
, i
) = multiplier
;
1120 * Local timer interrupt handler. It does both profiling and
1121 * process statistics/rescheduling.
1123 * We do profiling in every local tick, statistics/rescheduling
1124 * happen only every 'profiling multiplier' ticks. The default
1125 * multiplier is 1 and it can be changed by writing the new multiplier
1126 * value into /proc/profile.
1129 inline void smp_local_timer_interrupt(struct pt_regs
* regs
)
1131 int cpu
= smp_processor_id();
1133 profile_tick(CPU_PROFILING
, regs
);
1134 if (--per_cpu(prof_counter
, cpu
) <= 0) {
1136 * The multiplier may have changed since the last time we got
1137 * to this point as a result of the user writing to
1138 * /proc/profile. In this case we need to adjust the APIC
1139 * timer accordingly.
1141 * Interrupts are already masked off at this point.
1143 per_cpu(prof_counter
, cpu
) = per_cpu(prof_multiplier
, cpu
);
1144 if (per_cpu(prof_counter
, cpu
) !=
1145 per_cpu(prof_old_multiplier
, cpu
)) {
1148 per_cpu(prof_counter
, cpu
));
1149 per_cpu(prof_old_multiplier
, cpu
) =
1150 per_cpu(prof_counter
, cpu
);
1154 update_process_times(user_mode_vm(regs
));
1159 * We take the 'long' return path, and there every subsystem
1160 * grabs the apropriate locks (kernel lock/ irq lock).
1162 * we might want to decouple profiling from the 'long path',
1163 * and do the profiling totally in assembly.
1165 * Currently this isn't too much of an issue (performance wise),
1166 * we can take more than 100K local irqs per second on a 100 MHz P5.
1171 * Local APIC timer interrupt. This is the most natural way for doing
1172 * local interrupts, but local timer interrupts can be emulated by
1173 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1175 * [ if a single-CPU system runs an SMP kernel then we call the local
1176 * interrupt as well. Thus we cannot inline the local irq ... ]
1179 fastcall
void smp_apic_timer_interrupt(struct pt_regs
*regs
)
1181 int cpu
= smp_processor_id();
1184 * the NMI deadlock-detector uses this.
1186 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
1189 * NOTE! We'd better ACK the irq immediately,
1190 * because timer handling can be slow.
1194 * update_process_times() expects us to have done irq_enter().
1195 * Besides, if we don't timer interrupts ignore the global
1196 * interrupt lock, which is the WrongThing (tm) to do.
1199 smp_local_timer_interrupt(regs
);
1204 * This interrupt should _never_ happen with our APIC/SMP architecture
1206 fastcall
void smp_spurious_interrupt(struct pt_regs
*regs
)
1212 * Check if this really is a spurious interrupt and ACK it
1213 * if it is a vectored one. Just in case...
1214 * Spurious interrupts should not be ACKed.
1216 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1217 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1220 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1221 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, should never happen.\n",
1222 smp_processor_id());
1227 * This interrupt should never happen with our APIC/SMP architecture
1230 fastcall
void smp_error_interrupt(struct pt_regs
*regs
)
1232 unsigned long v
, v1
;
1235 /* First tickle the hardware, only then report what went on. -- REW */
1236 v
= apic_read(APIC_ESR
);
1237 apic_write(APIC_ESR
, 0);
1238 v1
= apic_read(APIC_ESR
);
1240 atomic_inc(&irq_err_count
);
1242 /* Here is what the APIC error bits mean:
1245 2: Send accept error
1246 3: Receive accept error
1248 5: Send illegal vector
1249 6: Received illegal vector
1250 7: Illegal register address
1252 printk (KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1253 smp_processor_id(), v
, v1
);
1258 * This initializes the IO-APIC and APIC hardware if this is
1261 int __init
APIC_init_uniprocessor (void)
1263 if (enable_local_apic
< 0)
1264 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1266 if (!smp_found_config
&& !cpu_has_apic
)
1270 * Complain if the BIOS pretends there is one.
1272 if (!cpu_has_apic
&& APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1273 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1274 boot_cpu_physical_apicid
);
1278 verify_local_APIC();
1282 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
1286 #ifdef CONFIG_X86_IO_APIC
1287 if (smp_found_config
)
1288 if (!skip_ioapic_setup
&& nr_ioapics
)
1291 setup_boot_APIC_clock();