2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/compiler.h>
32 #include <linux/acpi.h>
33 #include <linux/module.h>
34 #include <linux/sysdev.h>
39 #include <asm/timer.h>
40 #include <asm/i8259.h>
42 #include <mach_apic.h>
46 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
47 atomic_t irq_mis_count
;
49 /* Where if anywhere is the i8259 connect in external int mode */
50 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
52 static DEFINE_SPINLOCK(ioapic_lock
);
54 int timer_over_8254 __initdata
= 1;
57 * Is the SiS APIC rmw bug present ?
58 * -1 = don't know, 0 = no, 1 = yes
60 int sis_apic_bug
= -1;
63 * # of IRQ routing registers
65 int nr_ioapic_registers
[MAX_IO_APICS
];
67 int disable_timer_pin_1 __initdata
;
70 * Rough estimation of how many shared IRQs there are, can
73 #define MAX_PLUS_SHARED_IRQS NR_IRQS
74 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
77 * This is performance-critical, we want to do it O(1)
79 * the indexing order of this array favors 1:1 mappings
80 * between pins and IRQs.
83 static struct irq_pin_list
{
85 } irq_2_pin
[PIN_MAP_SIZE
];
87 int vector_irq
[NR_VECTORS
] __read_mostly
= { [0 ... NR_VECTORS
- 1] = -1};
89 #define vector_to_irq(vector) \
90 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
92 #define vector_to_irq(vector) (vector)
96 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
97 * shared ISA-space IRQs, so we have to support them. We are super
98 * fast in the common case, and fast for shared ISA-space IRQs.
100 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
102 static int first_free_entry
= NR_IRQS
;
103 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
106 entry
= irq_2_pin
+ entry
->next
;
108 if (entry
->pin
!= -1) {
109 entry
->next
= first_free_entry
;
110 entry
= irq_2_pin
+ entry
->next
;
111 if (++first_free_entry
>= PIN_MAP_SIZE
)
112 panic("io_apic.c: whoops");
119 * Reroute an IRQ to a different pin.
121 static void __init
replace_pin_at_irq(unsigned int irq
,
122 int oldapic
, int oldpin
,
123 int newapic
, int newpin
)
125 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
128 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
129 entry
->apic
= newapic
;
134 entry
= irq_2_pin
+ entry
->next
;
138 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
140 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
141 unsigned int pin
, reg
;
147 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
150 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
153 entry
= irq_2_pin
+ entry
->next
;
158 static void __mask_IO_APIC_irq (unsigned int irq
)
160 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
164 static void __unmask_IO_APIC_irq (unsigned int irq
)
166 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
169 /* mask = 1, trigger = 0 */
170 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
172 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
175 /* mask = 0, trigger = 1 */
176 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
178 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
181 static void mask_IO_APIC_irq (unsigned int irq
)
185 spin_lock_irqsave(&ioapic_lock
, flags
);
186 __mask_IO_APIC_irq(irq
);
187 spin_unlock_irqrestore(&ioapic_lock
, flags
);
190 static void unmask_IO_APIC_irq (unsigned int irq
)
194 spin_lock_irqsave(&ioapic_lock
, flags
);
195 __unmask_IO_APIC_irq(irq
);
196 spin_unlock_irqrestore(&ioapic_lock
, flags
);
199 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
201 struct IO_APIC_route_entry entry
;
204 /* Check delivery_mode to be sure we're not clearing an SMI pin */
205 spin_lock_irqsave(&ioapic_lock
, flags
);
206 *(((int*)&entry
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
207 *(((int*)&entry
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
208 spin_unlock_irqrestore(&ioapic_lock
, flags
);
209 if (entry
.delivery_mode
== dest_SMI
)
213 * Disable it in the IO-APIC irq-routing table:
215 memset(&entry
, 0, sizeof(entry
));
217 spin_lock_irqsave(&ioapic_lock
, flags
);
218 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry
) + 0));
219 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry
) + 1));
220 spin_unlock_irqrestore(&ioapic_lock
, flags
);
223 static void clear_IO_APIC (void)
227 for (apic
= 0; apic
< nr_ioapics
; apic
++)
228 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
229 clear_IO_APIC_pin(apic
, pin
);
233 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
237 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
238 unsigned int apicid_value
;
241 cpus_and(tmp
, cpumask
, cpu_online_map
);
245 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
247 apicid_value
= cpu_mask_to_apicid(cpumask
);
248 /* Prepare to do the io_apic_write */
249 apicid_value
= apicid_value
<< 24;
250 spin_lock_irqsave(&ioapic_lock
, flags
);
255 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
258 entry
= irq_2_pin
+ entry
->next
;
260 set_irq_info(irq
, cpumask
);
261 spin_unlock_irqrestore(&ioapic_lock
, flags
);
264 #if defined(CONFIG_IRQBALANCE)
265 # include <asm/processor.h> /* kernel_thread() */
266 # include <linux/kernel_stat.h> /* kstat */
267 # include <linux/slab.h> /* kmalloc() */
268 # include <linux/timer.h> /* time_after() */
270 # ifdef CONFIG_BALANCED_IRQ_DEBUG
271 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
272 # define Dprintk(x...) do { TDprintk(x); } while (0)
274 # define TDprintk(x...)
275 # define Dprintk(x...)
279 #define IRQBALANCE_CHECK_ARCH -999
280 static int irqbalance_disabled
= IRQBALANCE_CHECK_ARCH
;
281 static int physical_balance
= 0;
283 static struct irq_cpu_info
{
284 unsigned long * last_irq
;
285 unsigned long * irq_delta
;
287 } irq_cpu_data
[NR_CPUS
];
289 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
290 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
291 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
293 #define IDLE_ENOUGH(cpu,now) \
294 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
296 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
298 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
300 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
301 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
302 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
303 #define BALANCED_IRQ_LESS_DELTA (HZ)
305 static long balanced_irq_interval
= MAX_BALANCED_IRQ_INTERVAL
;
307 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
308 unsigned long now
, int direction
)
316 if (unlikely(cpu
== curr_cpu
))
319 if (direction
== 1) {
328 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
329 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
334 static inline void balance_irq(int cpu
, int irq
)
336 unsigned long now
= jiffies
;
337 cpumask_t allowed_mask
;
338 unsigned int new_cpu
;
340 if (irqbalance_disabled
)
343 cpus_and(allowed_mask
, cpu_online_map
, irq_affinity
[irq
]);
344 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
345 if (cpu
!= new_cpu
) {
346 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
350 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
353 Dprintk("Rotating IRQs among CPUs.\n");
354 for (i
= 0; i
< NR_CPUS
; i
++) {
355 for (j
= 0; cpu_online(i
) && (j
< NR_IRQS
); j
++) {
356 if (!irq_desc
[j
].action
)
358 /* Is it a significant load ? */
359 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
360 useful_load_threshold
)
365 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
366 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
370 static void do_irq_balance(void)
373 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
374 unsigned long move_this_load
= 0;
375 int max_loaded
= 0, min_loaded
= 0;
377 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
379 int tmp_loaded
, first_attempt
= 1;
380 unsigned long tmp_cpu_irq
;
381 unsigned long imbalance
= 0;
382 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
384 for (i
= 0; i
< NR_CPUS
; i
++) {
389 package_index
= CPU_TO_PACKAGEINDEX(i
);
390 for (j
= 0; j
< NR_IRQS
; j
++) {
391 unsigned long value_now
, delta
;
392 /* Is this an active IRQ? */
393 if (!irq_desc
[j
].action
)
395 if ( package_index
== i
)
396 IRQ_DELTA(package_index
,j
) = 0;
397 /* Determine the total count per processor per IRQ */
398 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
400 /* Determine the activity per processor per IRQ */
401 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
403 /* Update last_cpu_irq[][] for the next time */
404 LAST_CPU_IRQ(i
,j
) = value_now
;
406 /* Ignore IRQs whose rate is less than the clock */
407 if (delta
< useful_load_threshold
)
409 /* update the load for the processor or package total */
410 IRQ_DELTA(package_index
,j
) += delta
;
412 /* Keep track of the higher numbered sibling as well */
413 if (i
!= package_index
)
416 * We have sibling A and sibling B in the package
418 * cpu_irq[A] = load for cpu A + load for cpu B
419 * cpu_irq[B] = load for cpu B
421 CPU_IRQ(package_index
) += delta
;
424 /* Find the least loaded processor package */
425 for (i
= 0; i
< NR_CPUS
; i
++) {
428 if (i
!= CPU_TO_PACKAGEINDEX(i
))
430 if (min_cpu_irq
> CPU_IRQ(i
)) {
431 min_cpu_irq
= CPU_IRQ(i
);
435 max_cpu_irq
= ULONG_MAX
;
438 /* Look for heaviest loaded processor.
439 * We may come back to get the next heaviest loaded processor.
440 * Skip processors with trivial loads.
444 for (i
= 0; i
< NR_CPUS
; i
++) {
447 if (i
!= CPU_TO_PACKAGEINDEX(i
))
449 if (max_cpu_irq
<= CPU_IRQ(i
))
451 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
452 tmp_cpu_irq
= CPU_IRQ(i
);
457 if (tmp_loaded
== -1) {
458 /* In the case of small number of heavy interrupt sources,
459 * loading some of the cpus too much. We use Ingo's original
460 * approach to rotate them around.
462 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
463 rotate_irqs_among_cpus(useful_load_threshold
);
466 goto not_worth_the_effort
;
469 first_attempt
= 0; /* heaviest search */
470 max_cpu_irq
= tmp_cpu_irq
; /* load */
471 max_loaded
= tmp_loaded
; /* processor */
472 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
474 Dprintk("max_loaded cpu = %d\n", max_loaded
);
475 Dprintk("min_loaded cpu = %d\n", min_loaded
);
476 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq
);
477 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq
);
478 Dprintk("load imbalance = %lu\n", imbalance
);
480 /* if imbalance is less than approx 10% of max load, then
481 * observe diminishing returns action. - quit
483 if (imbalance
< (max_cpu_irq
>> 3)) {
484 Dprintk("Imbalance too trivial\n");
485 goto not_worth_the_effort
;
489 /* if we select an IRQ to move that can't go where we want, then
490 * see if there is another one to try.
494 for (j
= 0; j
< NR_IRQS
; j
++) {
495 /* Is this an active IRQ? */
496 if (!irq_desc
[j
].action
)
498 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
500 /* Try to find the IRQ that is closest to the imbalance
501 * without going over.
503 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
504 move_this_load
= IRQ_DELTA(max_loaded
,j
);
508 if (selected_irq
== -1) {
512 imbalance
= move_this_load
;
514 /* For physical_balance case, we accumlated both load
515 * values in the one of the siblings cpu_irq[],
516 * to use the same code for physical and logical processors
517 * as much as possible.
519 * NOTE: the cpu_irq[] array holds the sum of the load for
520 * sibling A and sibling B in the slot for the lowest numbered
521 * sibling (A), _AND_ the load for sibling B in the slot for
522 * the higher numbered sibling.
524 * We seek the least loaded sibling by making the comparison
527 load
= CPU_IRQ(min_loaded
) >> 1;
528 for_each_cpu_mask(j
, cpu_sibling_map
[min_loaded
]) {
529 if (load
> CPU_IRQ(j
)) {
530 /* This won't change cpu_sibling_map[min_loaded] */
536 cpus_and(allowed_mask
, cpu_online_map
, irq_affinity
[selected_irq
]);
537 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
538 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
540 if (!cpus_empty(tmp
)) {
542 Dprintk("irq = %d moved to cpu = %d\n",
543 selected_irq
, min_loaded
);
544 /* mark for change destination */
545 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
547 /* Since we made a change, come back sooner to
548 * check for more variation.
550 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
551 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
556 not_worth_the_effort
:
558 * if we did not find an IRQ to move, then adjust the time interval
561 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
562 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
563 Dprintk("IRQ worth rotating not found\n");
567 static int balanced_irq(void *unused
)
570 unsigned long prev_balance_time
= jiffies
;
571 long time_remaining
= balanced_irq_interval
;
575 /* push everything to CPU 0 to give us a starting point. */
576 for (i
= 0 ; i
< NR_IRQS
; i
++) {
577 pending_irq_cpumask
[i
] = cpumask_of_cpu(0);
578 set_pending_irq(i
, cpumask_of_cpu(0));
582 time_remaining
= schedule_timeout_interruptible(time_remaining
);
584 if (time_after(jiffies
,
585 prev_balance_time
+balanced_irq_interval
)) {
588 prev_balance_time
= jiffies
;
589 time_remaining
= balanced_irq_interval
;
596 static int __init
balanced_irq_init(void)
599 struct cpuinfo_x86
*c
;
602 cpus_shift_right(tmp
, cpu_online_map
, 2);
604 /* When not overwritten by the command line ask subarchitecture. */
605 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
606 irqbalance_disabled
= NO_BALANCE_IRQ
;
607 if (irqbalance_disabled
)
610 /* disable irqbalance completely if there is only one processor online */
611 if (num_online_cpus() < 2) {
612 irqbalance_disabled
= 1;
616 * Enable physical balance only if more than 1 physical processor
619 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
620 physical_balance
= 1;
622 for (i
= 0; i
< NR_CPUS
; i
++) {
625 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
626 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
627 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
628 printk(KERN_ERR
"balanced_irq_init: out of memory");
631 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
632 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
635 printk(KERN_INFO
"Starting balanced_irq\n");
636 if (kernel_thread(balanced_irq
, NULL
, CLONE_KERNEL
) >= 0)
639 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
641 for (i
= 0; i
< NR_CPUS
; i
++) {
642 kfree(irq_cpu_data
[i
].irq_delta
);
643 kfree(irq_cpu_data
[i
].last_irq
);
648 int __init
irqbalance_disable(char *str
)
650 irqbalance_disabled
= 1;
654 __setup("noirqbalance", irqbalance_disable
);
656 late_initcall(balanced_irq_init
);
657 #endif /* CONFIG_IRQBALANCE */
658 #endif /* CONFIG_SMP */
661 void fastcall
send_IPI_self(int vector
)
668 apic_wait_icr_idle();
669 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
671 * Send the IPI. The write to APIC_ICR fires this off.
673 apic_write_around(APIC_ICR
, cfg
);
675 #endif /* !CONFIG_SMP */
679 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
680 * specific CPU-side IRQs.
684 static int pirq_entries
[MAX_PIRQS
];
685 static int pirqs_enabled
;
686 int skip_ioapic_setup
;
688 static int __init
ioapic_setup(char *str
)
690 skip_ioapic_setup
= 1;
694 __setup("noapic", ioapic_setup
);
696 static int __init
ioapic_pirq_setup(char *str
)
699 int ints
[MAX_PIRQS
+1];
701 get_options(str
, ARRAY_SIZE(ints
), ints
);
703 for (i
= 0; i
< MAX_PIRQS
; i
++)
704 pirq_entries
[i
] = -1;
707 apic_printk(APIC_VERBOSE
, KERN_INFO
708 "PIRQ redirection, working around broken MP-BIOS.\n");
710 if (ints
[0] < MAX_PIRQS
)
713 for (i
= 0; i
< max
; i
++) {
714 apic_printk(APIC_VERBOSE
, KERN_DEBUG
715 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
717 * PIRQs are mapped upside down, usually.
719 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
724 __setup("pirq=", ioapic_pirq_setup
);
727 * Find the IRQ entry number of a certain pin.
729 static int find_irq_entry(int apic
, int pin
, int type
)
733 for (i
= 0; i
< mp_irq_entries
; i
++)
734 if (mp_irqs
[i
].mpc_irqtype
== type
&&
735 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
736 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
737 mp_irqs
[i
].mpc_dstirq
== pin
)
744 * Find the pin to which IRQ[irq] (ISA) is connected
746 static int __init
find_isa_irq_pin(int irq
, int type
)
750 for (i
= 0; i
< mp_irq_entries
; i
++) {
751 int lbus
= mp_irqs
[i
].mpc_srcbus
;
753 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
754 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
755 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
756 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
758 (mp_irqs
[i
].mpc_irqtype
== type
) &&
759 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
761 return mp_irqs
[i
].mpc_dstirq
;
766 static int __init
find_isa_irq_apic(int irq
, int type
)
770 for (i
= 0; i
< mp_irq_entries
; i
++) {
771 int lbus
= mp_irqs
[i
].mpc_srcbus
;
773 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
774 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
775 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
776 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
778 (mp_irqs
[i
].mpc_irqtype
== type
) &&
779 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
782 if (i
< mp_irq_entries
) {
784 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
785 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
794 * Find a specific PCI IRQ entry.
795 * Not an __init, possibly needed by modules
797 static int pin_2_irq(int idx
, int apic
, int pin
);
799 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
801 int apic
, i
, best_guess
= -1;
803 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
804 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
805 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
806 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
809 for (i
= 0; i
< mp_irq_entries
; i
++) {
810 int lbus
= mp_irqs
[i
].mpc_srcbus
;
812 for (apic
= 0; apic
< nr_ioapics
; apic
++)
813 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
814 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
817 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
818 !mp_irqs
[i
].mpc_irqtype
&&
820 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
821 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
823 if (!(apic
|| IO_APIC_IRQ(irq
)))
826 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
829 * Use the first all-but-pin matching entry as a
830 * best-guess fuzzy result for broken mptables.
838 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
841 * This function currently is only a helper for the i386 smp boot process where
842 * we need to reprogram the ioredtbls to cater for the cpus which have come online
843 * so mask in all cases should simply be TARGET_CPUS
846 void __init
setup_ioapic_dest(void)
848 int pin
, ioapic
, irq
, irq_entry
;
850 if (skip_ioapic_setup
== 1)
853 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
854 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
855 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
858 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
859 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
867 * EISA Edge/Level control register, ELCR
869 static int EISA_ELCR(unsigned int irq
)
872 unsigned int port
= 0x4d0 + (irq
>> 3);
873 return (inb(port
) >> (irq
& 7)) & 1;
875 apic_printk(APIC_VERBOSE
, KERN_INFO
876 "Broken MPtable reports ISA irq %d\n", irq
);
880 /* EISA interrupts are always polarity zero and can be edge or level
881 * trigger depending on the ELCR value. If an interrupt is listed as
882 * EISA conforming in the MP table, that means its trigger type must
883 * be read in from the ELCR */
885 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
886 #define default_EISA_polarity(idx) (0)
888 /* ISA interrupts are always polarity zero edge triggered,
889 * when listed as conforming in the MP table. */
891 #define default_ISA_trigger(idx) (0)
892 #define default_ISA_polarity(idx) (0)
894 /* PCI interrupts are always polarity one level triggered,
895 * when listed as conforming in the MP table. */
897 #define default_PCI_trigger(idx) (1)
898 #define default_PCI_polarity(idx) (1)
900 /* MCA interrupts are always polarity zero level triggered,
901 * when listed as conforming in the MP table. */
903 #define default_MCA_trigger(idx) (1)
904 #define default_MCA_polarity(idx) (0)
906 /* NEC98 interrupts are always polarity zero edge triggered,
907 * when listed as conforming in the MP table. */
909 #define default_NEC98_trigger(idx) (0)
910 #define default_NEC98_polarity(idx) (0)
912 static int __init
MPBIOS_polarity(int idx
)
914 int bus
= mp_irqs
[idx
].mpc_srcbus
;
918 * Determine IRQ line polarity (high active or low active):
920 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
922 case 0: /* conforms, ie. bus-type dependent polarity */
924 switch (mp_bus_id_to_type
[bus
])
926 case MP_BUS_ISA
: /* ISA pin */
928 polarity
= default_ISA_polarity(idx
);
931 case MP_BUS_EISA
: /* EISA pin */
933 polarity
= default_EISA_polarity(idx
);
936 case MP_BUS_PCI
: /* PCI pin */
938 polarity
= default_PCI_polarity(idx
);
941 case MP_BUS_MCA
: /* MCA pin */
943 polarity
= default_MCA_polarity(idx
);
946 case MP_BUS_NEC98
: /* NEC 98 pin */
948 polarity
= default_NEC98_polarity(idx
);
953 printk(KERN_WARNING
"broken BIOS!!\n");
960 case 1: /* high active */
965 case 2: /* reserved */
967 printk(KERN_WARNING
"broken BIOS!!\n");
971 case 3: /* low active */
976 default: /* invalid */
978 printk(KERN_WARNING
"broken BIOS!!\n");
986 static int MPBIOS_trigger(int idx
)
988 int bus
= mp_irqs
[idx
].mpc_srcbus
;
992 * Determine IRQ trigger mode (edge or level sensitive):
994 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
996 case 0: /* conforms, ie. bus-type dependent */
998 switch (mp_bus_id_to_type
[bus
])
1000 case MP_BUS_ISA
: /* ISA pin */
1002 trigger
= default_ISA_trigger(idx
);
1005 case MP_BUS_EISA
: /* EISA pin */
1007 trigger
= default_EISA_trigger(idx
);
1010 case MP_BUS_PCI
: /* PCI pin */
1012 trigger
= default_PCI_trigger(idx
);
1015 case MP_BUS_MCA
: /* MCA pin */
1017 trigger
= default_MCA_trigger(idx
);
1020 case MP_BUS_NEC98
: /* NEC 98 pin */
1022 trigger
= default_NEC98_trigger(idx
);
1027 printk(KERN_WARNING
"broken BIOS!!\n");
1039 case 2: /* reserved */
1041 printk(KERN_WARNING
"broken BIOS!!\n");
1050 default: /* invalid */
1052 printk(KERN_WARNING
"broken BIOS!!\n");
1060 static inline int irq_polarity(int idx
)
1062 return MPBIOS_polarity(idx
);
1065 static inline int irq_trigger(int idx
)
1067 return MPBIOS_trigger(idx
);
1070 static int pin_2_irq(int idx
, int apic
, int pin
)
1073 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1076 * Debugging check, we are in big trouble if this message pops up!
1078 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1079 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1081 switch (mp_bus_id_to_type
[bus
])
1083 case MP_BUS_ISA
: /* ISA pin */
1088 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1091 case MP_BUS_PCI
: /* PCI pin */
1094 * PCI IRQs are mapped in order
1098 irq
+= nr_ioapic_registers
[i
++];
1102 * For MPS mode, so far only needed by ES7000 platform
1104 if (ioapic_renumber_irq
)
1105 irq
= ioapic_renumber_irq(apic
, irq
);
1111 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
1118 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1120 if ((pin
>= 16) && (pin
<= 23)) {
1121 if (pirq_entries
[pin
-16] != -1) {
1122 if (!pirq_entries
[pin
-16]) {
1123 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1124 "disabling PIRQ%d\n", pin
-16);
1126 irq
= pirq_entries
[pin
-16];
1127 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1128 "using PIRQ%d -> IRQ %d\n",
1136 static inline int IO_APIC_irq_trigger(int irq
)
1140 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1141 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1142 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1143 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1144 return irq_trigger(idx
);
1148 * nonexistent IRQs are edge default
1153 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1154 u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1156 int assign_irq_vector(int irq
)
1158 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
1160 BUG_ON(irq
>= NR_IRQ_VECTORS
);
1161 if (irq
!= AUTO_ASSIGN
&& IO_APIC_VECTOR(irq
) > 0)
1162 return IO_APIC_VECTOR(irq
);
1164 current_vector
+= 8;
1165 if (current_vector
== SYSCALL_VECTOR
)
1168 if (current_vector
>= FIRST_SYSTEM_VECTOR
) {
1172 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
1175 vector_irq
[current_vector
] = irq
;
1176 if (irq
!= AUTO_ASSIGN
)
1177 IO_APIC_VECTOR(irq
) = current_vector
;
1179 return current_vector
;
1182 static struct hw_interrupt_type ioapic_level_type
;
1183 static struct hw_interrupt_type ioapic_edge_type
;
1185 #define IOAPIC_AUTO -1
1186 #define IOAPIC_EDGE 0
1187 #define IOAPIC_LEVEL 1
1189 static inline void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1191 if (use_pci_vector() && !platform_legacy_irq(irq
)) {
1192 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1193 trigger
== IOAPIC_LEVEL
)
1194 irq_desc
[vector
].handler
= &ioapic_level_type
;
1196 irq_desc
[vector
].handler
= &ioapic_edge_type
;
1197 set_intr_gate(vector
, interrupt
[vector
]);
1199 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1200 trigger
== IOAPIC_LEVEL
)
1201 irq_desc
[irq
].handler
= &ioapic_level_type
;
1203 irq_desc
[irq
].handler
= &ioapic_edge_type
;
1204 set_intr_gate(vector
, interrupt
[irq
]);
1208 static void __init
setup_IO_APIC_irqs(void)
1210 struct IO_APIC_route_entry entry
;
1211 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1212 unsigned long flags
;
1214 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1216 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1217 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1220 * add it to the IO-APIC irq-routing table:
1222 memset(&entry
,0,sizeof(entry
));
1224 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1225 entry
.dest_mode
= INT_DEST_MODE
;
1226 entry
.mask
= 0; /* enable IRQ */
1227 entry
.dest
.logical
.logical_dest
=
1228 cpu_mask_to_apicid(TARGET_CPUS
);
1230 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1233 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1234 " IO-APIC (apicid-pin) %d-%d",
1235 mp_ioapics
[apic
].mpc_apicid
,
1239 apic_printk(APIC_VERBOSE
, ", %d-%d",
1240 mp_ioapics
[apic
].mpc_apicid
, pin
);
1244 entry
.trigger
= irq_trigger(idx
);
1245 entry
.polarity
= irq_polarity(idx
);
1247 if (irq_trigger(idx
)) {
1252 irq
= pin_2_irq(idx
, apic
, pin
);
1254 * skip adding the timer int on secondary nodes, which causes
1255 * a small but painful rift in the time-space continuum
1257 if (multi_timer_check(apic
, irq
))
1260 add_pin_to_irq(irq
, apic
, pin
);
1262 if (!apic
&& !IO_APIC_IRQ(irq
))
1265 if (IO_APIC_IRQ(irq
)) {
1266 vector
= assign_irq_vector(irq
);
1267 entry
.vector
= vector
;
1268 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1270 if (!apic
&& (irq
< 16))
1271 disable_8259A_irq(irq
);
1273 spin_lock_irqsave(&ioapic_lock
, flags
);
1274 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
1275 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
1276 set_native_irq_info(irq
, TARGET_CPUS
);
1277 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1282 apic_printk(APIC_VERBOSE
, " not connected.\n");
1286 * Set up the 8259A-master output pin:
1288 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
1290 struct IO_APIC_route_entry entry
;
1291 unsigned long flags
;
1293 memset(&entry
,0,sizeof(entry
));
1295 disable_8259A_irq(0);
1298 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1301 * We use logical delivery to get the timer IRQ
1304 entry
.dest_mode
= INT_DEST_MODE
;
1305 entry
.mask
= 0; /* unmask IRQ now */
1306 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1307 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1310 entry
.vector
= vector
;
1313 * The timer IRQ doesn't have to know that behind the
1314 * scene we have a 8259A-master in AEOI mode ...
1316 irq_desc
[0].handler
= &ioapic_edge_type
;
1319 * Add it to the IO-APIC irq-routing table:
1321 spin_lock_irqsave(&ioapic_lock
, flags
);
1322 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
1323 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
1324 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1326 enable_8259A_irq(0);
1329 static inline void UNEXPECTED_IO_APIC(void)
1333 void __init
print_IO_APIC(void)
1336 union IO_APIC_reg_00 reg_00
;
1337 union IO_APIC_reg_01 reg_01
;
1338 union IO_APIC_reg_02 reg_02
;
1339 union IO_APIC_reg_03 reg_03
;
1340 unsigned long flags
;
1342 if (apic_verbosity
== APIC_QUIET
)
1345 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1346 for (i
= 0; i
< nr_ioapics
; i
++)
1347 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1348 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1351 * We are a bit conservative about what we expect. We have to
1352 * know about every hardware change ASAP.
1354 printk(KERN_INFO
"testing the IO APIC.......................\n");
1356 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1358 spin_lock_irqsave(&ioapic_lock
, flags
);
1359 reg_00
.raw
= io_apic_read(apic
, 0);
1360 reg_01
.raw
= io_apic_read(apic
, 1);
1361 if (reg_01
.bits
.version
>= 0x10)
1362 reg_02
.raw
= io_apic_read(apic
, 2);
1363 if (reg_01
.bits
.version
>= 0x20)
1364 reg_03
.raw
= io_apic_read(apic
, 3);
1365 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1367 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1368 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1369 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1370 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1371 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1372 if (reg_00
.bits
.ID
>= get_physical_broadcast())
1373 UNEXPECTED_IO_APIC();
1374 if (reg_00
.bits
.__reserved_1
|| reg_00
.bits
.__reserved_2
)
1375 UNEXPECTED_IO_APIC();
1377 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1378 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1379 if ( (reg_01
.bits
.entries
!= 0x0f) && /* older (Neptune) boards */
1380 (reg_01
.bits
.entries
!= 0x17) && /* typical ISA+PCI boards */
1381 (reg_01
.bits
.entries
!= 0x1b) && /* Compaq Proliant boards */
1382 (reg_01
.bits
.entries
!= 0x1f) && /* dual Xeon boards */
1383 (reg_01
.bits
.entries
!= 0x22) && /* bigger Xeon boards */
1384 (reg_01
.bits
.entries
!= 0x2E) &&
1385 (reg_01
.bits
.entries
!= 0x3F)
1387 UNEXPECTED_IO_APIC();
1389 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1390 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1391 if ( (reg_01
.bits
.version
!= 0x01) && /* 82489DX IO-APICs */
1392 (reg_01
.bits
.version
!= 0x10) && /* oldest IO-APICs */
1393 (reg_01
.bits
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
1394 (reg_01
.bits
.version
!= 0x13) && /* Xeon IO-APICs */
1395 (reg_01
.bits
.version
!= 0x20) /* Intel P64H (82806 AA) */
1397 UNEXPECTED_IO_APIC();
1398 if (reg_01
.bits
.__reserved_1
|| reg_01
.bits
.__reserved_2
)
1399 UNEXPECTED_IO_APIC();
1402 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1403 * but the value of reg_02 is read as the previous read register
1404 * value, so ignore it if reg_02 == reg_01.
1406 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1407 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1408 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1409 if (reg_02
.bits
.__reserved_1
|| reg_02
.bits
.__reserved_2
)
1410 UNEXPECTED_IO_APIC();
1414 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1415 * or reg_03, but the value of reg_0[23] is read as the previous read
1416 * register value, so ignore it if reg_03 == reg_0[12].
1418 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1419 reg_03
.raw
!= reg_01
.raw
) {
1420 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1421 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1422 if (reg_03
.bits
.__reserved_1
)
1423 UNEXPECTED_IO_APIC();
1426 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1428 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1429 " Stat Dest Deli Vect: \n");
1431 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1432 struct IO_APIC_route_entry entry
;
1434 spin_lock_irqsave(&ioapic_lock
, flags
);
1435 *(((int *)&entry
)+0) = io_apic_read(apic
, 0x10+i
*2);
1436 *(((int *)&entry
)+1) = io_apic_read(apic
, 0x11+i
*2);
1437 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1439 printk(KERN_DEBUG
" %02x %03X %02X ",
1441 entry
.dest
.logical
.logical_dest
,
1442 entry
.dest
.physical
.physical_dest
1445 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1450 entry
.delivery_status
,
1452 entry
.delivery_mode
,
1457 if (use_pci_vector())
1458 printk(KERN_INFO
"Using vector-based indexing\n");
1459 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1460 for (i
= 0; i
< NR_IRQS
; i
++) {
1461 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1464 if (use_pci_vector() && !platform_legacy_irq(i
))
1465 printk(KERN_DEBUG
"IRQ%d ", IO_APIC_VECTOR(i
));
1467 printk(KERN_DEBUG
"IRQ%d ", i
);
1469 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1472 entry
= irq_2_pin
+ entry
->next
;
1477 printk(KERN_INFO
".................................... done.\n");
1484 static void print_APIC_bitfield (int base
)
1489 if (apic_verbosity
== APIC_QUIET
)
1492 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1493 for (i
= 0; i
< 8; i
++) {
1494 v
= apic_read(base
+ i
*0x10);
1495 for (j
= 0; j
< 32; j
++) {
1505 void /*__init*/ print_local_APIC(void * dummy
)
1507 unsigned int v
, ver
, maxlvt
;
1509 if (apic_verbosity
== APIC_QUIET
)
1512 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1513 smp_processor_id(), hard_smp_processor_id());
1514 v
= apic_read(APIC_ID
);
1515 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1516 v
= apic_read(APIC_LVR
);
1517 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1518 ver
= GET_APIC_VERSION(v
);
1519 maxlvt
= get_maxlvt();
1521 v
= apic_read(APIC_TASKPRI
);
1522 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1524 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1525 v
= apic_read(APIC_ARBPRI
);
1526 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1527 v
& APIC_ARBPRI_MASK
);
1528 v
= apic_read(APIC_PROCPRI
);
1529 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1532 v
= apic_read(APIC_EOI
);
1533 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1534 v
= apic_read(APIC_RRR
);
1535 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1536 v
= apic_read(APIC_LDR
);
1537 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1538 v
= apic_read(APIC_DFR
);
1539 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1540 v
= apic_read(APIC_SPIV
);
1541 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1543 printk(KERN_DEBUG
"... APIC ISR field:\n");
1544 print_APIC_bitfield(APIC_ISR
);
1545 printk(KERN_DEBUG
"... APIC TMR field:\n");
1546 print_APIC_bitfield(APIC_TMR
);
1547 printk(KERN_DEBUG
"... APIC IRR field:\n");
1548 print_APIC_bitfield(APIC_IRR
);
1550 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1551 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1552 apic_write(APIC_ESR
, 0);
1553 v
= apic_read(APIC_ESR
);
1554 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1557 v
= apic_read(APIC_ICR
);
1558 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1559 v
= apic_read(APIC_ICR2
);
1560 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1562 v
= apic_read(APIC_LVTT
);
1563 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1565 if (maxlvt
> 3) { /* PC is LVT#4. */
1566 v
= apic_read(APIC_LVTPC
);
1567 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1569 v
= apic_read(APIC_LVT0
);
1570 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1571 v
= apic_read(APIC_LVT1
);
1572 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1574 if (maxlvt
> 2) { /* ERR is LVT#3. */
1575 v
= apic_read(APIC_LVTERR
);
1576 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1579 v
= apic_read(APIC_TMICT
);
1580 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1581 v
= apic_read(APIC_TMCCT
);
1582 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1583 v
= apic_read(APIC_TDCR
);
1584 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1588 void print_all_local_APICs (void)
1590 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1593 void /*__init*/ print_PIC(void)
1596 unsigned long flags
;
1598 if (apic_verbosity
== APIC_QUIET
)
1601 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1603 spin_lock_irqsave(&i8259A_lock
, flags
);
1605 v
= inb(0xa1) << 8 | inb(0x21);
1606 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1608 v
= inb(0xa0) << 8 | inb(0x20);
1609 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1613 v
= inb(0xa0) << 8 | inb(0x20);
1617 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1619 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1621 v
= inb(0x4d1) << 8 | inb(0x4d0);
1622 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1627 static void __init
enable_IO_APIC(void)
1629 union IO_APIC_reg_01 reg_01
;
1630 int i8259_apic
, i8259_pin
;
1632 unsigned long flags
;
1634 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1635 irq_2_pin
[i
].pin
= -1;
1636 irq_2_pin
[i
].next
= 0;
1639 for (i
= 0; i
< MAX_PIRQS
; i
++)
1640 pirq_entries
[i
] = -1;
1643 * The number of IO-APIC IRQ registers (== #pins):
1645 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1646 spin_lock_irqsave(&ioapic_lock
, flags
);
1647 reg_01
.raw
= io_apic_read(apic
, 1);
1648 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1649 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1651 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1653 /* See if any of the pins is in ExtINT mode */
1654 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1655 struct IO_APIC_route_entry entry
;
1656 spin_lock_irqsave(&ioapic_lock
, flags
);
1657 *(((int *)&entry
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
1658 *(((int *)&entry
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
1659 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1662 /* If the interrupt line is enabled and in ExtInt mode
1663 * I have found the pin where the i8259 is connected.
1665 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1666 ioapic_i8259
.apic
= apic
;
1667 ioapic_i8259
.pin
= pin
;
1673 /* Look to see what if the MP table has reported the ExtINT */
1674 /* If we could not find the appropriate pin by looking at the ioapic
1675 * the i8259 probably is not connected the ioapic but give the
1676 * mptable a chance anyway.
1678 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1679 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1680 /* Trust the MP table if nothing is setup in the hardware */
1681 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1682 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1683 ioapic_i8259
.pin
= i8259_pin
;
1684 ioapic_i8259
.apic
= i8259_apic
;
1686 /* Complain if the MP table and the hardware disagree */
1687 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1688 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1690 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1694 * Do not trust the IO-APIC being empty at bootup
1700 * Not an __init, needed by the reboot code
1702 void disable_IO_APIC(void)
1705 * Clear the IO-APIC before rebooting:
1710 * If the i8259 is routed through an IOAPIC
1711 * Put that IOAPIC in virtual wire mode
1712 * so legacy interrupts can be delivered.
1714 if (ioapic_i8259
.pin
!= -1) {
1715 struct IO_APIC_route_entry entry
;
1716 unsigned long flags
;
1718 memset(&entry
, 0, sizeof(entry
));
1719 entry
.mask
= 0; /* Enabled */
1720 entry
.trigger
= 0; /* Edge */
1722 entry
.polarity
= 0; /* High */
1723 entry
.delivery_status
= 0;
1724 entry
.dest_mode
= 0; /* Physical */
1725 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1727 entry
.dest
.physical
.physical_dest
=
1728 GET_APIC_ID(apic_read(APIC_ID
));
1731 * Add it to the IO-APIC irq-routing table:
1733 spin_lock_irqsave(&ioapic_lock
, flags
);
1734 io_apic_write(ioapic_i8259
.apic
, 0x11+2*ioapic_i8259
.pin
,
1735 *(((int *)&entry
)+1));
1736 io_apic_write(ioapic_i8259
.apic
, 0x10+2*ioapic_i8259
.pin
,
1737 *(((int *)&entry
)+0));
1738 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1740 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1744 * function to set the IO-APIC physical IDs based on the
1745 * values stored in the MPC table.
1747 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1750 #ifndef CONFIG_X86_NUMAQ
1751 static void __init
setup_ioapic_ids_from_mpc(void)
1753 union IO_APIC_reg_00 reg_00
;
1754 physid_mask_t phys_id_present_map
;
1757 unsigned char old_id
;
1758 unsigned long flags
;
1761 * Don't check I/O APIC IDs for xAPIC systems. They have
1762 * no meaning without the serial APIC bus.
1764 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
&& boot_cpu_data
.x86
< 15))
1767 * This is broken; anything with a real cpu count has to
1768 * circumvent this idiocy regardless.
1770 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1773 * Set the IOAPIC ID to the value stored in the MPC table.
1775 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1777 /* Read the register 0 value */
1778 spin_lock_irqsave(&ioapic_lock
, flags
);
1779 reg_00
.raw
= io_apic_read(apic
, 0);
1780 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1782 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1784 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1785 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1786 apic
, mp_ioapics
[apic
].mpc_apicid
);
1787 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1789 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1793 * Sanity check, is the ID really free? Every APIC in a
1794 * system must have a unique ID or we get lots of nice
1795 * 'stuck on smp_invalidate_needed IPI wait' messages.
1797 if (check_apicid_used(phys_id_present_map
,
1798 mp_ioapics
[apic
].mpc_apicid
)) {
1799 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1800 apic
, mp_ioapics
[apic
].mpc_apicid
);
1801 for (i
= 0; i
< get_physical_broadcast(); i
++)
1802 if (!physid_isset(i
, phys_id_present_map
))
1804 if (i
>= get_physical_broadcast())
1805 panic("Max APIC ID exceeded!\n");
1806 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1808 physid_set(i
, phys_id_present_map
);
1809 mp_ioapics
[apic
].mpc_apicid
= i
;
1812 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1813 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1814 "phys_id_present_map\n",
1815 mp_ioapics
[apic
].mpc_apicid
);
1816 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1821 * We need to adjust the IRQ routing table
1822 * if the ID changed.
1824 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1825 for (i
= 0; i
< mp_irq_entries
; i
++)
1826 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1827 mp_irqs
[i
].mpc_dstapic
1828 = mp_ioapics
[apic
].mpc_apicid
;
1831 * Read the right value from the MPC table and
1832 * write it into the ID register.
1834 apic_printk(APIC_VERBOSE
, KERN_INFO
1835 "...changing IO-APIC physical APIC ID to %d ...",
1836 mp_ioapics
[apic
].mpc_apicid
);
1838 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1839 spin_lock_irqsave(&ioapic_lock
, flags
);
1840 io_apic_write(apic
, 0, reg_00
.raw
);
1841 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1846 spin_lock_irqsave(&ioapic_lock
, flags
);
1847 reg_00
.raw
= io_apic_read(apic
, 0);
1848 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1849 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1850 printk("could not set ID!\n");
1852 apic_printk(APIC_VERBOSE
, " ok.\n");
1856 static void __init
setup_ioapic_ids_from_mpc(void) { }
1860 * There is a nasty bug in some older SMP boards, their mptable lies
1861 * about the timer IRQ. We do the following to work around the situation:
1863 * - timer IRQ defaults to IO-APIC IRQ
1864 * - if this function detects that timer IRQs are defunct, then we fall
1865 * back to ISA timer IRQs
1867 static int __init
timer_irq_works(void)
1869 unsigned long t1
= jiffies
;
1872 /* Let ten ticks pass... */
1873 mdelay((10 * 1000) / HZ
);
1876 * Expect a few ticks at least, to be sure some possible
1877 * glue logic does not lock up after one or two first
1878 * ticks in a non-ExtINT mode. Also the local APIC
1879 * might have cached one ExtINT interrupt. Finally, at
1880 * least one tick may be lost due to delays.
1882 if (jiffies
- t1
> 4)
1889 * In the SMP+IOAPIC case it might happen that there are an unspecified
1890 * number of pending IRQ events unhandled. These cases are very rare,
1891 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1892 * better to do it this way as thus we do not have to be aware of
1893 * 'pending' interrupts in the IRQ path, except at this point.
1896 * Edge triggered needs to resend any interrupt
1897 * that was delayed but this is now handled in the device
1902 * Starting up a edge-triggered IO-APIC interrupt is
1903 * nasty - we need to make sure that we get the edge.
1904 * If it is already asserted for some reason, we need
1905 * return 1 to indicate that is was pending.
1907 * This is not complete - we should be able to fake
1908 * an edge even if it isn't on the 8259A...
1910 static unsigned int startup_edge_ioapic_irq(unsigned int irq
)
1912 int was_pending
= 0;
1913 unsigned long flags
;
1915 spin_lock_irqsave(&ioapic_lock
, flags
);
1917 disable_8259A_irq(irq
);
1918 if (i8259A_irq_pending(irq
))
1921 __unmask_IO_APIC_irq(irq
);
1922 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1928 * Once we have recorded IRQ_PENDING already, we can mask the
1929 * interrupt for real. This prevents IRQ storms from unhandled
1932 static void ack_edge_ioapic_irq(unsigned int irq
)
1935 if ((irq_desc
[irq
].status
& (IRQ_PENDING
| IRQ_DISABLED
))
1936 == (IRQ_PENDING
| IRQ_DISABLED
))
1937 mask_IO_APIC_irq(irq
);
1942 * Level triggered interrupts can just be masked,
1943 * and shutting down and starting up the interrupt
1944 * is the same as enabling and disabling them -- except
1945 * with a startup need to return a "was pending" value.
1947 * Level triggered interrupts are special because we
1948 * do not touch any IO-APIC register while handling
1949 * them. We ack the APIC in the end-IRQ handler, not
1950 * in the start-IRQ-handler. Protection against reentrance
1951 * from the same interrupt is still provided, both by the
1952 * generic IRQ layer and by the fact that an unacked local
1953 * APIC does not accept IRQs.
1955 static unsigned int startup_level_ioapic_irq (unsigned int irq
)
1957 unmask_IO_APIC_irq(irq
);
1959 return 0; /* don't check for pending */
1962 static void end_level_ioapic_irq (unsigned int irq
)
1969 * It appears there is an erratum which affects at least version 0x11
1970 * of I/O APIC (that's the 82093AA and cores integrated into various
1971 * chipsets). Under certain conditions a level-triggered interrupt is
1972 * erroneously delivered as edge-triggered one but the respective IRR
1973 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1974 * message but it will never arrive and further interrupts are blocked
1975 * from the source. The exact reason is so far unknown, but the
1976 * phenomenon was observed when two consecutive interrupt requests
1977 * from a given source get delivered to the same CPU and the source is
1978 * temporarily disabled in between.
1980 * A workaround is to simulate an EOI message manually. We achieve it
1981 * by setting the trigger mode to edge and then to level when the edge
1982 * trigger mode gets detected in the TMR of a local APIC for a
1983 * level-triggered interrupt. We mask the source for the time of the
1984 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1985 * The idea is from Manfred Spraul. --macro
1987 i
= IO_APIC_VECTOR(irq
);
1989 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1993 if (!(v
& (1 << (i
& 0x1f)))) {
1994 atomic_inc(&irq_mis_count
);
1995 spin_lock(&ioapic_lock
);
1996 __mask_and_edge_IO_APIC_irq(irq
);
1997 __unmask_and_level_IO_APIC_irq(irq
);
1998 spin_unlock(&ioapic_lock
);
2002 #ifdef CONFIG_PCI_MSI
2003 static unsigned int startup_edge_ioapic_vector(unsigned int vector
)
2005 int irq
= vector_to_irq(vector
);
2007 return startup_edge_ioapic_irq(irq
);
2010 static void ack_edge_ioapic_vector(unsigned int vector
)
2012 int irq
= vector_to_irq(vector
);
2014 move_native_irq(vector
);
2015 ack_edge_ioapic_irq(irq
);
2018 static unsigned int startup_level_ioapic_vector (unsigned int vector
)
2020 int irq
= vector_to_irq(vector
);
2022 return startup_level_ioapic_irq (irq
);
2025 static void end_level_ioapic_vector (unsigned int vector
)
2027 int irq
= vector_to_irq(vector
);
2029 move_native_irq(vector
);
2030 end_level_ioapic_irq(irq
);
2033 static void mask_IO_APIC_vector (unsigned int vector
)
2035 int irq
= vector_to_irq(vector
);
2037 mask_IO_APIC_irq(irq
);
2040 static void unmask_IO_APIC_vector (unsigned int vector
)
2042 int irq
= vector_to_irq(vector
);
2044 unmask_IO_APIC_irq(irq
);
2048 static void set_ioapic_affinity_vector (unsigned int vector
,
2051 int irq
= vector_to_irq(vector
);
2053 set_native_irq_info(vector
, cpu_mask
);
2054 set_ioapic_affinity_irq(irq
, cpu_mask
);
2060 * Level and edge triggered IO-APIC interrupts need different handling,
2061 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2062 * handled with the level-triggered descriptor, but that one has slightly
2063 * more overhead. Level-triggered interrupts cannot be handled with the
2064 * edge-triggered handler, without risking IRQ storms and other ugly
2067 static struct hw_interrupt_type ioapic_edge_type __read_mostly
= {
2068 .typename
= "IO-APIC-edge",
2069 .startup
= startup_edge_ioapic
,
2070 .shutdown
= shutdown_edge_ioapic
,
2071 .enable
= enable_edge_ioapic
,
2072 .disable
= disable_edge_ioapic
,
2073 .ack
= ack_edge_ioapic
,
2074 .end
= end_edge_ioapic
,
2076 .set_affinity
= set_ioapic_affinity
,
2080 static struct hw_interrupt_type ioapic_level_type __read_mostly
= {
2081 .typename
= "IO-APIC-level",
2082 .startup
= startup_level_ioapic
,
2083 .shutdown
= shutdown_level_ioapic
,
2084 .enable
= enable_level_ioapic
,
2085 .disable
= disable_level_ioapic
,
2086 .ack
= mask_and_ack_level_ioapic
,
2087 .end
= end_level_ioapic
,
2089 .set_affinity
= set_ioapic_affinity
,
2093 static inline void init_IO_APIC_traps(void)
2098 * NOTE! The local APIC isn't very good at handling
2099 * multiple interrupts at the same interrupt level.
2100 * As the interrupt level is determined by taking the
2101 * vector number and shifting that right by 4, we
2102 * want to spread these out a bit so that they don't
2103 * all fall in the same interrupt level.
2105 * Also, we've got to be careful not to trash gate
2106 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2108 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
2110 if (use_pci_vector()) {
2111 if (!platform_legacy_irq(tmp
))
2112 if ((tmp
= vector_to_irq(tmp
)) == -1)
2115 if (IO_APIC_IRQ(tmp
) && !IO_APIC_VECTOR(tmp
)) {
2117 * Hmm.. We don't have an entry for this,
2118 * so default to an old-fashioned 8259
2119 * interrupt if we can..
2122 make_8259A_irq(irq
);
2124 /* Strange. Oh, well.. */
2125 irq_desc
[irq
].handler
= &no_irq_type
;
2130 static void enable_lapic_irq (unsigned int irq
)
2134 v
= apic_read(APIC_LVT0
);
2135 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2138 static void disable_lapic_irq (unsigned int irq
)
2142 v
= apic_read(APIC_LVT0
);
2143 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2146 static void ack_lapic_irq (unsigned int irq
)
2151 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
2153 static struct hw_interrupt_type lapic_irq_type __read_mostly
= {
2154 .typename
= "local-APIC-edge",
2155 .startup
= NULL
, /* startup_irq() not used for IRQ0 */
2156 .shutdown
= NULL
, /* shutdown_irq() not used for IRQ0 */
2157 .enable
= enable_lapic_irq
,
2158 .disable
= disable_lapic_irq
,
2159 .ack
= ack_lapic_irq
,
2160 .end
= end_lapic_irq
2163 static void setup_nmi (void)
2166 * Dirty trick to enable the NMI watchdog ...
2167 * We put the 8259A master into AEOI mode and
2168 * unmask on all local APICs LVT0 as NMI.
2170 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2171 * is from Maciej W. Rozycki - so we do not have to EOI from
2172 * the NMI handler or the timer interrupt.
2174 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2176 on_each_cpu(enable_NMI_through_LVT0
, NULL
, 1, 1);
2178 apic_printk(APIC_VERBOSE
, " done.\n");
2182 * This looks a bit hackish but it's about the only one way of sending
2183 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2184 * not support the ExtINT mode, unfortunately. We need to send these
2185 * cycles as some i82489DX-based boards have glue logic that keeps the
2186 * 8259A interrupt line asserted until INTA. --macro
2188 static inline void unlock_ExtINT_logic(void)
2191 struct IO_APIC_route_entry entry0
, entry1
;
2192 unsigned char save_control
, save_freq_select
;
2193 unsigned long flags
;
2195 pin
= find_isa_irq_pin(8, mp_INT
);
2196 apic
= find_isa_irq_apic(8, mp_INT
);
2200 spin_lock_irqsave(&ioapic_lock
, flags
);
2201 *(((int *)&entry0
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
2202 *(((int *)&entry0
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
2203 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2204 clear_IO_APIC_pin(apic
, pin
);
2206 memset(&entry1
, 0, sizeof(entry1
));
2208 entry1
.dest_mode
= 0; /* physical delivery */
2209 entry1
.mask
= 0; /* unmask IRQ now */
2210 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2211 entry1
.delivery_mode
= dest_ExtINT
;
2212 entry1
.polarity
= entry0
.polarity
;
2216 spin_lock_irqsave(&ioapic_lock
, flags
);
2217 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry1
) + 1));
2218 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry1
) + 0));
2219 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2221 save_control
= CMOS_READ(RTC_CONTROL
);
2222 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2223 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2225 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2230 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2234 CMOS_WRITE(save_control
, RTC_CONTROL
);
2235 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2236 clear_IO_APIC_pin(apic
, pin
);
2238 spin_lock_irqsave(&ioapic_lock
, flags
);
2239 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry0
) + 1));
2240 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry0
) + 0));
2241 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2245 * This code may look a bit paranoid, but it's supposed to cooperate with
2246 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2247 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2248 * fanatically on his truly buggy board.
2250 static inline void check_timer(void)
2252 int apic1
, pin1
, apic2
, pin2
;
2256 * get/set the timer IRQ vector:
2258 disable_8259A_irq(0);
2259 vector
= assign_irq_vector(0);
2260 set_intr_gate(vector
, interrupt
[0]);
2263 * Subtle, code in do_timer_interrupt() expects an AEOI
2264 * mode for the 8259A whenever interrupts are routed
2265 * through I/O APICs. Also IRQ0 has to be enabled in
2266 * the 8259A which implies the virtual wire has to be
2267 * disabled in the local APIC.
2269 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2272 if (timer_over_8254
> 0)
2273 enable_8259A_irq(0);
2275 pin1
= find_isa_irq_pin(0, mp_INT
);
2276 apic1
= find_isa_irq_apic(0, mp_INT
);
2277 pin2
= ioapic_i8259
.pin
;
2278 apic2
= ioapic_i8259
.apic
;
2280 printk(KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2281 vector
, apic1
, pin1
, apic2
, pin2
);
2285 * Ok, does IRQ0 through the IOAPIC work?
2287 unmask_IO_APIC_irq(0);
2288 if (timer_irq_works()) {
2289 if (nmi_watchdog
== NMI_IO_APIC
) {
2290 disable_8259A_irq(0);
2292 enable_8259A_irq(0);
2294 if (disable_timer_pin_1
> 0)
2295 clear_IO_APIC_pin(0, pin1
);
2298 clear_IO_APIC_pin(apic1
, pin1
);
2299 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to "
2303 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2305 printk("\n..... (found pin %d) ...", pin2
);
2307 * legacy devices should be connected to IO APIC #0
2309 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
2310 if (timer_irq_works()) {
2313 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2315 add_pin_to_irq(0, apic2
, pin2
);
2316 if (nmi_watchdog
== NMI_IO_APIC
) {
2322 * Cleanup, just in case ...
2324 clear_IO_APIC_pin(apic2
, pin2
);
2326 printk(" failed.\n");
2328 if (nmi_watchdog
== NMI_IO_APIC
) {
2329 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2333 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2335 disable_8259A_irq(0);
2336 irq_desc
[0].handler
= &lapic_irq_type
;
2337 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2338 enable_8259A_irq(0);
2340 if (timer_irq_works()) {
2341 printk(" works.\n");
2344 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2345 printk(" failed.\n");
2347 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2352 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2354 unlock_ExtINT_logic();
2356 if (timer_irq_works()) {
2357 printk(" works.\n");
2360 printk(" failed :(.\n");
2361 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2362 "report. Then try booting with the 'noapic' option");
2367 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2368 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2369 * Linux doesn't really care, as it's not actually used
2370 * for any interrupt handling anyway.
2372 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2374 void __init
setup_IO_APIC(void)
2379 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2381 io_apic_irqs
= ~PIC_IRQS
;
2383 printk("ENABLING IO-APIC IRQs\n");
2386 * Set up IO-APIC IRQ routing.
2389 setup_ioapic_ids_from_mpc();
2391 setup_IO_APIC_irqs();
2392 init_IO_APIC_traps();
2398 static int __init
setup_disable_8254_timer(char *s
)
2400 timer_over_8254
= -1;
2403 static int __init
setup_enable_8254_timer(char *s
)
2405 timer_over_8254
= 2;
2409 __setup("disable_8254_timer", setup_disable_8254_timer
);
2410 __setup("enable_8254_timer", setup_enable_8254_timer
);
2413 * Called after all the initialization is done. If we didnt find any
2414 * APIC bugs then we can allow the modify fast path
2417 static int __init
io_apic_bug_finalize(void)
2419 if(sis_apic_bug
== -1)
2424 late_initcall(io_apic_bug_finalize
);
2426 struct sysfs_ioapic_data
{
2427 struct sys_device dev
;
2428 struct IO_APIC_route_entry entry
[0];
2430 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2432 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2434 struct IO_APIC_route_entry
*entry
;
2435 struct sysfs_ioapic_data
*data
;
2436 unsigned long flags
;
2439 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2440 entry
= data
->entry
;
2441 spin_lock_irqsave(&ioapic_lock
, flags
);
2442 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ ) {
2443 *(((int *)entry
) + 1) = io_apic_read(dev
->id
, 0x11 + 2 * i
);
2444 *(((int *)entry
) + 0) = io_apic_read(dev
->id
, 0x10 + 2 * i
);
2446 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2451 static int ioapic_resume(struct sys_device
*dev
)
2453 struct IO_APIC_route_entry
*entry
;
2454 struct sysfs_ioapic_data
*data
;
2455 unsigned long flags
;
2456 union IO_APIC_reg_00 reg_00
;
2459 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2460 entry
= data
->entry
;
2462 spin_lock_irqsave(&ioapic_lock
, flags
);
2463 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2464 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2465 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2466 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2468 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ ) {
2469 io_apic_write(dev
->id
, 0x11+2*i
, *(((int *)entry
)+1));
2470 io_apic_write(dev
->id
, 0x10+2*i
, *(((int *)entry
)+0));
2472 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2477 static struct sysdev_class ioapic_sysdev_class
= {
2478 set_kset_name("ioapic"),
2479 .suspend
= ioapic_suspend
,
2480 .resume
= ioapic_resume
,
2483 static int __init
ioapic_init_sysfs(void)
2485 struct sys_device
* dev
;
2486 int i
, size
, error
= 0;
2488 error
= sysdev_class_register(&ioapic_sysdev_class
);
2492 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2493 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2494 * sizeof(struct IO_APIC_route_entry
);
2495 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2496 if (!mp_ioapic_data
[i
]) {
2497 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2500 memset(mp_ioapic_data
[i
], 0, size
);
2501 dev
= &mp_ioapic_data
[i
]->dev
;
2503 dev
->cls
= &ioapic_sysdev_class
;
2504 error
= sysdev_register(dev
);
2506 kfree(mp_ioapic_data
[i
]);
2507 mp_ioapic_data
[i
] = NULL
;
2508 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2516 device_initcall(ioapic_init_sysfs
);
2518 /* --------------------------------------------------------------------------
2519 ACPI-based IOAPIC Configuration
2520 -------------------------------------------------------------------------- */
2524 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2526 union IO_APIC_reg_00 reg_00
;
2527 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2529 unsigned long flags
;
2533 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2534 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2535 * supports up to 16 on one shared APIC bus.
2537 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2538 * advantage of new APIC bus architecture.
2541 if (physids_empty(apic_id_map
))
2542 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2544 spin_lock_irqsave(&ioapic_lock
, flags
);
2545 reg_00
.raw
= io_apic_read(ioapic
, 0);
2546 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2548 if (apic_id
>= get_physical_broadcast()) {
2549 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2550 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2551 apic_id
= reg_00
.bits
.ID
;
2555 * Every APIC in a system must have a unique ID or we get lots of nice
2556 * 'stuck on smp_invalidate_needed IPI wait' messages.
2558 if (check_apicid_used(apic_id_map
, apic_id
)) {
2560 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2561 if (!check_apicid_used(apic_id_map
, i
))
2565 if (i
== get_physical_broadcast())
2566 panic("Max apic_id exceeded!\n");
2568 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2569 "trying %d\n", ioapic
, apic_id
, i
);
2574 tmp
= apicid_to_cpu_present(apic_id
);
2575 physids_or(apic_id_map
, apic_id_map
, tmp
);
2577 if (reg_00
.bits
.ID
!= apic_id
) {
2578 reg_00
.bits
.ID
= apic_id
;
2580 spin_lock_irqsave(&ioapic_lock
, flags
);
2581 io_apic_write(ioapic
, 0, reg_00
.raw
);
2582 reg_00
.raw
= io_apic_read(ioapic
, 0);
2583 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2586 if (reg_00
.bits
.ID
!= apic_id
) {
2587 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2592 apic_printk(APIC_VERBOSE
, KERN_INFO
2593 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2599 int __init
io_apic_get_version (int ioapic
)
2601 union IO_APIC_reg_01 reg_01
;
2602 unsigned long flags
;
2604 spin_lock_irqsave(&ioapic_lock
, flags
);
2605 reg_01
.raw
= io_apic_read(ioapic
, 1);
2606 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2608 return reg_01
.bits
.version
;
2612 int __init
io_apic_get_redir_entries (int ioapic
)
2614 union IO_APIC_reg_01 reg_01
;
2615 unsigned long flags
;
2617 spin_lock_irqsave(&ioapic_lock
, flags
);
2618 reg_01
.raw
= io_apic_read(ioapic
, 1);
2619 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2621 return reg_01
.bits
.entries
;
2625 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2627 struct IO_APIC_route_entry entry
;
2628 unsigned long flags
;
2630 if (!IO_APIC_IRQ(irq
)) {
2631 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2637 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2638 * Note that we mask (disable) IRQs now -- these get enabled when the
2639 * corresponding device driver registers for this IRQ.
2642 memset(&entry
,0,sizeof(entry
));
2644 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2645 entry
.dest_mode
= INT_DEST_MODE
;
2646 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2647 entry
.trigger
= edge_level
;
2648 entry
.polarity
= active_high_low
;
2652 * IRQs < 16 are already in the irq_2_pin[] map
2655 add_pin_to_irq(irq
, ioapic
, pin
);
2657 entry
.vector
= assign_irq_vector(irq
);
2659 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2660 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2661 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2662 edge_level
, active_high_low
);
2664 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2666 if (!ioapic
&& (irq
< 16))
2667 disable_8259A_irq(irq
);
2669 spin_lock_irqsave(&ioapic_lock
, flags
);
2670 io_apic_write(ioapic
, 0x11+2*pin
, *(((int *)&entry
)+1));
2671 io_apic_write(ioapic
, 0x10+2*pin
, *(((int *)&entry
)+0));
2672 set_native_irq_info(use_pci_vector() ? entry
.vector
: irq
, TARGET_CPUS
);
2673 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2678 #endif /* CONFIG_ACPI */