2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/compiler.h>
32 #include <linux/acpi.h>
33 #include <linux/module.h>
34 #include <linux/sysdev.h>
39 #include <asm/timer.h>
40 #include <asm/i8259.h>
42 #include <mach_apic.h>
46 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
47 atomic_t irq_mis_count
;
49 /* Where if anywhere is the i8259 connect in external int mode */
50 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
52 static DEFINE_SPINLOCK(ioapic_lock
);
54 int timer_over_8254 __initdata
= 1;
57 * Is the SiS APIC rmw bug present ?
58 * -1 = don't know, 0 = no, 1 = yes
60 int sis_apic_bug
= -1;
63 * # of IRQ routing registers
65 int nr_ioapic_registers
[MAX_IO_APICS
];
67 int disable_timer_pin_1 __initdata
;
70 * Rough estimation of how many shared IRQs there are, can
73 #define MAX_PLUS_SHARED_IRQS NR_IRQS
74 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
77 * This is performance-critical, we want to do it O(1)
79 * the indexing order of this array favors 1:1 mappings
80 * between pins and IRQs.
83 static struct irq_pin_list
{
85 } irq_2_pin
[PIN_MAP_SIZE
];
87 int vector_irq
[NR_VECTORS
] __read_mostly
= { [0 ... NR_VECTORS
- 1] = -1};
89 #define vector_to_irq(vector) \
90 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
92 #define vector_to_irq(vector) (vector)
96 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
97 * shared ISA-space IRQs, so we have to support them. We are super
98 * fast in the common case, and fast for shared ISA-space IRQs.
100 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
102 static int first_free_entry
= NR_IRQS
;
103 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
106 entry
= irq_2_pin
+ entry
->next
;
108 if (entry
->pin
!= -1) {
109 entry
->next
= first_free_entry
;
110 entry
= irq_2_pin
+ entry
->next
;
111 if (++first_free_entry
>= PIN_MAP_SIZE
)
112 panic("io_apic.c: whoops");
119 * Reroute an IRQ to a different pin.
121 static void __init
replace_pin_at_irq(unsigned int irq
,
122 int oldapic
, int oldpin
,
123 int newapic
, int newpin
)
125 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
128 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
129 entry
->apic
= newapic
;
134 entry
= irq_2_pin
+ entry
->next
;
138 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
140 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
141 unsigned int pin
, reg
;
147 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
150 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
153 entry
= irq_2_pin
+ entry
->next
;
158 static void __mask_IO_APIC_irq (unsigned int irq
)
160 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
164 static void __unmask_IO_APIC_irq (unsigned int irq
)
166 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
169 /* mask = 1, trigger = 0 */
170 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
172 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
175 /* mask = 0, trigger = 1 */
176 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
178 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
181 static void mask_IO_APIC_irq (unsigned int irq
)
185 spin_lock_irqsave(&ioapic_lock
, flags
);
186 __mask_IO_APIC_irq(irq
);
187 spin_unlock_irqrestore(&ioapic_lock
, flags
);
190 static void unmask_IO_APIC_irq (unsigned int irq
)
194 spin_lock_irqsave(&ioapic_lock
, flags
);
195 __unmask_IO_APIC_irq(irq
);
196 spin_unlock_irqrestore(&ioapic_lock
, flags
);
199 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
201 struct IO_APIC_route_entry entry
;
204 /* Check delivery_mode to be sure we're not clearing an SMI pin */
205 spin_lock_irqsave(&ioapic_lock
, flags
);
206 *(((int*)&entry
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
207 *(((int*)&entry
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
208 spin_unlock_irqrestore(&ioapic_lock
, flags
);
209 if (entry
.delivery_mode
== dest_SMI
)
213 * Disable it in the IO-APIC irq-routing table:
215 memset(&entry
, 0, sizeof(entry
));
217 spin_lock_irqsave(&ioapic_lock
, flags
);
218 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry
) + 0));
219 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry
) + 1));
220 spin_unlock_irqrestore(&ioapic_lock
, flags
);
223 static void clear_IO_APIC (void)
227 for (apic
= 0; apic
< nr_ioapics
; apic
++)
228 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
229 clear_IO_APIC_pin(apic
, pin
);
233 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
237 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
238 unsigned int apicid_value
;
241 cpus_and(tmp
, cpumask
, cpu_online_map
);
245 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
247 apicid_value
= cpu_mask_to_apicid(cpumask
);
248 /* Prepare to do the io_apic_write */
249 apicid_value
= apicid_value
<< 24;
250 spin_lock_irqsave(&ioapic_lock
, flags
);
255 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
258 entry
= irq_2_pin
+ entry
->next
;
260 set_irq_info(irq
, cpumask
);
261 spin_unlock_irqrestore(&ioapic_lock
, flags
);
264 #if defined(CONFIG_IRQBALANCE)
265 # include <asm/processor.h> /* kernel_thread() */
266 # include <linux/kernel_stat.h> /* kstat */
267 # include <linux/slab.h> /* kmalloc() */
268 # include <linux/timer.h> /* time_after() */
270 # ifdef CONFIG_BALANCED_IRQ_DEBUG
271 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
272 # define Dprintk(x...) do { TDprintk(x); } while (0)
274 # define TDprintk(x...)
275 # define Dprintk(x...)
279 #define IRQBALANCE_CHECK_ARCH -999
280 static int irqbalance_disabled
= IRQBALANCE_CHECK_ARCH
;
281 static int physical_balance
= 0;
283 static struct irq_cpu_info
{
284 unsigned long * last_irq
;
285 unsigned long * irq_delta
;
287 } irq_cpu_data
[NR_CPUS
];
289 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
290 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
291 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
293 #define IDLE_ENOUGH(cpu,now) \
294 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
296 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
298 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
300 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
301 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
302 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
303 #define BALANCED_IRQ_LESS_DELTA (HZ)
305 static long balanced_irq_interval
= MAX_BALANCED_IRQ_INTERVAL
;
307 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
308 unsigned long now
, int direction
)
316 if (unlikely(cpu
== curr_cpu
))
319 if (direction
== 1) {
328 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
329 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
334 static inline void balance_irq(int cpu
, int irq
)
336 unsigned long now
= jiffies
;
337 cpumask_t allowed_mask
;
338 unsigned int new_cpu
;
340 if (irqbalance_disabled
)
343 cpus_and(allowed_mask
, cpu_online_map
, irq_affinity
[irq
]);
344 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
345 if (cpu
!= new_cpu
) {
346 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
350 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
353 Dprintk("Rotating IRQs among CPUs.\n");
354 for_each_online_cpu(i
) {
355 for (j
= 0; j
< NR_IRQS
; j
++) {
356 if (!irq_desc
[j
].action
)
358 /* Is it a significant load ? */
359 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
360 useful_load_threshold
)
365 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
366 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
370 static void do_irq_balance(void)
373 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
374 unsigned long move_this_load
= 0;
375 int max_loaded
= 0, min_loaded
= 0;
377 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
379 int tmp_loaded
, first_attempt
= 1;
380 unsigned long tmp_cpu_irq
;
381 unsigned long imbalance
= 0;
382 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
384 for_each_possible_cpu(i
) {
389 package_index
= CPU_TO_PACKAGEINDEX(i
);
390 for (j
= 0; j
< NR_IRQS
; j
++) {
391 unsigned long value_now
, delta
;
392 /* Is this an active IRQ? */
393 if (!irq_desc
[j
].action
)
395 if ( package_index
== i
)
396 IRQ_DELTA(package_index
,j
) = 0;
397 /* Determine the total count per processor per IRQ */
398 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
400 /* Determine the activity per processor per IRQ */
401 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
403 /* Update last_cpu_irq[][] for the next time */
404 LAST_CPU_IRQ(i
,j
) = value_now
;
406 /* Ignore IRQs whose rate is less than the clock */
407 if (delta
< useful_load_threshold
)
409 /* update the load for the processor or package total */
410 IRQ_DELTA(package_index
,j
) += delta
;
412 /* Keep track of the higher numbered sibling as well */
413 if (i
!= package_index
)
416 * We have sibling A and sibling B in the package
418 * cpu_irq[A] = load for cpu A + load for cpu B
419 * cpu_irq[B] = load for cpu B
421 CPU_IRQ(package_index
) += delta
;
424 /* Find the least loaded processor package */
425 for_each_online_cpu(i
) {
426 if (i
!= CPU_TO_PACKAGEINDEX(i
))
428 if (min_cpu_irq
> CPU_IRQ(i
)) {
429 min_cpu_irq
= CPU_IRQ(i
);
433 max_cpu_irq
= ULONG_MAX
;
436 /* Look for heaviest loaded processor.
437 * We may come back to get the next heaviest loaded processor.
438 * Skip processors with trivial loads.
442 for_each_online_cpu(i
) {
443 if (i
!= CPU_TO_PACKAGEINDEX(i
))
445 if (max_cpu_irq
<= CPU_IRQ(i
))
447 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
448 tmp_cpu_irq
= CPU_IRQ(i
);
453 if (tmp_loaded
== -1) {
454 /* In the case of small number of heavy interrupt sources,
455 * loading some of the cpus too much. We use Ingo's original
456 * approach to rotate them around.
458 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
459 rotate_irqs_among_cpus(useful_load_threshold
);
462 goto not_worth_the_effort
;
465 first_attempt
= 0; /* heaviest search */
466 max_cpu_irq
= tmp_cpu_irq
; /* load */
467 max_loaded
= tmp_loaded
; /* processor */
468 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
470 Dprintk("max_loaded cpu = %d\n", max_loaded
);
471 Dprintk("min_loaded cpu = %d\n", min_loaded
);
472 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq
);
473 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq
);
474 Dprintk("load imbalance = %lu\n", imbalance
);
476 /* if imbalance is less than approx 10% of max load, then
477 * observe diminishing returns action. - quit
479 if (imbalance
< (max_cpu_irq
>> 3)) {
480 Dprintk("Imbalance too trivial\n");
481 goto not_worth_the_effort
;
485 /* if we select an IRQ to move that can't go where we want, then
486 * see if there is another one to try.
490 for (j
= 0; j
< NR_IRQS
; j
++) {
491 /* Is this an active IRQ? */
492 if (!irq_desc
[j
].action
)
494 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
496 /* Try to find the IRQ that is closest to the imbalance
497 * without going over.
499 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
500 move_this_load
= IRQ_DELTA(max_loaded
,j
);
504 if (selected_irq
== -1) {
508 imbalance
= move_this_load
;
510 /* For physical_balance case, we accumlated both load
511 * values in the one of the siblings cpu_irq[],
512 * to use the same code for physical and logical processors
513 * as much as possible.
515 * NOTE: the cpu_irq[] array holds the sum of the load for
516 * sibling A and sibling B in the slot for the lowest numbered
517 * sibling (A), _AND_ the load for sibling B in the slot for
518 * the higher numbered sibling.
520 * We seek the least loaded sibling by making the comparison
523 load
= CPU_IRQ(min_loaded
) >> 1;
524 for_each_cpu_mask(j
, cpu_sibling_map
[min_loaded
]) {
525 if (load
> CPU_IRQ(j
)) {
526 /* This won't change cpu_sibling_map[min_loaded] */
532 cpus_and(allowed_mask
, cpu_online_map
, irq_affinity
[selected_irq
]);
533 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
534 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
536 if (!cpus_empty(tmp
)) {
538 Dprintk("irq = %d moved to cpu = %d\n",
539 selected_irq
, min_loaded
);
540 /* mark for change destination */
541 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
543 /* Since we made a change, come back sooner to
544 * check for more variation.
546 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
547 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
552 not_worth_the_effort
:
554 * if we did not find an IRQ to move, then adjust the time interval
557 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
558 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
559 Dprintk("IRQ worth rotating not found\n");
563 static int balanced_irq(void *unused
)
566 unsigned long prev_balance_time
= jiffies
;
567 long time_remaining
= balanced_irq_interval
;
571 /* push everything to CPU 0 to give us a starting point. */
572 for (i
= 0 ; i
< NR_IRQS
; i
++) {
573 pending_irq_cpumask
[i
] = cpumask_of_cpu(0);
574 set_pending_irq(i
, cpumask_of_cpu(0));
578 time_remaining
= schedule_timeout_interruptible(time_remaining
);
580 if (time_after(jiffies
,
581 prev_balance_time
+balanced_irq_interval
)) {
584 prev_balance_time
= jiffies
;
585 time_remaining
= balanced_irq_interval
;
592 static int __init
balanced_irq_init(void)
595 struct cpuinfo_x86
*c
;
598 cpus_shift_right(tmp
, cpu_online_map
, 2);
600 /* When not overwritten by the command line ask subarchitecture. */
601 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
602 irqbalance_disabled
= NO_BALANCE_IRQ
;
603 if (irqbalance_disabled
)
606 /* disable irqbalance completely if there is only one processor online */
607 if (num_online_cpus() < 2) {
608 irqbalance_disabled
= 1;
612 * Enable physical balance only if more than 1 physical processor
615 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
616 physical_balance
= 1;
618 for_each_online_cpu(i
) {
619 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
620 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
621 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
622 printk(KERN_ERR
"balanced_irq_init: out of memory");
625 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
626 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
629 printk(KERN_INFO
"Starting balanced_irq\n");
630 if (kernel_thread(balanced_irq
, NULL
, CLONE_KERNEL
) >= 0)
633 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
635 for_each_possible_cpu(i
) {
636 kfree(irq_cpu_data
[i
].irq_delta
);
637 irq_cpu_data
[i
].irq_delta
= NULL
;
638 kfree(irq_cpu_data
[i
].last_irq
);
639 irq_cpu_data
[i
].last_irq
= NULL
;
644 int __init
irqbalance_disable(char *str
)
646 irqbalance_disabled
= 1;
650 __setup("noirqbalance", irqbalance_disable
);
652 late_initcall(balanced_irq_init
);
653 #endif /* CONFIG_IRQBALANCE */
654 #endif /* CONFIG_SMP */
657 void fastcall
send_IPI_self(int vector
)
664 apic_wait_icr_idle();
665 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
667 * Send the IPI. The write to APIC_ICR fires this off.
669 apic_write_around(APIC_ICR
, cfg
);
671 #endif /* !CONFIG_SMP */
675 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
676 * specific CPU-side IRQs.
680 static int pirq_entries
[MAX_PIRQS
];
681 static int pirqs_enabled
;
682 int skip_ioapic_setup
;
684 static int __init
ioapic_setup(char *str
)
686 skip_ioapic_setup
= 1;
690 __setup("noapic", ioapic_setup
);
692 static int __init
ioapic_pirq_setup(char *str
)
695 int ints
[MAX_PIRQS
+1];
697 get_options(str
, ARRAY_SIZE(ints
), ints
);
699 for (i
= 0; i
< MAX_PIRQS
; i
++)
700 pirq_entries
[i
] = -1;
703 apic_printk(APIC_VERBOSE
, KERN_INFO
704 "PIRQ redirection, working around broken MP-BIOS.\n");
706 if (ints
[0] < MAX_PIRQS
)
709 for (i
= 0; i
< max
; i
++) {
710 apic_printk(APIC_VERBOSE
, KERN_DEBUG
711 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
713 * PIRQs are mapped upside down, usually.
715 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
720 __setup("pirq=", ioapic_pirq_setup
);
723 * Find the IRQ entry number of a certain pin.
725 static int find_irq_entry(int apic
, int pin
, int type
)
729 for (i
= 0; i
< mp_irq_entries
; i
++)
730 if (mp_irqs
[i
].mpc_irqtype
== type
&&
731 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
732 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
733 mp_irqs
[i
].mpc_dstirq
== pin
)
740 * Find the pin to which IRQ[irq] (ISA) is connected
742 static int __init
find_isa_irq_pin(int irq
, int type
)
746 for (i
= 0; i
< mp_irq_entries
; i
++) {
747 int lbus
= mp_irqs
[i
].mpc_srcbus
;
749 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
750 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
751 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
752 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
754 (mp_irqs
[i
].mpc_irqtype
== type
) &&
755 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
757 return mp_irqs
[i
].mpc_dstirq
;
762 static int __init
find_isa_irq_apic(int irq
, int type
)
766 for (i
= 0; i
< mp_irq_entries
; i
++) {
767 int lbus
= mp_irqs
[i
].mpc_srcbus
;
769 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
770 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
771 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
772 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
774 (mp_irqs
[i
].mpc_irqtype
== type
) &&
775 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
778 if (i
< mp_irq_entries
) {
780 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
781 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
790 * Find a specific PCI IRQ entry.
791 * Not an __init, possibly needed by modules
793 static int pin_2_irq(int idx
, int apic
, int pin
);
795 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
797 int apic
, i
, best_guess
= -1;
799 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
800 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
801 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
802 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
805 for (i
= 0; i
< mp_irq_entries
; i
++) {
806 int lbus
= mp_irqs
[i
].mpc_srcbus
;
808 for (apic
= 0; apic
< nr_ioapics
; apic
++)
809 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
810 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
813 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
814 !mp_irqs
[i
].mpc_irqtype
&&
816 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
817 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
819 if (!(apic
|| IO_APIC_IRQ(irq
)))
822 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
825 * Use the first all-but-pin matching entry as a
826 * best-guess fuzzy result for broken mptables.
834 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
837 * This function currently is only a helper for the i386 smp boot process where
838 * we need to reprogram the ioredtbls to cater for the cpus which have come online
839 * so mask in all cases should simply be TARGET_CPUS
842 void __init
setup_ioapic_dest(void)
844 int pin
, ioapic
, irq
, irq_entry
;
846 if (skip_ioapic_setup
== 1)
849 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
850 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
851 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
854 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
855 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
863 * EISA Edge/Level control register, ELCR
865 static int EISA_ELCR(unsigned int irq
)
868 unsigned int port
= 0x4d0 + (irq
>> 3);
869 return (inb(port
) >> (irq
& 7)) & 1;
871 apic_printk(APIC_VERBOSE
, KERN_INFO
872 "Broken MPtable reports ISA irq %d\n", irq
);
876 /* EISA interrupts are always polarity zero and can be edge or level
877 * trigger depending on the ELCR value. If an interrupt is listed as
878 * EISA conforming in the MP table, that means its trigger type must
879 * be read in from the ELCR */
881 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
882 #define default_EISA_polarity(idx) (0)
884 /* ISA interrupts are always polarity zero edge triggered,
885 * when listed as conforming in the MP table. */
887 #define default_ISA_trigger(idx) (0)
888 #define default_ISA_polarity(idx) (0)
890 /* PCI interrupts are always polarity one level triggered,
891 * when listed as conforming in the MP table. */
893 #define default_PCI_trigger(idx) (1)
894 #define default_PCI_polarity(idx) (1)
896 /* MCA interrupts are always polarity zero level triggered,
897 * when listed as conforming in the MP table. */
899 #define default_MCA_trigger(idx) (1)
900 #define default_MCA_polarity(idx) (0)
902 /* NEC98 interrupts are always polarity zero edge triggered,
903 * when listed as conforming in the MP table. */
905 #define default_NEC98_trigger(idx) (0)
906 #define default_NEC98_polarity(idx) (0)
908 static int __init
MPBIOS_polarity(int idx
)
910 int bus
= mp_irqs
[idx
].mpc_srcbus
;
914 * Determine IRQ line polarity (high active or low active):
916 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
918 case 0: /* conforms, ie. bus-type dependent polarity */
920 switch (mp_bus_id_to_type
[bus
])
922 case MP_BUS_ISA
: /* ISA pin */
924 polarity
= default_ISA_polarity(idx
);
927 case MP_BUS_EISA
: /* EISA pin */
929 polarity
= default_EISA_polarity(idx
);
932 case MP_BUS_PCI
: /* PCI pin */
934 polarity
= default_PCI_polarity(idx
);
937 case MP_BUS_MCA
: /* MCA pin */
939 polarity
= default_MCA_polarity(idx
);
942 case MP_BUS_NEC98
: /* NEC 98 pin */
944 polarity
= default_NEC98_polarity(idx
);
949 printk(KERN_WARNING
"broken BIOS!!\n");
956 case 1: /* high active */
961 case 2: /* reserved */
963 printk(KERN_WARNING
"broken BIOS!!\n");
967 case 3: /* low active */
972 default: /* invalid */
974 printk(KERN_WARNING
"broken BIOS!!\n");
982 static int MPBIOS_trigger(int idx
)
984 int bus
= mp_irqs
[idx
].mpc_srcbus
;
988 * Determine IRQ trigger mode (edge or level sensitive):
990 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
992 case 0: /* conforms, ie. bus-type dependent */
994 switch (mp_bus_id_to_type
[bus
])
996 case MP_BUS_ISA
: /* ISA pin */
998 trigger
= default_ISA_trigger(idx
);
1001 case MP_BUS_EISA
: /* EISA pin */
1003 trigger
= default_EISA_trigger(idx
);
1006 case MP_BUS_PCI
: /* PCI pin */
1008 trigger
= default_PCI_trigger(idx
);
1011 case MP_BUS_MCA
: /* MCA pin */
1013 trigger
= default_MCA_trigger(idx
);
1016 case MP_BUS_NEC98
: /* NEC 98 pin */
1018 trigger
= default_NEC98_trigger(idx
);
1023 printk(KERN_WARNING
"broken BIOS!!\n");
1035 case 2: /* reserved */
1037 printk(KERN_WARNING
"broken BIOS!!\n");
1046 default: /* invalid */
1048 printk(KERN_WARNING
"broken BIOS!!\n");
1056 static inline int irq_polarity(int idx
)
1058 return MPBIOS_polarity(idx
);
1061 static inline int irq_trigger(int idx
)
1063 return MPBIOS_trigger(idx
);
1066 static int pin_2_irq(int idx
, int apic
, int pin
)
1069 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1072 * Debugging check, we are in big trouble if this message pops up!
1074 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1075 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1077 switch (mp_bus_id_to_type
[bus
])
1079 case MP_BUS_ISA
: /* ISA pin */
1084 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1087 case MP_BUS_PCI
: /* PCI pin */
1090 * PCI IRQs are mapped in order
1094 irq
+= nr_ioapic_registers
[i
++];
1098 * For MPS mode, so far only needed by ES7000 platform
1100 if (ioapic_renumber_irq
)
1101 irq
= ioapic_renumber_irq(apic
, irq
);
1107 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
1114 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1116 if ((pin
>= 16) && (pin
<= 23)) {
1117 if (pirq_entries
[pin
-16] != -1) {
1118 if (!pirq_entries
[pin
-16]) {
1119 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1120 "disabling PIRQ%d\n", pin
-16);
1122 irq
= pirq_entries
[pin
-16];
1123 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1124 "using PIRQ%d -> IRQ %d\n",
1132 static inline int IO_APIC_irq_trigger(int irq
)
1136 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1137 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1138 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1139 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1140 return irq_trigger(idx
);
1144 * nonexistent IRQs are edge default
1149 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1150 u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1152 int assign_irq_vector(int irq
)
1154 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
1156 BUG_ON(irq
>= NR_IRQ_VECTORS
);
1157 if (irq
!= AUTO_ASSIGN
&& IO_APIC_VECTOR(irq
) > 0)
1158 return IO_APIC_VECTOR(irq
);
1160 current_vector
+= 8;
1161 if (current_vector
== SYSCALL_VECTOR
)
1164 if (current_vector
>= FIRST_SYSTEM_VECTOR
) {
1168 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
1171 vector_irq
[current_vector
] = irq
;
1172 if (irq
!= AUTO_ASSIGN
)
1173 IO_APIC_VECTOR(irq
) = current_vector
;
1175 return current_vector
;
1178 static struct hw_interrupt_type ioapic_level_type
;
1179 static struct hw_interrupt_type ioapic_edge_type
;
1181 #define IOAPIC_AUTO -1
1182 #define IOAPIC_EDGE 0
1183 #define IOAPIC_LEVEL 1
1185 static inline void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1187 if (use_pci_vector() && !platform_legacy_irq(irq
)) {
1188 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1189 trigger
== IOAPIC_LEVEL
)
1190 irq_desc
[vector
].handler
= &ioapic_level_type
;
1192 irq_desc
[vector
].handler
= &ioapic_edge_type
;
1193 set_intr_gate(vector
, interrupt
[vector
]);
1195 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1196 trigger
== IOAPIC_LEVEL
)
1197 irq_desc
[irq
].handler
= &ioapic_level_type
;
1199 irq_desc
[irq
].handler
= &ioapic_edge_type
;
1200 set_intr_gate(vector
, interrupt
[irq
]);
1204 static void __init
setup_IO_APIC_irqs(void)
1206 struct IO_APIC_route_entry entry
;
1207 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1208 unsigned long flags
;
1210 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1212 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1213 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1216 * add it to the IO-APIC irq-routing table:
1218 memset(&entry
,0,sizeof(entry
));
1220 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1221 entry
.dest_mode
= INT_DEST_MODE
;
1222 entry
.mask
= 0; /* enable IRQ */
1223 entry
.dest
.logical
.logical_dest
=
1224 cpu_mask_to_apicid(TARGET_CPUS
);
1226 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1229 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1230 " IO-APIC (apicid-pin) %d-%d",
1231 mp_ioapics
[apic
].mpc_apicid
,
1235 apic_printk(APIC_VERBOSE
, ", %d-%d",
1236 mp_ioapics
[apic
].mpc_apicid
, pin
);
1240 entry
.trigger
= irq_trigger(idx
);
1241 entry
.polarity
= irq_polarity(idx
);
1243 if (irq_trigger(idx
)) {
1248 irq
= pin_2_irq(idx
, apic
, pin
);
1250 * skip adding the timer int on secondary nodes, which causes
1251 * a small but painful rift in the time-space continuum
1253 if (multi_timer_check(apic
, irq
))
1256 add_pin_to_irq(irq
, apic
, pin
);
1258 if (!apic
&& !IO_APIC_IRQ(irq
))
1261 if (IO_APIC_IRQ(irq
)) {
1262 vector
= assign_irq_vector(irq
);
1263 entry
.vector
= vector
;
1264 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1266 if (!apic
&& (irq
< 16))
1267 disable_8259A_irq(irq
);
1269 spin_lock_irqsave(&ioapic_lock
, flags
);
1270 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
1271 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
1272 set_native_irq_info(irq
, TARGET_CPUS
);
1273 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1278 apic_printk(APIC_VERBOSE
, " not connected.\n");
1282 * Set up the 8259A-master output pin:
1284 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
1286 struct IO_APIC_route_entry entry
;
1287 unsigned long flags
;
1289 memset(&entry
,0,sizeof(entry
));
1291 disable_8259A_irq(0);
1294 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1297 * We use logical delivery to get the timer IRQ
1300 entry
.dest_mode
= INT_DEST_MODE
;
1301 entry
.mask
= 0; /* unmask IRQ now */
1302 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1303 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1306 entry
.vector
= vector
;
1309 * The timer IRQ doesn't have to know that behind the
1310 * scene we have a 8259A-master in AEOI mode ...
1312 irq_desc
[0].handler
= &ioapic_edge_type
;
1315 * Add it to the IO-APIC irq-routing table:
1317 spin_lock_irqsave(&ioapic_lock
, flags
);
1318 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
1319 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
1320 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1322 enable_8259A_irq(0);
1325 static inline void UNEXPECTED_IO_APIC(void)
1329 void __init
print_IO_APIC(void)
1332 union IO_APIC_reg_00 reg_00
;
1333 union IO_APIC_reg_01 reg_01
;
1334 union IO_APIC_reg_02 reg_02
;
1335 union IO_APIC_reg_03 reg_03
;
1336 unsigned long flags
;
1338 if (apic_verbosity
== APIC_QUIET
)
1341 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1342 for (i
= 0; i
< nr_ioapics
; i
++)
1343 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1344 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1347 * We are a bit conservative about what we expect. We have to
1348 * know about every hardware change ASAP.
1350 printk(KERN_INFO
"testing the IO APIC.......................\n");
1352 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1354 spin_lock_irqsave(&ioapic_lock
, flags
);
1355 reg_00
.raw
= io_apic_read(apic
, 0);
1356 reg_01
.raw
= io_apic_read(apic
, 1);
1357 if (reg_01
.bits
.version
>= 0x10)
1358 reg_02
.raw
= io_apic_read(apic
, 2);
1359 if (reg_01
.bits
.version
>= 0x20)
1360 reg_03
.raw
= io_apic_read(apic
, 3);
1361 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1363 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1364 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1365 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1366 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1367 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1368 if (reg_00
.bits
.ID
>= get_physical_broadcast())
1369 UNEXPECTED_IO_APIC();
1370 if (reg_00
.bits
.__reserved_1
|| reg_00
.bits
.__reserved_2
)
1371 UNEXPECTED_IO_APIC();
1373 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1374 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1375 if ( (reg_01
.bits
.entries
!= 0x0f) && /* older (Neptune) boards */
1376 (reg_01
.bits
.entries
!= 0x17) && /* typical ISA+PCI boards */
1377 (reg_01
.bits
.entries
!= 0x1b) && /* Compaq Proliant boards */
1378 (reg_01
.bits
.entries
!= 0x1f) && /* dual Xeon boards */
1379 (reg_01
.bits
.entries
!= 0x22) && /* bigger Xeon boards */
1380 (reg_01
.bits
.entries
!= 0x2E) &&
1381 (reg_01
.bits
.entries
!= 0x3F)
1383 UNEXPECTED_IO_APIC();
1385 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1386 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1387 if ( (reg_01
.bits
.version
!= 0x01) && /* 82489DX IO-APICs */
1388 (reg_01
.bits
.version
!= 0x10) && /* oldest IO-APICs */
1389 (reg_01
.bits
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
1390 (reg_01
.bits
.version
!= 0x13) && /* Xeon IO-APICs */
1391 (reg_01
.bits
.version
!= 0x20) /* Intel P64H (82806 AA) */
1393 UNEXPECTED_IO_APIC();
1394 if (reg_01
.bits
.__reserved_1
|| reg_01
.bits
.__reserved_2
)
1395 UNEXPECTED_IO_APIC();
1398 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1399 * but the value of reg_02 is read as the previous read register
1400 * value, so ignore it if reg_02 == reg_01.
1402 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1403 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1404 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1405 if (reg_02
.bits
.__reserved_1
|| reg_02
.bits
.__reserved_2
)
1406 UNEXPECTED_IO_APIC();
1410 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1411 * or reg_03, but the value of reg_0[23] is read as the previous read
1412 * register value, so ignore it if reg_03 == reg_0[12].
1414 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1415 reg_03
.raw
!= reg_01
.raw
) {
1416 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1417 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1418 if (reg_03
.bits
.__reserved_1
)
1419 UNEXPECTED_IO_APIC();
1422 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1424 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1425 " Stat Dest Deli Vect: \n");
1427 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1428 struct IO_APIC_route_entry entry
;
1430 spin_lock_irqsave(&ioapic_lock
, flags
);
1431 *(((int *)&entry
)+0) = io_apic_read(apic
, 0x10+i
*2);
1432 *(((int *)&entry
)+1) = io_apic_read(apic
, 0x11+i
*2);
1433 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1435 printk(KERN_DEBUG
" %02x %03X %02X ",
1437 entry
.dest
.logical
.logical_dest
,
1438 entry
.dest
.physical
.physical_dest
1441 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1446 entry
.delivery_status
,
1448 entry
.delivery_mode
,
1453 if (use_pci_vector())
1454 printk(KERN_INFO
"Using vector-based indexing\n");
1455 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1456 for (i
= 0; i
< NR_IRQS
; i
++) {
1457 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1460 if (use_pci_vector() && !platform_legacy_irq(i
))
1461 printk(KERN_DEBUG
"IRQ%d ", IO_APIC_VECTOR(i
));
1463 printk(KERN_DEBUG
"IRQ%d ", i
);
1465 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1468 entry
= irq_2_pin
+ entry
->next
;
1473 printk(KERN_INFO
".................................... done.\n");
1480 static void print_APIC_bitfield (int base
)
1485 if (apic_verbosity
== APIC_QUIET
)
1488 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1489 for (i
= 0; i
< 8; i
++) {
1490 v
= apic_read(base
+ i
*0x10);
1491 for (j
= 0; j
< 32; j
++) {
1501 void /*__init*/ print_local_APIC(void * dummy
)
1503 unsigned int v
, ver
, maxlvt
;
1505 if (apic_verbosity
== APIC_QUIET
)
1508 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1509 smp_processor_id(), hard_smp_processor_id());
1510 v
= apic_read(APIC_ID
);
1511 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1512 v
= apic_read(APIC_LVR
);
1513 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1514 ver
= GET_APIC_VERSION(v
);
1515 maxlvt
= get_maxlvt();
1517 v
= apic_read(APIC_TASKPRI
);
1518 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1520 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1521 v
= apic_read(APIC_ARBPRI
);
1522 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1523 v
& APIC_ARBPRI_MASK
);
1524 v
= apic_read(APIC_PROCPRI
);
1525 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1528 v
= apic_read(APIC_EOI
);
1529 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1530 v
= apic_read(APIC_RRR
);
1531 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1532 v
= apic_read(APIC_LDR
);
1533 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1534 v
= apic_read(APIC_DFR
);
1535 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1536 v
= apic_read(APIC_SPIV
);
1537 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1539 printk(KERN_DEBUG
"... APIC ISR field:\n");
1540 print_APIC_bitfield(APIC_ISR
);
1541 printk(KERN_DEBUG
"... APIC TMR field:\n");
1542 print_APIC_bitfield(APIC_TMR
);
1543 printk(KERN_DEBUG
"... APIC IRR field:\n");
1544 print_APIC_bitfield(APIC_IRR
);
1546 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1547 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1548 apic_write(APIC_ESR
, 0);
1549 v
= apic_read(APIC_ESR
);
1550 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1553 v
= apic_read(APIC_ICR
);
1554 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1555 v
= apic_read(APIC_ICR2
);
1556 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1558 v
= apic_read(APIC_LVTT
);
1559 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1561 if (maxlvt
> 3) { /* PC is LVT#4. */
1562 v
= apic_read(APIC_LVTPC
);
1563 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1565 v
= apic_read(APIC_LVT0
);
1566 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1567 v
= apic_read(APIC_LVT1
);
1568 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1570 if (maxlvt
> 2) { /* ERR is LVT#3. */
1571 v
= apic_read(APIC_LVTERR
);
1572 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1575 v
= apic_read(APIC_TMICT
);
1576 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1577 v
= apic_read(APIC_TMCCT
);
1578 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1579 v
= apic_read(APIC_TDCR
);
1580 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1584 void print_all_local_APICs (void)
1586 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1589 void /*__init*/ print_PIC(void)
1592 unsigned long flags
;
1594 if (apic_verbosity
== APIC_QUIET
)
1597 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1599 spin_lock_irqsave(&i8259A_lock
, flags
);
1601 v
= inb(0xa1) << 8 | inb(0x21);
1602 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1604 v
= inb(0xa0) << 8 | inb(0x20);
1605 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1609 v
= inb(0xa0) << 8 | inb(0x20);
1613 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1615 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1617 v
= inb(0x4d1) << 8 | inb(0x4d0);
1618 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1623 static void __init
enable_IO_APIC(void)
1625 union IO_APIC_reg_01 reg_01
;
1626 int i8259_apic
, i8259_pin
;
1628 unsigned long flags
;
1630 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1631 irq_2_pin
[i
].pin
= -1;
1632 irq_2_pin
[i
].next
= 0;
1635 for (i
= 0; i
< MAX_PIRQS
; i
++)
1636 pirq_entries
[i
] = -1;
1639 * The number of IO-APIC IRQ registers (== #pins):
1641 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1642 spin_lock_irqsave(&ioapic_lock
, flags
);
1643 reg_01
.raw
= io_apic_read(apic
, 1);
1644 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1645 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1647 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1649 /* See if any of the pins is in ExtINT mode */
1650 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1651 struct IO_APIC_route_entry entry
;
1652 spin_lock_irqsave(&ioapic_lock
, flags
);
1653 *(((int *)&entry
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
1654 *(((int *)&entry
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
1655 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1658 /* If the interrupt line is enabled and in ExtInt mode
1659 * I have found the pin where the i8259 is connected.
1661 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1662 ioapic_i8259
.apic
= apic
;
1663 ioapic_i8259
.pin
= pin
;
1669 /* Look to see what if the MP table has reported the ExtINT */
1670 /* If we could not find the appropriate pin by looking at the ioapic
1671 * the i8259 probably is not connected the ioapic but give the
1672 * mptable a chance anyway.
1674 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1675 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1676 /* Trust the MP table if nothing is setup in the hardware */
1677 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1678 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1679 ioapic_i8259
.pin
= i8259_pin
;
1680 ioapic_i8259
.apic
= i8259_apic
;
1682 /* Complain if the MP table and the hardware disagree */
1683 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1684 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1686 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1690 * Do not trust the IO-APIC being empty at bootup
1696 * Not an __init, needed by the reboot code
1698 void disable_IO_APIC(void)
1701 * Clear the IO-APIC before rebooting:
1706 * If the i8259 is routed through an IOAPIC
1707 * Put that IOAPIC in virtual wire mode
1708 * so legacy interrupts can be delivered.
1710 if (ioapic_i8259
.pin
!= -1) {
1711 struct IO_APIC_route_entry entry
;
1712 unsigned long flags
;
1714 memset(&entry
, 0, sizeof(entry
));
1715 entry
.mask
= 0; /* Enabled */
1716 entry
.trigger
= 0; /* Edge */
1718 entry
.polarity
= 0; /* High */
1719 entry
.delivery_status
= 0;
1720 entry
.dest_mode
= 0; /* Physical */
1721 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1723 entry
.dest
.physical
.physical_dest
=
1724 GET_APIC_ID(apic_read(APIC_ID
));
1727 * Add it to the IO-APIC irq-routing table:
1729 spin_lock_irqsave(&ioapic_lock
, flags
);
1730 io_apic_write(ioapic_i8259
.apic
, 0x11+2*ioapic_i8259
.pin
,
1731 *(((int *)&entry
)+1));
1732 io_apic_write(ioapic_i8259
.apic
, 0x10+2*ioapic_i8259
.pin
,
1733 *(((int *)&entry
)+0));
1734 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1736 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1740 * function to set the IO-APIC physical IDs based on the
1741 * values stored in the MPC table.
1743 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1746 #ifndef CONFIG_X86_NUMAQ
1747 static void __init
setup_ioapic_ids_from_mpc(void)
1749 union IO_APIC_reg_00 reg_00
;
1750 physid_mask_t phys_id_present_map
;
1753 unsigned char old_id
;
1754 unsigned long flags
;
1757 * Don't check I/O APIC IDs for xAPIC systems. They have
1758 * no meaning without the serial APIC bus.
1760 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1761 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1764 * This is broken; anything with a real cpu count has to
1765 * circumvent this idiocy regardless.
1767 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1770 * Set the IOAPIC ID to the value stored in the MPC table.
1772 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1774 /* Read the register 0 value */
1775 spin_lock_irqsave(&ioapic_lock
, flags
);
1776 reg_00
.raw
= io_apic_read(apic
, 0);
1777 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1779 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1781 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1782 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1783 apic
, mp_ioapics
[apic
].mpc_apicid
);
1784 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1786 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1790 * Sanity check, is the ID really free? Every APIC in a
1791 * system must have a unique ID or we get lots of nice
1792 * 'stuck on smp_invalidate_needed IPI wait' messages.
1794 if (check_apicid_used(phys_id_present_map
,
1795 mp_ioapics
[apic
].mpc_apicid
)) {
1796 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1797 apic
, mp_ioapics
[apic
].mpc_apicid
);
1798 for (i
= 0; i
< get_physical_broadcast(); i
++)
1799 if (!physid_isset(i
, phys_id_present_map
))
1801 if (i
>= get_physical_broadcast())
1802 panic("Max APIC ID exceeded!\n");
1803 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1805 physid_set(i
, phys_id_present_map
);
1806 mp_ioapics
[apic
].mpc_apicid
= i
;
1809 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1810 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1811 "phys_id_present_map\n",
1812 mp_ioapics
[apic
].mpc_apicid
);
1813 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1818 * We need to adjust the IRQ routing table
1819 * if the ID changed.
1821 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1822 for (i
= 0; i
< mp_irq_entries
; i
++)
1823 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1824 mp_irqs
[i
].mpc_dstapic
1825 = mp_ioapics
[apic
].mpc_apicid
;
1828 * Read the right value from the MPC table and
1829 * write it into the ID register.
1831 apic_printk(APIC_VERBOSE
, KERN_INFO
1832 "...changing IO-APIC physical APIC ID to %d ...",
1833 mp_ioapics
[apic
].mpc_apicid
);
1835 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1836 spin_lock_irqsave(&ioapic_lock
, flags
);
1837 io_apic_write(apic
, 0, reg_00
.raw
);
1838 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1843 spin_lock_irqsave(&ioapic_lock
, flags
);
1844 reg_00
.raw
= io_apic_read(apic
, 0);
1845 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1846 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1847 printk("could not set ID!\n");
1849 apic_printk(APIC_VERBOSE
, " ok.\n");
1853 static void __init
setup_ioapic_ids_from_mpc(void) { }
1857 * There is a nasty bug in some older SMP boards, their mptable lies
1858 * about the timer IRQ. We do the following to work around the situation:
1860 * - timer IRQ defaults to IO-APIC IRQ
1861 * - if this function detects that timer IRQs are defunct, then we fall
1862 * back to ISA timer IRQs
1864 static int __init
timer_irq_works(void)
1866 unsigned long t1
= jiffies
;
1869 /* Let ten ticks pass... */
1870 mdelay((10 * 1000) / HZ
);
1873 * Expect a few ticks at least, to be sure some possible
1874 * glue logic does not lock up after one or two first
1875 * ticks in a non-ExtINT mode. Also the local APIC
1876 * might have cached one ExtINT interrupt. Finally, at
1877 * least one tick may be lost due to delays.
1879 if (jiffies
- t1
> 4)
1886 * In the SMP+IOAPIC case it might happen that there are an unspecified
1887 * number of pending IRQ events unhandled. These cases are very rare,
1888 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1889 * better to do it this way as thus we do not have to be aware of
1890 * 'pending' interrupts in the IRQ path, except at this point.
1893 * Edge triggered needs to resend any interrupt
1894 * that was delayed but this is now handled in the device
1899 * Starting up a edge-triggered IO-APIC interrupt is
1900 * nasty - we need to make sure that we get the edge.
1901 * If it is already asserted for some reason, we need
1902 * return 1 to indicate that is was pending.
1904 * This is not complete - we should be able to fake
1905 * an edge even if it isn't on the 8259A...
1907 static unsigned int startup_edge_ioapic_irq(unsigned int irq
)
1909 int was_pending
= 0;
1910 unsigned long flags
;
1912 spin_lock_irqsave(&ioapic_lock
, flags
);
1914 disable_8259A_irq(irq
);
1915 if (i8259A_irq_pending(irq
))
1918 __unmask_IO_APIC_irq(irq
);
1919 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1925 * Once we have recorded IRQ_PENDING already, we can mask the
1926 * interrupt for real. This prevents IRQ storms from unhandled
1929 static void ack_edge_ioapic_irq(unsigned int irq
)
1932 if ((irq_desc
[irq
].status
& (IRQ_PENDING
| IRQ_DISABLED
))
1933 == (IRQ_PENDING
| IRQ_DISABLED
))
1934 mask_IO_APIC_irq(irq
);
1939 * Level triggered interrupts can just be masked,
1940 * and shutting down and starting up the interrupt
1941 * is the same as enabling and disabling them -- except
1942 * with a startup need to return a "was pending" value.
1944 * Level triggered interrupts are special because we
1945 * do not touch any IO-APIC register while handling
1946 * them. We ack the APIC in the end-IRQ handler, not
1947 * in the start-IRQ-handler. Protection against reentrance
1948 * from the same interrupt is still provided, both by the
1949 * generic IRQ layer and by the fact that an unacked local
1950 * APIC does not accept IRQs.
1952 static unsigned int startup_level_ioapic_irq (unsigned int irq
)
1954 unmask_IO_APIC_irq(irq
);
1956 return 0; /* don't check for pending */
1959 static void end_level_ioapic_irq (unsigned int irq
)
1966 * It appears there is an erratum which affects at least version 0x11
1967 * of I/O APIC (that's the 82093AA and cores integrated into various
1968 * chipsets). Under certain conditions a level-triggered interrupt is
1969 * erroneously delivered as edge-triggered one but the respective IRR
1970 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1971 * message but it will never arrive and further interrupts are blocked
1972 * from the source. The exact reason is so far unknown, but the
1973 * phenomenon was observed when two consecutive interrupt requests
1974 * from a given source get delivered to the same CPU and the source is
1975 * temporarily disabled in between.
1977 * A workaround is to simulate an EOI message manually. We achieve it
1978 * by setting the trigger mode to edge and then to level when the edge
1979 * trigger mode gets detected in the TMR of a local APIC for a
1980 * level-triggered interrupt. We mask the source for the time of the
1981 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1982 * The idea is from Manfred Spraul. --macro
1984 i
= IO_APIC_VECTOR(irq
);
1986 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1990 if (!(v
& (1 << (i
& 0x1f)))) {
1991 atomic_inc(&irq_mis_count
);
1992 spin_lock(&ioapic_lock
);
1993 __mask_and_edge_IO_APIC_irq(irq
);
1994 __unmask_and_level_IO_APIC_irq(irq
);
1995 spin_unlock(&ioapic_lock
);
1999 #ifdef CONFIG_PCI_MSI
2000 static unsigned int startup_edge_ioapic_vector(unsigned int vector
)
2002 int irq
= vector_to_irq(vector
);
2004 return startup_edge_ioapic_irq(irq
);
2007 static void ack_edge_ioapic_vector(unsigned int vector
)
2009 int irq
= vector_to_irq(vector
);
2011 move_native_irq(vector
);
2012 ack_edge_ioapic_irq(irq
);
2015 static unsigned int startup_level_ioapic_vector (unsigned int vector
)
2017 int irq
= vector_to_irq(vector
);
2019 return startup_level_ioapic_irq (irq
);
2022 static void end_level_ioapic_vector (unsigned int vector
)
2024 int irq
= vector_to_irq(vector
);
2026 move_native_irq(vector
);
2027 end_level_ioapic_irq(irq
);
2030 static void mask_IO_APIC_vector (unsigned int vector
)
2032 int irq
= vector_to_irq(vector
);
2034 mask_IO_APIC_irq(irq
);
2037 static void unmask_IO_APIC_vector (unsigned int vector
)
2039 int irq
= vector_to_irq(vector
);
2041 unmask_IO_APIC_irq(irq
);
2045 static void set_ioapic_affinity_vector (unsigned int vector
,
2048 int irq
= vector_to_irq(vector
);
2050 set_native_irq_info(vector
, cpu_mask
);
2051 set_ioapic_affinity_irq(irq
, cpu_mask
);
2057 * Level and edge triggered IO-APIC interrupts need different handling,
2058 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2059 * handled with the level-triggered descriptor, but that one has slightly
2060 * more overhead. Level-triggered interrupts cannot be handled with the
2061 * edge-triggered handler, without risking IRQ storms and other ugly
2064 static struct hw_interrupt_type ioapic_edge_type __read_mostly
= {
2065 .typename
= "IO-APIC-edge",
2066 .startup
= startup_edge_ioapic
,
2067 .shutdown
= shutdown_edge_ioapic
,
2068 .enable
= enable_edge_ioapic
,
2069 .disable
= disable_edge_ioapic
,
2070 .ack
= ack_edge_ioapic
,
2071 .end
= end_edge_ioapic
,
2073 .set_affinity
= set_ioapic_affinity
,
2077 static struct hw_interrupt_type ioapic_level_type __read_mostly
= {
2078 .typename
= "IO-APIC-level",
2079 .startup
= startup_level_ioapic
,
2080 .shutdown
= shutdown_level_ioapic
,
2081 .enable
= enable_level_ioapic
,
2082 .disable
= disable_level_ioapic
,
2083 .ack
= mask_and_ack_level_ioapic
,
2084 .end
= end_level_ioapic
,
2086 .set_affinity
= set_ioapic_affinity
,
2090 static inline void init_IO_APIC_traps(void)
2095 * NOTE! The local APIC isn't very good at handling
2096 * multiple interrupts at the same interrupt level.
2097 * As the interrupt level is determined by taking the
2098 * vector number and shifting that right by 4, we
2099 * want to spread these out a bit so that they don't
2100 * all fall in the same interrupt level.
2102 * Also, we've got to be careful not to trash gate
2103 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2105 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
2107 if (use_pci_vector()) {
2108 if (!platform_legacy_irq(tmp
))
2109 if ((tmp
= vector_to_irq(tmp
)) == -1)
2112 if (IO_APIC_IRQ(tmp
) && !IO_APIC_VECTOR(tmp
)) {
2114 * Hmm.. We don't have an entry for this,
2115 * so default to an old-fashioned 8259
2116 * interrupt if we can..
2119 make_8259A_irq(irq
);
2121 /* Strange. Oh, well.. */
2122 irq_desc
[irq
].handler
= &no_irq_type
;
2127 static void enable_lapic_irq (unsigned int irq
)
2131 v
= apic_read(APIC_LVT0
);
2132 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2135 static void disable_lapic_irq (unsigned int irq
)
2139 v
= apic_read(APIC_LVT0
);
2140 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2143 static void ack_lapic_irq (unsigned int irq
)
2148 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
2150 static struct hw_interrupt_type lapic_irq_type __read_mostly
= {
2151 .typename
= "local-APIC-edge",
2152 .startup
= NULL
, /* startup_irq() not used for IRQ0 */
2153 .shutdown
= NULL
, /* shutdown_irq() not used for IRQ0 */
2154 .enable
= enable_lapic_irq
,
2155 .disable
= disable_lapic_irq
,
2156 .ack
= ack_lapic_irq
,
2157 .end
= end_lapic_irq
2160 static void setup_nmi (void)
2163 * Dirty trick to enable the NMI watchdog ...
2164 * We put the 8259A master into AEOI mode and
2165 * unmask on all local APICs LVT0 as NMI.
2167 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2168 * is from Maciej W. Rozycki - so we do not have to EOI from
2169 * the NMI handler or the timer interrupt.
2171 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2173 on_each_cpu(enable_NMI_through_LVT0
, NULL
, 1, 1);
2175 apic_printk(APIC_VERBOSE
, " done.\n");
2179 * This looks a bit hackish but it's about the only one way of sending
2180 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2181 * not support the ExtINT mode, unfortunately. We need to send these
2182 * cycles as some i82489DX-based boards have glue logic that keeps the
2183 * 8259A interrupt line asserted until INTA. --macro
2185 static inline void unlock_ExtINT_logic(void)
2188 struct IO_APIC_route_entry entry0
, entry1
;
2189 unsigned char save_control
, save_freq_select
;
2190 unsigned long flags
;
2192 pin
= find_isa_irq_pin(8, mp_INT
);
2193 apic
= find_isa_irq_apic(8, mp_INT
);
2197 spin_lock_irqsave(&ioapic_lock
, flags
);
2198 *(((int *)&entry0
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
2199 *(((int *)&entry0
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
2200 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2201 clear_IO_APIC_pin(apic
, pin
);
2203 memset(&entry1
, 0, sizeof(entry1
));
2205 entry1
.dest_mode
= 0; /* physical delivery */
2206 entry1
.mask
= 0; /* unmask IRQ now */
2207 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2208 entry1
.delivery_mode
= dest_ExtINT
;
2209 entry1
.polarity
= entry0
.polarity
;
2213 spin_lock_irqsave(&ioapic_lock
, flags
);
2214 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry1
) + 1));
2215 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry1
) + 0));
2216 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2218 save_control
= CMOS_READ(RTC_CONTROL
);
2219 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2220 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2222 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2227 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2231 CMOS_WRITE(save_control
, RTC_CONTROL
);
2232 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2233 clear_IO_APIC_pin(apic
, pin
);
2235 spin_lock_irqsave(&ioapic_lock
, flags
);
2236 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry0
) + 1));
2237 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry0
) + 0));
2238 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2242 * This code may look a bit paranoid, but it's supposed to cooperate with
2243 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2244 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2245 * fanatically on his truly buggy board.
2247 static inline void check_timer(void)
2249 int apic1
, pin1
, apic2
, pin2
;
2253 * get/set the timer IRQ vector:
2255 disable_8259A_irq(0);
2256 vector
= assign_irq_vector(0);
2257 set_intr_gate(vector
, interrupt
[0]);
2260 * Subtle, code in do_timer_interrupt() expects an AEOI
2261 * mode for the 8259A whenever interrupts are routed
2262 * through I/O APICs. Also IRQ0 has to be enabled in
2263 * the 8259A which implies the virtual wire has to be
2264 * disabled in the local APIC.
2266 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2269 if (timer_over_8254
> 0)
2270 enable_8259A_irq(0);
2272 pin1
= find_isa_irq_pin(0, mp_INT
);
2273 apic1
= find_isa_irq_apic(0, mp_INT
);
2274 pin2
= ioapic_i8259
.pin
;
2275 apic2
= ioapic_i8259
.apic
;
2277 printk(KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2278 vector
, apic1
, pin1
, apic2
, pin2
);
2282 * Ok, does IRQ0 through the IOAPIC work?
2284 unmask_IO_APIC_irq(0);
2285 if (timer_irq_works()) {
2286 if (nmi_watchdog
== NMI_IO_APIC
) {
2287 disable_8259A_irq(0);
2289 enable_8259A_irq(0);
2291 if (disable_timer_pin_1
> 0)
2292 clear_IO_APIC_pin(0, pin1
);
2295 clear_IO_APIC_pin(apic1
, pin1
);
2296 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to "
2300 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2302 printk("\n..... (found pin %d) ...", pin2
);
2304 * legacy devices should be connected to IO APIC #0
2306 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
2307 if (timer_irq_works()) {
2310 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2312 add_pin_to_irq(0, apic2
, pin2
);
2313 if (nmi_watchdog
== NMI_IO_APIC
) {
2319 * Cleanup, just in case ...
2321 clear_IO_APIC_pin(apic2
, pin2
);
2323 printk(" failed.\n");
2325 if (nmi_watchdog
== NMI_IO_APIC
) {
2326 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2330 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2332 disable_8259A_irq(0);
2333 irq_desc
[0].handler
= &lapic_irq_type
;
2334 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2335 enable_8259A_irq(0);
2337 if (timer_irq_works()) {
2338 printk(" works.\n");
2341 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2342 printk(" failed.\n");
2344 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2349 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2351 unlock_ExtINT_logic();
2353 if (timer_irq_works()) {
2354 printk(" works.\n");
2357 printk(" failed :(.\n");
2358 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2359 "report. Then try booting with the 'noapic' option");
2364 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2365 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2366 * Linux doesn't really care, as it's not actually used
2367 * for any interrupt handling anyway.
2369 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2371 void __init
setup_IO_APIC(void)
2376 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2378 io_apic_irqs
= ~PIC_IRQS
;
2380 printk("ENABLING IO-APIC IRQs\n");
2383 * Set up IO-APIC IRQ routing.
2386 setup_ioapic_ids_from_mpc();
2388 setup_IO_APIC_irqs();
2389 init_IO_APIC_traps();
2395 static int __init
setup_disable_8254_timer(char *s
)
2397 timer_over_8254
= -1;
2400 static int __init
setup_enable_8254_timer(char *s
)
2402 timer_over_8254
= 2;
2406 __setup("disable_8254_timer", setup_disable_8254_timer
);
2407 __setup("enable_8254_timer", setup_enable_8254_timer
);
2410 * Called after all the initialization is done. If we didnt find any
2411 * APIC bugs then we can allow the modify fast path
2414 static int __init
io_apic_bug_finalize(void)
2416 if(sis_apic_bug
== -1)
2421 late_initcall(io_apic_bug_finalize
);
2423 struct sysfs_ioapic_data
{
2424 struct sys_device dev
;
2425 struct IO_APIC_route_entry entry
[0];
2427 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2429 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2431 struct IO_APIC_route_entry
*entry
;
2432 struct sysfs_ioapic_data
*data
;
2433 unsigned long flags
;
2436 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2437 entry
= data
->entry
;
2438 spin_lock_irqsave(&ioapic_lock
, flags
);
2439 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ ) {
2440 *(((int *)entry
) + 1) = io_apic_read(dev
->id
, 0x11 + 2 * i
);
2441 *(((int *)entry
) + 0) = io_apic_read(dev
->id
, 0x10 + 2 * i
);
2443 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2448 static int ioapic_resume(struct sys_device
*dev
)
2450 struct IO_APIC_route_entry
*entry
;
2451 struct sysfs_ioapic_data
*data
;
2452 unsigned long flags
;
2453 union IO_APIC_reg_00 reg_00
;
2456 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2457 entry
= data
->entry
;
2459 spin_lock_irqsave(&ioapic_lock
, flags
);
2460 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2461 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2462 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2463 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2465 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ ) {
2466 io_apic_write(dev
->id
, 0x11+2*i
, *(((int *)entry
)+1));
2467 io_apic_write(dev
->id
, 0x10+2*i
, *(((int *)entry
)+0));
2469 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2474 static struct sysdev_class ioapic_sysdev_class
= {
2475 set_kset_name("ioapic"),
2476 .suspend
= ioapic_suspend
,
2477 .resume
= ioapic_resume
,
2480 static int __init
ioapic_init_sysfs(void)
2482 struct sys_device
* dev
;
2483 int i
, size
, error
= 0;
2485 error
= sysdev_class_register(&ioapic_sysdev_class
);
2489 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2490 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2491 * sizeof(struct IO_APIC_route_entry
);
2492 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2493 if (!mp_ioapic_data
[i
]) {
2494 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2497 memset(mp_ioapic_data
[i
], 0, size
);
2498 dev
= &mp_ioapic_data
[i
]->dev
;
2500 dev
->cls
= &ioapic_sysdev_class
;
2501 error
= sysdev_register(dev
);
2503 kfree(mp_ioapic_data
[i
]);
2504 mp_ioapic_data
[i
] = NULL
;
2505 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2513 device_initcall(ioapic_init_sysfs
);
2515 /* --------------------------------------------------------------------------
2516 ACPI-based IOAPIC Configuration
2517 -------------------------------------------------------------------------- */
2521 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2523 union IO_APIC_reg_00 reg_00
;
2524 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2526 unsigned long flags
;
2530 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2531 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2532 * supports up to 16 on one shared APIC bus.
2534 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2535 * advantage of new APIC bus architecture.
2538 if (physids_empty(apic_id_map
))
2539 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2541 spin_lock_irqsave(&ioapic_lock
, flags
);
2542 reg_00
.raw
= io_apic_read(ioapic
, 0);
2543 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2545 if (apic_id
>= get_physical_broadcast()) {
2546 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2547 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2548 apic_id
= reg_00
.bits
.ID
;
2552 * Every APIC in a system must have a unique ID or we get lots of nice
2553 * 'stuck on smp_invalidate_needed IPI wait' messages.
2555 if (check_apicid_used(apic_id_map
, apic_id
)) {
2557 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2558 if (!check_apicid_used(apic_id_map
, i
))
2562 if (i
== get_physical_broadcast())
2563 panic("Max apic_id exceeded!\n");
2565 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2566 "trying %d\n", ioapic
, apic_id
, i
);
2571 tmp
= apicid_to_cpu_present(apic_id
);
2572 physids_or(apic_id_map
, apic_id_map
, tmp
);
2574 if (reg_00
.bits
.ID
!= apic_id
) {
2575 reg_00
.bits
.ID
= apic_id
;
2577 spin_lock_irqsave(&ioapic_lock
, flags
);
2578 io_apic_write(ioapic
, 0, reg_00
.raw
);
2579 reg_00
.raw
= io_apic_read(ioapic
, 0);
2580 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2583 if (reg_00
.bits
.ID
!= apic_id
) {
2584 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2589 apic_printk(APIC_VERBOSE
, KERN_INFO
2590 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2596 int __init
io_apic_get_version (int ioapic
)
2598 union IO_APIC_reg_01 reg_01
;
2599 unsigned long flags
;
2601 spin_lock_irqsave(&ioapic_lock
, flags
);
2602 reg_01
.raw
= io_apic_read(ioapic
, 1);
2603 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2605 return reg_01
.bits
.version
;
2609 int __init
io_apic_get_redir_entries (int ioapic
)
2611 union IO_APIC_reg_01 reg_01
;
2612 unsigned long flags
;
2614 spin_lock_irqsave(&ioapic_lock
, flags
);
2615 reg_01
.raw
= io_apic_read(ioapic
, 1);
2616 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2618 return reg_01
.bits
.entries
;
2622 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2624 struct IO_APIC_route_entry entry
;
2625 unsigned long flags
;
2627 if (!IO_APIC_IRQ(irq
)) {
2628 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2634 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2635 * Note that we mask (disable) IRQs now -- these get enabled when the
2636 * corresponding device driver registers for this IRQ.
2639 memset(&entry
,0,sizeof(entry
));
2641 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2642 entry
.dest_mode
= INT_DEST_MODE
;
2643 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2644 entry
.trigger
= edge_level
;
2645 entry
.polarity
= active_high_low
;
2649 * IRQs < 16 are already in the irq_2_pin[] map
2652 add_pin_to_irq(irq
, ioapic
, pin
);
2654 entry
.vector
= assign_irq_vector(irq
);
2656 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2657 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2658 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2659 edge_level
, active_high_low
);
2661 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2663 if (!ioapic
&& (irq
< 16))
2664 disable_8259A_irq(irq
);
2666 spin_lock_irqsave(&ioapic_lock
, flags
);
2667 io_apic_write(ioapic
, 0x11+2*pin
, *(((int *)&entry
)+1));
2668 io_apic_write(ioapic
, 0x10+2*pin
, *(((int *)&entry
)+0));
2669 set_native_irq_info(use_pci_vector() ? entry
.vector
: irq
, TARGET_CPUS
);
2670 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2675 #endif /* CONFIG_ACPI */