2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/compiler.h>
32 #include <linux/acpi.h>
33 #include <linux/module.h>
34 #include <linux/sysdev.h>
39 #include <asm/timer.h>
40 #include <asm/i8259.h>
42 #include <mach_apic.h>
46 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
47 atomic_t irq_mis_count
;
49 /* Where if anywhere is the i8259 connect in external int mode */
50 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
52 static DEFINE_SPINLOCK(ioapic_lock
);
54 int timer_over_8254 __initdata
= 1;
57 * Is the SiS APIC rmw bug present ?
58 * -1 = don't know, 0 = no, 1 = yes
60 int sis_apic_bug
= -1;
63 * # of IRQ routing registers
65 int nr_ioapic_registers
[MAX_IO_APICS
];
67 int disable_timer_pin_1 __initdata
;
70 * Rough estimation of how many shared IRQs there are, can
73 #define MAX_PLUS_SHARED_IRQS NR_IRQS
74 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
77 * This is performance-critical, we want to do it O(1)
79 * the indexing order of this array favors 1:1 mappings
80 * between pins and IRQs.
83 static struct irq_pin_list
{
85 } irq_2_pin
[PIN_MAP_SIZE
];
87 int vector_irq
[NR_VECTORS
] __read_mostly
= { [0 ... NR_VECTORS
- 1] = -1};
89 #define vector_to_irq(vector) \
90 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
92 #define vector_to_irq(vector) (vector)
96 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
97 * shared ISA-space IRQs, so we have to support them. We are super
98 * fast in the common case, and fast for shared ISA-space IRQs.
100 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
102 static int first_free_entry
= NR_IRQS
;
103 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
106 entry
= irq_2_pin
+ entry
->next
;
108 if (entry
->pin
!= -1) {
109 entry
->next
= first_free_entry
;
110 entry
= irq_2_pin
+ entry
->next
;
111 if (++first_free_entry
>= PIN_MAP_SIZE
)
112 panic("io_apic.c: whoops");
119 * Reroute an IRQ to a different pin.
121 static void __init
replace_pin_at_irq(unsigned int irq
,
122 int oldapic
, int oldpin
,
123 int newapic
, int newpin
)
125 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
128 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
129 entry
->apic
= newapic
;
134 entry
= irq_2_pin
+ entry
->next
;
138 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
140 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
141 unsigned int pin
, reg
;
147 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
150 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
153 entry
= irq_2_pin
+ entry
->next
;
158 static void __mask_IO_APIC_irq (unsigned int irq
)
160 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
164 static void __unmask_IO_APIC_irq (unsigned int irq
)
166 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
169 /* mask = 1, trigger = 0 */
170 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
172 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
175 /* mask = 0, trigger = 1 */
176 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
178 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
181 static void mask_IO_APIC_irq (unsigned int irq
)
185 spin_lock_irqsave(&ioapic_lock
, flags
);
186 __mask_IO_APIC_irq(irq
);
187 spin_unlock_irqrestore(&ioapic_lock
, flags
);
190 static void unmask_IO_APIC_irq (unsigned int irq
)
194 spin_lock_irqsave(&ioapic_lock
, flags
);
195 __unmask_IO_APIC_irq(irq
);
196 spin_unlock_irqrestore(&ioapic_lock
, flags
);
199 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
201 struct IO_APIC_route_entry entry
;
204 /* Check delivery_mode to be sure we're not clearing an SMI pin */
205 spin_lock_irqsave(&ioapic_lock
, flags
);
206 *(((int*)&entry
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
207 *(((int*)&entry
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
208 spin_unlock_irqrestore(&ioapic_lock
, flags
);
209 if (entry
.delivery_mode
== dest_SMI
)
213 * Disable it in the IO-APIC irq-routing table:
215 memset(&entry
, 0, sizeof(entry
));
217 spin_lock_irqsave(&ioapic_lock
, flags
);
218 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry
) + 0));
219 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry
) + 1));
220 spin_unlock_irqrestore(&ioapic_lock
, flags
);
223 static void clear_IO_APIC (void)
227 for (apic
= 0; apic
< nr_ioapics
; apic
++)
228 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
229 clear_IO_APIC_pin(apic
, pin
);
233 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
237 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
238 unsigned int apicid_value
;
241 cpus_and(tmp
, cpumask
, cpu_online_map
);
245 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
247 apicid_value
= cpu_mask_to_apicid(cpumask
);
248 /* Prepare to do the io_apic_write */
249 apicid_value
= apicid_value
<< 24;
250 spin_lock_irqsave(&ioapic_lock
, flags
);
255 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
258 entry
= irq_2_pin
+ entry
->next
;
260 set_irq_info(irq
, cpumask
);
261 spin_unlock_irqrestore(&ioapic_lock
, flags
);
264 #if defined(CONFIG_IRQBALANCE)
265 # include <asm/processor.h> /* kernel_thread() */
266 # include <linux/kernel_stat.h> /* kstat */
267 # include <linux/slab.h> /* kmalloc() */
268 # include <linux/timer.h> /* time_after() */
270 #ifdef CONFIG_BALANCED_IRQ_DEBUG
271 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
272 # define Dprintk(x...) do { TDprintk(x); } while (0)
274 # define TDprintk(x...)
275 # define Dprintk(x...)
278 #define IRQBALANCE_CHECK_ARCH -999
279 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
280 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
281 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
282 #define BALANCED_IRQ_LESS_DELTA (HZ)
284 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
285 static int physical_balance __read_mostly
;
286 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
288 static struct irq_cpu_info
{
289 unsigned long * last_irq
;
290 unsigned long * irq_delta
;
292 } irq_cpu_data
[NR_CPUS
];
294 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
295 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
296 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
298 #define IDLE_ENOUGH(cpu,now) \
299 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
301 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
303 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
305 static cpumask_t balance_irq_affinity
[NR_IRQS
] = {
306 [0 ... NR_IRQS
-1] = CPU_MASK_ALL
309 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
311 balance_irq_affinity
[irq
] = mask
;
314 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
315 unsigned long now
, int direction
)
323 if (unlikely(cpu
== curr_cpu
))
326 if (direction
== 1) {
335 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
336 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
341 static inline void balance_irq(int cpu
, int irq
)
343 unsigned long now
= jiffies
;
344 cpumask_t allowed_mask
;
345 unsigned int new_cpu
;
347 if (irqbalance_disabled
)
350 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
351 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
352 if (cpu
!= new_cpu
) {
353 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
357 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
360 Dprintk("Rotating IRQs among CPUs.\n");
361 for_each_online_cpu(i
) {
362 for (j
= 0; j
< NR_IRQS
; j
++) {
363 if (!irq_desc
[j
].action
)
365 /* Is it a significant load ? */
366 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
367 useful_load_threshold
)
372 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
373 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
377 static void do_irq_balance(void)
380 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
381 unsigned long move_this_load
= 0;
382 int max_loaded
= 0, min_loaded
= 0;
384 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
386 int tmp_loaded
, first_attempt
= 1;
387 unsigned long tmp_cpu_irq
;
388 unsigned long imbalance
= 0;
389 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
391 for_each_possible_cpu(i
) {
396 package_index
= CPU_TO_PACKAGEINDEX(i
);
397 for (j
= 0; j
< NR_IRQS
; j
++) {
398 unsigned long value_now
, delta
;
399 /* Is this an active IRQ? */
400 if (!irq_desc
[j
].action
)
402 if ( package_index
== i
)
403 IRQ_DELTA(package_index
,j
) = 0;
404 /* Determine the total count per processor per IRQ */
405 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
407 /* Determine the activity per processor per IRQ */
408 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
410 /* Update last_cpu_irq[][] for the next time */
411 LAST_CPU_IRQ(i
,j
) = value_now
;
413 /* Ignore IRQs whose rate is less than the clock */
414 if (delta
< useful_load_threshold
)
416 /* update the load for the processor or package total */
417 IRQ_DELTA(package_index
,j
) += delta
;
419 /* Keep track of the higher numbered sibling as well */
420 if (i
!= package_index
)
423 * We have sibling A and sibling B in the package
425 * cpu_irq[A] = load for cpu A + load for cpu B
426 * cpu_irq[B] = load for cpu B
428 CPU_IRQ(package_index
) += delta
;
431 /* Find the least loaded processor package */
432 for_each_online_cpu(i
) {
433 if (i
!= CPU_TO_PACKAGEINDEX(i
))
435 if (min_cpu_irq
> CPU_IRQ(i
)) {
436 min_cpu_irq
= CPU_IRQ(i
);
440 max_cpu_irq
= ULONG_MAX
;
443 /* Look for heaviest loaded processor.
444 * We may come back to get the next heaviest loaded processor.
445 * Skip processors with trivial loads.
449 for_each_online_cpu(i
) {
450 if (i
!= CPU_TO_PACKAGEINDEX(i
))
452 if (max_cpu_irq
<= CPU_IRQ(i
))
454 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
455 tmp_cpu_irq
= CPU_IRQ(i
);
460 if (tmp_loaded
== -1) {
461 /* In the case of small number of heavy interrupt sources,
462 * loading some of the cpus too much. We use Ingo's original
463 * approach to rotate them around.
465 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
466 rotate_irqs_among_cpus(useful_load_threshold
);
469 goto not_worth_the_effort
;
472 first_attempt
= 0; /* heaviest search */
473 max_cpu_irq
= tmp_cpu_irq
; /* load */
474 max_loaded
= tmp_loaded
; /* processor */
475 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
477 Dprintk("max_loaded cpu = %d\n", max_loaded
);
478 Dprintk("min_loaded cpu = %d\n", min_loaded
);
479 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq
);
480 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq
);
481 Dprintk("load imbalance = %lu\n", imbalance
);
483 /* if imbalance is less than approx 10% of max load, then
484 * observe diminishing returns action. - quit
486 if (imbalance
< (max_cpu_irq
>> 3)) {
487 Dprintk("Imbalance too trivial\n");
488 goto not_worth_the_effort
;
492 /* if we select an IRQ to move that can't go where we want, then
493 * see if there is another one to try.
497 for (j
= 0; j
< NR_IRQS
; j
++) {
498 /* Is this an active IRQ? */
499 if (!irq_desc
[j
].action
)
501 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
503 /* Try to find the IRQ that is closest to the imbalance
504 * without going over.
506 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
507 move_this_load
= IRQ_DELTA(max_loaded
,j
);
511 if (selected_irq
== -1) {
515 imbalance
= move_this_load
;
517 /* For physical_balance case, we accumlated both load
518 * values in the one of the siblings cpu_irq[],
519 * to use the same code for physical and logical processors
520 * as much as possible.
522 * NOTE: the cpu_irq[] array holds the sum of the load for
523 * sibling A and sibling B in the slot for the lowest numbered
524 * sibling (A), _AND_ the load for sibling B in the slot for
525 * the higher numbered sibling.
527 * We seek the least loaded sibling by making the comparison
530 load
= CPU_IRQ(min_loaded
) >> 1;
531 for_each_cpu_mask(j
, cpu_sibling_map
[min_loaded
]) {
532 if (load
> CPU_IRQ(j
)) {
533 /* This won't change cpu_sibling_map[min_loaded] */
539 cpus_and(allowed_mask
,
541 balance_irq_affinity
[selected_irq
]);
542 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
543 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
545 if (!cpus_empty(tmp
)) {
547 Dprintk("irq = %d moved to cpu = %d\n",
548 selected_irq
, min_loaded
);
549 /* mark for change destination */
550 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
552 /* Since we made a change, come back sooner to
553 * check for more variation.
555 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
556 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
561 not_worth_the_effort
:
563 * if we did not find an IRQ to move, then adjust the time interval
566 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
567 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
568 Dprintk("IRQ worth rotating not found\n");
572 static int balanced_irq(void *unused
)
575 unsigned long prev_balance_time
= jiffies
;
576 long time_remaining
= balanced_irq_interval
;
580 /* push everything to CPU 0 to give us a starting point. */
581 for (i
= 0 ; i
< NR_IRQS
; i
++) {
582 pending_irq_cpumask
[i
] = cpumask_of_cpu(0);
583 set_pending_irq(i
, cpumask_of_cpu(0));
587 time_remaining
= schedule_timeout_interruptible(time_remaining
);
589 if (time_after(jiffies
,
590 prev_balance_time
+balanced_irq_interval
)) {
593 prev_balance_time
= jiffies
;
594 time_remaining
= balanced_irq_interval
;
601 static int __init
balanced_irq_init(void)
604 struct cpuinfo_x86
*c
;
607 cpus_shift_right(tmp
, cpu_online_map
, 2);
609 /* When not overwritten by the command line ask subarchitecture. */
610 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
611 irqbalance_disabled
= NO_BALANCE_IRQ
;
612 if (irqbalance_disabled
)
615 /* disable irqbalance completely if there is only one processor online */
616 if (num_online_cpus() < 2) {
617 irqbalance_disabled
= 1;
621 * Enable physical balance only if more than 1 physical processor
624 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
625 physical_balance
= 1;
627 for_each_online_cpu(i
) {
628 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
629 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
630 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
631 printk(KERN_ERR
"balanced_irq_init: out of memory");
634 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
635 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
638 printk(KERN_INFO
"Starting balanced_irq\n");
639 if (kernel_thread(balanced_irq
, NULL
, CLONE_KERNEL
) >= 0)
642 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
644 for_each_possible_cpu(i
) {
645 kfree(irq_cpu_data
[i
].irq_delta
);
646 irq_cpu_data
[i
].irq_delta
= NULL
;
647 kfree(irq_cpu_data
[i
].last_irq
);
648 irq_cpu_data
[i
].last_irq
= NULL
;
653 int __init
irqbalance_disable(char *str
)
655 irqbalance_disabled
= 1;
659 __setup("noirqbalance", irqbalance_disable
);
661 late_initcall(balanced_irq_init
);
662 #endif /* CONFIG_IRQBALANCE */
663 #endif /* CONFIG_SMP */
666 void fastcall
send_IPI_self(int vector
)
673 apic_wait_icr_idle();
674 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
676 * Send the IPI. The write to APIC_ICR fires this off.
678 apic_write_around(APIC_ICR
, cfg
);
680 #endif /* !CONFIG_SMP */
684 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
685 * specific CPU-side IRQs.
689 static int pirq_entries
[MAX_PIRQS
];
690 static int pirqs_enabled
;
691 int skip_ioapic_setup
;
693 static int __init
ioapic_setup(char *str
)
695 skip_ioapic_setup
= 1;
699 __setup("noapic", ioapic_setup
);
701 static int __init
ioapic_pirq_setup(char *str
)
704 int ints
[MAX_PIRQS
+1];
706 get_options(str
, ARRAY_SIZE(ints
), ints
);
708 for (i
= 0; i
< MAX_PIRQS
; i
++)
709 pirq_entries
[i
] = -1;
712 apic_printk(APIC_VERBOSE
, KERN_INFO
713 "PIRQ redirection, working around broken MP-BIOS.\n");
715 if (ints
[0] < MAX_PIRQS
)
718 for (i
= 0; i
< max
; i
++) {
719 apic_printk(APIC_VERBOSE
, KERN_DEBUG
720 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
722 * PIRQs are mapped upside down, usually.
724 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
729 __setup("pirq=", ioapic_pirq_setup
);
732 * Find the IRQ entry number of a certain pin.
734 static int find_irq_entry(int apic
, int pin
, int type
)
738 for (i
= 0; i
< mp_irq_entries
; i
++)
739 if (mp_irqs
[i
].mpc_irqtype
== type
&&
740 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
741 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
742 mp_irqs
[i
].mpc_dstirq
== pin
)
749 * Find the pin to which IRQ[irq] (ISA) is connected
751 static int __init
find_isa_irq_pin(int irq
, int type
)
755 for (i
= 0; i
< mp_irq_entries
; i
++) {
756 int lbus
= mp_irqs
[i
].mpc_srcbus
;
758 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
759 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
760 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
761 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
763 (mp_irqs
[i
].mpc_irqtype
== type
) &&
764 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
766 return mp_irqs
[i
].mpc_dstirq
;
771 static int __init
find_isa_irq_apic(int irq
, int type
)
775 for (i
= 0; i
< mp_irq_entries
; i
++) {
776 int lbus
= mp_irqs
[i
].mpc_srcbus
;
778 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
779 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
780 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
781 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
783 (mp_irqs
[i
].mpc_irqtype
== type
) &&
784 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
787 if (i
< mp_irq_entries
) {
789 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
790 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
799 * Find a specific PCI IRQ entry.
800 * Not an __init, possibly needed by modules
802 static int pin_2_irq(int idx
, int apic
, int pin
);
804 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
806 int apic
, i
, best_guess
= -1;
808 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
809 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
810 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
811 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
814 for (i
= 0; i
< mp_irq_entries
; i
++) {
815 int lbus
= mp_irqs
[i
].mpc_srcbus
;
817 for (apic
= 0; apic
< nr_ioapics
; apic
++)
818 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
819 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
822 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
823 !mp_irqs
[i
].mpc_irqtype
&&
825 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
826 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
828 if (!(apic
|| IO_APIC_IRQ(irq
)))
831 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
834 * Use the first all-but-pin matching entry as a
835 * best-guess fuzzy result for broken mptables.
843 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
846 * This function currently is only a helper for the i386 smp boot process where
847 * we need to reprogram the ioredtbls to cater for the cpus which have come online
848 * so mask in all cases should simply be TARGET_CPUS
851 void __init
setup_ioapic_dest(void)
853 int pin
, ioapic
, irq
, irq_entry
;
855 if (skip_ioapic_setup
== 1)
858 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
859 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
860 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
863 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
864 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
872 * EISA Edge/Level control register, ELCR
874 static int EISA_ELCR(unsigned int irq
)
877 unsigned int port
= 0x4d0 + (irq
>> 3);
878 return (inb(port
) >> (irq
& 7)) & 1;
880 apic_printk(APIC_VERBOSE
, KERN_INFO
881 "Broken MPtable reports ISA irq %d\n", irq
);
885 /* EISA interrupts are always polarity zero and can be edge or level
886 * trigger depending on the ELCR value. If an interrupt is listed as
887 * EISA conforming in the MP table, that means its trigger type must
888 * be read in from the ELCR */
890 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
891 #define default_EISA_polarity(idx) (0)
893 /* ISA interrupts are always polarity zero edge triggered,
894 * when listed as conforming in the MP table. */
896 #define default_ISA_trigger(idx) (0)
897 #define default_ISA_polarity(idx) (0)
899 /* PCI interrupts are always polarity one level triggered,
900 * when listed as conforming in the MP table. */
902 #define default_PCI_trigger(idx) (1)
903 #define default_PCI_polarity(idx) (1)
905 /* MCA interrupts are always polarity zero level triggered,
906 * when listed as conforming in the MP table. */
908 #define default_MCA_trigger(idx) (1)
909 #define default_MCA_polarity(idx) (0)
911 /* NEC98 interrupts are always polarity zero edge triggered,
912 * when listed as conforming in the MP table. */
914 #define default_NEC98_trigger(idx) (0)
915 #define default_NEC98_polarity(idx) (0)
917 static int __init
MPBIOS_polarity(int idx
)
919 int bus
= mp_irqs
[idx
].mpc_srcbus
;
923 * Determine IRQ line polarity (high active or low active):
925 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
927 case 0: /* conforms, ie. bus-type dependent polarity */
929 switch (mp_bus_id_to_type
[bus
])
931 case MP_BUS_ISA
: /* ISA pin */
933 polarity
= default_ISA_polarity(idx
);
936 case MP_BUS_EISA
: /* EISA pin */
938 polarity
= default_EISA_polarity(idx
);
941 case MP_BUS_PCI
: /* PCI pin */
943 polarity
= default_PCI_polarity(idx
);
946 case MP_BUS_MCA
: /* MCA pin */
948 polarity
= default_MCA_polarity(idx
);
951 case MP_BUS_NEC98
: /* NEC 98 pin */
953 polarity
= default_NEC98_polarity(idx
);
958 printk(KERN_WARNING
"broken BIOS!!\n");
965 case 1: /* high active */
970 case 2: /* reserved */
972 printk(KERN_WARNING
"broken BIOS!!\n");
976 case 3: /* low active */
981 default: /* invalid */
983 printk(KERN_WARNING
"broken BIOS!!\n");
991 static int MPBIOS_trigger(int idx
)
993 int bus
= mp_irqs
[idx
].mpc_srcbus
;
997 * Determine IRQ trigger mode (edge or level sensitive):
999 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
1001 case 0: /* conforms, ie. bus-type dependent */
1003 switch (mp_bus_id_to_type
[bus
])
1005 case MP_BUS_ISA
: /* ISA pin */
1007 trigger
= default_ISA_trigger(idx
);
1010 case MP_BUS_EISA
: /* EISA pin */
1012 trigger
= default_EISA_trigger(idx
);
1015 case MP_BUS_PCI
: /* PCI pin */
1017 trigger
= default_PCI_trigger(idx
);
1020 case MP_BUS_MCA
: /* MCA pin */
1022 trigger
= default_MCA_trigger(idx
);
1025 case MP_BUS_NEC98
: /* NEC 98 pin */
1027 trigger
= default_NEC98_trigger(idx
);
1032 printk(KERN_WARNING
"broken BIOS!!\n");
1044 case 2: /* reserved */
1046 printk(KERN_WARNING
"broken BIOS!!\n");
1055 default: /* invalid */
1057 printk(KERN_WARNING
"broken BIOS!!\n");
1065 static inline int irq_polarity(int idx
)
1067 return MPBIOS_polarity(idx
);
1070 static inline int irq_trigger(int idx
)
1072 return MPBIOS_trigger(idx
);
1075 static int pin_2_irq(int idx
, int apic
, int pin
)
1078 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1081 * Debugging check, we are in big trouble if this message pops up!
1083 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1084 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1086 switch (mp_bus_id_to_type
[bus
])
1088 case MP_BUS_ISA
: /* ISA pin */
1093 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1096 case MP_BUS_PCI
: /* PCI pin */
1099 * PCI IRQs are mapped in order
1103 irq
+= nr_ioapic_registers
[i
++];
1107 * For MPS mode, so far only needed by ES7000 platform
1109 if (ioapic_renumber_irq
)
1110 irq
= ioapic_renumber_irq(apic
, irq
);
1116 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
1123 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1125 if ((pin
>= 16) && (pin
<= 23)) {
1126 if (pirq_entries
[pin
-16] != -1) {
1127 if (!pirq_entries
[pin
-16]) {
1128 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1129 "disabling PIRQ%d\n", pin
-16);
1131 irq
= pirq_entries
[pin
-16];
1132 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1133 "using PIRQ%d -> IRQ %d\n",
1141 static inline int IO_APIC_irq_trigger(int irq
)
1145 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1146 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1147 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1148 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1149 return irq_trigger(idx
);
1153 * nonexistent IRQs are edge default
1158 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1159 u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1161 int assign_irq_vector(int irq
)
1163 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
1165 BUG_ON(irq
>= NR_IRQ_VECTORS
);
1166 if (irq
!= AUTO_ASSIGN
&& IO_APIC_VECTOR(irq
) > 0)
1167 return IO_APIC_VECTOR(irq
);
1169 current_vector
+= 8;
1170 if (current_vector
== SYSCALL_VECTOR
)
1173 if (current_vector
>= FIRST_SYSTEM_VECTOR
) {
1177 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
1180 vector_irq
[current_vector
] = irq
;
1181 if (irq
!= AUTO_ASSIGN
)
1182 IO_APIC_VECTOR(irq
) = current_vector
;
1184 return current_vector
;
1187 static struct hw_interrupt_type ioapic_level_type
;
1188 static struct hw_interrupt_type ioapic_edge_type
;
1190 #define IOAPIC_AUTO -1
1191 #define IOAPIC_EDGE 0
1192 #define IOAPIC_LEVEL 1
1194 static inline void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1196 if (use_pci_vector() && !platform_legacy_irq(irq
)) {
1197 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1198 trigger
== IOAPIC_LEVEL
)
1199 irq_desc
[vector
].handler
= &ioapic_level_type
;
1201 irq_desc
[vector
].handler
= &ioapic_edge_type
;
1202 set_intr_gate(vector
, interrupt
[vector
]);
1204 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1205 trigger
== IOAPIC_LEVEL
)
1206 irq_desc
[irq
].handler
= &ioapic_level_type
;
1208 irq_desc
[irq
].handler
= &ioapic_edge_type
;
1209 set_intr_gate(vector
, interrupt
[irq
]);
1213 static void __init
setup_IO_APIC_irqs(void)
1215 struct IO_APIC_route_entry entry
;
1216 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1217 unsigned long flags
;
1219 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1221 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1222 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1225 * add it to the IO-APIC irq-routing table:
1227 memset(&entry
,0,sizeof(entry
));
1229 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1230 entry
.dest_mode
= INT_DEST_MODE
;
1231 entry
.mask
= 0; /* enable IRQ */
1232 entry
.dest
.logical
.logical_dest
=
1233 cpu_mask_to_apicid(TARGET_CPUS
);
1235 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1238 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1239 " IO-APIC (apicid-pin) %d-%d",
1240 mp_ioapics
[apic
].mpc_apicid
,
1244 apic_printk(APIC_VERBOSE
, ", %d-%d",
1245 mp_ioapics
[apic
].mpc_apicid
, pin
);
1249 entry
.trigger
= irq_trigger(idx
);
1250 entry
.polarity
= irq_polarity(idx
);
1252 if (irq_trigger(idx
)) {
1257 irq
= pin_2_irq(idx
, apic
, pin
);
1259 * skip adding the timer int on secondary nodes, which causes
1260 * a small but painful rift in the time-space continuum
1262 if (multi_timer_check(apic
, irq
))
1265 add_pin_to_irq(irq
, apic
, pin
);
1267 if (!apic
&& !IO_APIC_IRQ(irq
))
1270 if (IO_APIC_IRQ(irq
)) {
1271 vector
= assign_irq_vector(irq
);
1272 entry
.vector
= vector
;
1273 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1275 if (!apic
&& (irq
< 16))
1276 disable_8259A_irq(irq
);
1278 spin_lock_irqsave(&ioapic_lock
, flags
);
1279 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
1280 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
1281 set_native_irq_info(irq
, TARGET_CPUS
);
1282 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1287 apic_printk(APIC_VERBOSE
, " not connected.\n");
1291 * Set up the 8259A-master output pin:
1293 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
1295 struct IO_APIC_route_entry entry
;
1296 unsigned long flags
;
1298 memset(&entry
,0,sizeof(entry
));
1300 disable_8259A_irq(0);
1303 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1306 * We use logical delivery to get the timer IRQ
1309 entry
.dest_mode
= INT_DEST_MODE
;
1310 entry
.mask
= 0; /* unmask IRQ now */
1311 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1312 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1315 entry
.vector
= vector
;
1318 * The timer IRQ doesn't have to know that behind the
1319 * scene we have a 8259A-master in AEOI mode ...
1321 irq_desc
[0].handler
= &ioapic_edge_type
;
1324 * Add it to the IO-APIC irq-routing table:
1326 spin_lock_irqsave(&ioapic_lock
, flags
);
1327 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
1328 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
1329 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1331 enable_8259A_irq(0);
1334 static inline void UNEXPECTED_IO_APIC(void)
1338 void __init
print_IO_APIC(void)
1341 union IO_APIC_reg_00 reg_00
;
1342 union IO_APIC_reg_01 reg_01
;
1343 union IO_APIC_reg_02 reg_02
;
1344 union IO_APIC_reg_03 reg_03
;
1345 unsigned long flags
;
1347 if (apic_verbosity
== APIC_QUIET
)
1350 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1351 for (i
= 0; i
< nr_ioapics
; i
++)
1352 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1353 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1356 * We are a bit conservative about what we expect. We have to
1357 * know about every hardware change ASAP.
1359 printk(KERN_INFO
"testing the IO APIC.......................\n");
1361 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1363 spin_lock_irqsave(&ioapic_lock
, flags
);
1364 reg_00
.raw
= io_apic_read(apic
, 0);
1365 reg_01
.raw
= io_apic_read(apic
, 1);
1366 if (reg_01
.bits
.version
>= 0x10)
1367 reg_02
.raw
= io_apic_read(apic
, 2);
1368 if (reg_01
.bits
.version
>= 0x20)
1369 reg_03
.raw
= io_apic_read(apic
, 3);
1370 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1372 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1373 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1374 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1375 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1376 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1377 if (reg_00
.bits
.ID
>= get_physical_broadcast())
1378 UNEXPECTED_IO_APIC();
1379 if (reg_00
.bits
.__reserved_1
|| reg_00
.bits
.__reserved_2
)
1380 UNEXPECTED_IO_APIC();
1382 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1383 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1384 if ( (reg_01
.bits
.entries
!= 0x0f) && /* older (Neptune) boards */
1385 (reg_01
.bits
.entries
!= 0x17) && /* typical ISA+PCI boards */
1386 (reg_01
.bits
.entries
!= 0x1b) && /* Compaq Proliant boards */
1387 (reg_01
.bits
.entries
!= 0x1f) && /* dual Xeon boards */
1388 (reg_01
.bits
.entries
!= 0x22) && /* bigger Xeon boards */
1389 (reg_01
.bits
.entries
!= 0x2E) &&
1390 (reg_01
.bits
.entries
!= 0x3F)
1392 UNEXPECTED_IO_APIC();
1394 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1395 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1396 if ( (reg_01
.bits
.version
!= 0x01) && /* 82489DX IO-APICs */
1397 (reg_01
.bits
.version
!= 0x10) && /* oldest IO-APICs */
1398 (reg_01
.bits
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
1399 (reg_01
.bits
.version
!= 0x13) && /* Xeon IO-APICs */
1400 (reg_01
.bits
.version
!= 0x20) /* Intel P64H (82806 AA) */
1402 UNEXPECTED_IO_APIC();
1403 if (reg_01
.bits
.__reserved_1
|| reg_01
.bits
.__reserved_2
)
1404 UNEXPECTED_IO_APIC();
1407 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1408 * but the value of reg_02 is read as the previous read register
1409 * value, so ignore it if reg_02 == reg_01.
1411 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1412 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1413 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1414 if (reg_02
.bits
.__reserved_1
|| reg_02
.bits
.__reserved_2
)
1415 UNEXPECTED_IO_APIC();
1419 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1420 * or reg_03, but the value of reg_0[23] is read as the previous read
1421 * register value, so ignore it if reg_03 == reg_0[12].
1423 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1424 reg_03
.raw
!= reg_01
.raw
) {
1425 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1426 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1427 if (reg_03
.bits
.__reserved_1
)
1428 UNEXPECTED_IO_APIC();
1431 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1433 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1434 " Stat Dest Deli Vect: \n");
1436 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1437 struct IO_APIC_route_entry entry
;
1439 spin_lock_irqsave(&ioapic_lock
, flags
);
1440 *(((int *)&entry
)+0) = io_apic_read(apic
, 0x10+i
*2);
1441 *(((int *)&entry
)+1) = io_apic_read(apic
, 0x11+i
*2);
1442 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1444 printk(KERN_DEBUG
" %02x %03X %02X ",
1446 entry
.dest
.logical
.logical_dest
,
1447 entry
.dest
.physical
.physical_dest
1450 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1455 entry
.delivery_status
,
1457 entry
.delivery_mode
,
1462 if (use_pci_vector())
1463 printk(KERN_INFO
"Using vector-based indexing\n");
1464 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1465 for (i
= 0; i
< NR_IRQS
; i
++) {
1466 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1469 if (use_pci_vector() && !platform_legacy_irq(i
))
1470 printk(KERN_DEBUG
"IRQ%d ", IO_APIC_VECTOR(i
));
1472 printk(KERN_DEBUG
"IRQ%d ", i
);
1474 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1477 entry
= irq_2_pin
+ entry
->next
;
1482 printk(KERN_INFO
".................................... done.\n");
1489 static void print_APIC_bitfield (int base
)
1494 if (apic_verbosity
== APIC_QUIET
)
1497 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1498 for (i
= 0; i
< 8; i
++) {
1499 v
= apic_read(base
+ i
*0x10);
1500 for (j
= 0; j
< 32; j
++) {
1510 void /*__init*/ print_local_APIC(void * dummy
)
1512 unsigned int v
, ver
, maxlvt
;
1514 if (apic_verbosity
== APIC_QUIET
)
1517 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1518 smp_processor_id(), hard_smp_processor_id());
1519 v
= apic_read(APIC_ID
);
1520 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1521 v
= apic_read(APIC_LVR
);
1522 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1523 ver
= GET_APIC_VERSION(v
);
1524 maxlvt
= get_maxlvt();
1526 v
= apic_read(APIC_TASKPRI
);
1527 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1529 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1530 v
= apic_read(APIC_ARBPRI
);
1531 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1532 v
& APIC_ARBPRI_MASK
);
1533 v
= apic_read(APIC_PROCPRI
);
1534 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1537 v
= apic_read(APIC_EOI
);
1538 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1539 v
= apic_read(APIC_RRR
);
1540 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1541 v
= apic_read(APIC_LDR
);
1542 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1543 v
= apic_read(APIC_DFR
);
1544 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1545 v
= apic_read(APIC_SPIV
);
1546 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1548 printk(KERN_DEBUG
"... APIC ISR field:\n");
1549 print_APIC_bitfield(APIC_ISR
);
1550 printk(KERN_DEBUG
"... APIC TMR field:\n");
1551 print_APIC_bitfield(APIC_TMR
);
1552 printk(KERN_DEBUG
"... APIC IRR field:\n");
1553 print_APIC_bitfield(APIC_IRR
);
1555 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1556 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1557 apic_write(APIC_ESR
, 0);
1558 v
= apic_read(APIC_ESR
);
1559 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1562 v
= apic_read(APIC_ICR
);
1563 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1564 v
= apic_read(APIC_ICR2
);
1565 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1567 v
= apic_read(APIC_LVTT
);
1568 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1570 if (maxlvt
> 3) { /* PC is LVT#4. */
1571 v
= apic_read(APIC_LVTPC
);
1572 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1574 v
= apic_read(APIC_LVT0
);
1575 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1576 v
= apic_read(APIC_LVT1
);
1577 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1579 if (maxlvt
> 2) { /* ERR is LVT#3. */
1580 v
= apic_read(APIC_LVTERR
);
1581 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1584 v
= apic_read(APIC_TMICT
);
1585 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1586 v
= apic_read(APIC_TMCCT
);
1587 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1588 v
= apic_read(APIC_TDCR
);
1589 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1593 void print_all_local_APICs (void)
1595 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1598 void /*__init*/ print_PIC(void)
1601 unsigned long flags
;
1603 if (apic_verbosity
== APIC_QUIET
)
1606 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1608 spin_lock_irqsave(&i8259A_lock
, flags
);
1610 v
= inb(0xa1) << 8 | inb(0x21);
1611 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1613 v
= inb(0xa0) << 8 | inb(0x20);
1614 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1618 v
= inb(0xa0) << 8 | inb(0x20);
1622 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1624 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1626 v
= inb(0x4d1) << 8 | inb(0x4d0);
1627 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1632 static void __init
enable_IO_APIC(void)
1634 union IO_APIC_reg_01 reg_01
;
1635 int i8259_apic
, i8259_pin
;
1637 unsigned long flags
;
1639 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1640 irq_2_pin
[i
].pin
= -1;
1641 irq_2_pin
[i
].next
= 0;
1644 for (i
= 0; i
< MAX_PIRQS
; i
++)
1645 pirq_entries
[i
] = -1;
1648 * The number of IO-APIC IRQ registers (== #pins):
1650 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1651 spin_lock_irqsave(&ioapic_lock
, flags
);
1652 reg_01
.raw
= io_apic_read(apic
, 1);
1653 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1654 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1656 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1658 /* See if any of the pins is in ExtINT mode */
1659 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1660 struct IO_APIC_route_entry entry
;
1661 spin_lock_irqsave(&ioapic_lock
, flags
);
1662 *(((int *)&entry
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
1663 *(((int *)&entry
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
1664 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1667 /* If the interrupt line is enabled and in ExtInt mode
1668 * I have found the pin where the i8259 is connected.
1670 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1671 ioapic_i8259
.apic
= apic
;
1672 ioapic_i8259
.pin
= pin
;
1678 /* Look to see what if the MP table has reported the ExtINT */
1679 /* If we could not find the appropriate pin by looking at the ioapic
1680 * the i8259 probably is not connected the ioapic but give the
1681 * mptable a chance anyway.
1683 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1684 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1685 /* Trust the MP table if nothing is setup in the hardware */
1686 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1687 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1688 ioapic_i8259
.pin
= i8259_pin
;
1689 ioapic_i8259
.apic
= i8259_apic
;
1691 /* Complain if the MP table and the hardware disagree */
1692 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1693 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1695 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1699 * Do not trust the IO-APIC being empty at bootup
1705 * Not an __init, needed by the reboot code
1707 void disable_IO_APIC(void)
1710 * Clear the IO-APIC before rebooting:
1715 * If the i8259 is routed through an IOAPIC
1716 * Put that IOAPIC in virtual wire mode
1717 * so legacy interrupts can be delivered.
1719 if (ioapic_i8259
.pin
!= -1) {
1720 struct IO_APIC_route_entry entry
;
1721 unsigned long flags
;
1723 memset(&entry
, 0, sizeof(entry
));
1724 entry
.mask
= 0; /* Enabled */
1725 entry
.trigger
= 0; /* Edge */
1727 entry
.polarity
= 0; /* High */
1728 entry
.delivery_status
= 0;
1729 entry
.dest_mode
= 0; /* Physical */
1730 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1732 entry
.dest
.physical
.physical_dest
=
1733 GET_APIC_ID(apic_read(APIC_ID
));
1736 * Add it to the IO-APIC irq-routing table:
1738 spin_lock_irqsave(&ioapic_lock
, flags
);
1739 io_apic_write(ioapic_i8259
.apic
, 0x11+2*ioapic_i8259
.pin
,
1740 *(((int *)&entry
)+1));
1741 io_apic_write(ioapic_i8259
.apic
, 0x10+2*ioapic_i8259
.pin
,
1742 *(((int *)&entry
)+0));
1743 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1745 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1749 * function to set the IO-APIC physical IDs based on the
1750 * values stored in the MPC table.
1752 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1755 #ifndef CONFIG_X86_NUMAQ
1756 static void __init
setup_ioapic_ids_from_mpc(void)
1758 union IO_APIC_reg_00 reg_00
;
1759 physid_mask_t phys_id_present_map
;
1762 unsigned char old_id
;
1763 unsigned long flags
;
1766 * Don't check I/O APIC IDs for xAPIC systems. They have
1767 * no meaning without the serial APIC bus.
1769 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1770 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1773 * This is broken; anything with a real cpu count has to
1774 * circumvent this idiocy regardless.
1776 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1779 * Set the IOAPIC ID to the value stored in the MPC table.
1781 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1783 /* Read the register 0 value */
1784 spin_lock_irqsave(&ioapic_lock
, flags
);
1785 reg_00
.raw
= io_apic_read(apic
, 0);
1786 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1788 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1790 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1791 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1792 apic
, mp_ioapics
[apic
].mpc_apicid
);
1793 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1795 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1799 * Sanity check, is the ID really free? Every APIC in a
1800 * system must have a unique ID or we get lots of nice
1801 * 'stuck on smp_invalidate_needed IPI wait' messages.
1803 if (check_apicid_used(phys_id_present_map
,
1804 mp_ioapics
[apic
].mpc_apicid
)) {
1805 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1806 apic
, mp_ioapics
[apic
].mpc_apicid
);
1807 for (i
= 0; i
< get_physical_broadcast(); i
++)
1808 if (!physid_isset(i
, phys_id_present_map
))
1810 if (i
>= get_physical_broadcast())
1811 panic("Max APIC ID exceeded!\n");
1812 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1814 physid_set(i
, phys_id_present_map
);
1815 mp_ioapics
[apic
].mpc_apicid
= i
;
1818 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1819 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1820 "phys_id_present_map\n",
1821 mp_ioapics
[apic
].mpc_apicid
);
1822 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1827 * We need to adjust the IRQ routing table
1828 * if the ID changed.
1830 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1831 for (i
= 0; i
< mp_irq_entries
; i
++)
1832 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1833 mp_irqs
[i
].mpc_dstapic
1834 = mp_ioapics
[apic
].mpc_apicid
;
1837 * Read the right value from the MPC table and
1838 * write it into the ID register.
1840 apic_printk(APIC_VERBOSE
, KERN_INFO
1841 "...changing IO-APIC physical APIC ID to %d ...",
1842 mp_ioapics
[apic
].mpc_apicid
);
1844 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1845 spin_lock_irqsave(&ioapic_lock
, flags
);
1846 io_apic_write(apic
, 0, reg_00
.raw
);
1847 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1852 spin_lock_irqsave(&ioapic_lock
, flags
);
1853 reg_00
.raw
= io_apic_read(apic
, 0);
1854 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1855 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1856 printk("could not set ID!\n");
1858 apic_printk(APIC_VERBOSE
, " ok.\n");
1862 static void __init
setup_ioapic_ids_from_mpc(void) { }
1866 * There is a nasty bug in some older SMP boards, their mptable lies
1867 * about the timer IRQ. We do the following to work around the situation:
1869 * - timer IRQ defaults to IO-APIC IRQ
1870 * - if this function detects that timer IRQs are defunct, then we fall
1871 * back to ISA timer IRQs
1873 static int __init
timer_irq_works(void)
1875 unsigned long t1
= jiffies
;
1878 /* Let ten ticks pass... */
1879 mdelay((10 * 1000) / HZ
);
1882 * Expect a few ticks at least, to be sure some possible
1883 * glue logic does not lock up after one or two first
1884 * ticks in a non-ExtINT mode. Also the local APIC
1885 * might have cached one ExtINT interrupt. Finally, at
1886 * least one tick may be lost due to delays.
1888 if (jiffies
- t1
> 4)
1895 * In the SMP+IOAPIC case it might happen that there are an unspecified
1896 * number of pending IRQ events unhandled. These cases are very rare,
1897 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1898 * better to do it this way as thus we do not have to be aware of
1899 * 'pending' interrupts in the IRQ path, except at this point.
1902 * Edge triggered needs to resend any interrupt
1903 * that was delayed but this is now handled in the device
1908 * Starting up a edge-triggered IO-APIC interrupt is
1909 * nasty - we need to make sure that we get the edge.
1910 * If it is already asserted for some reason, we need
1911 * return 1 to indicate that is was pending.
1913 * This is not complete - we should be able to fake
1914 * an edge even if it isn't on the 8259A...
1916 static unsigned int startup_edge_ioapic_irq(unsigned int irq
)
1918 int was_pending
= 0;
1919 unsigned long flags
;
1921 spin_lock_irqsave(&ioapic_lock
, flags
);
1923 disable_8259A_irq(irq
);
1924 if (i8259A_irq_pending(irq
))
1927 __unmask_IO_APIC_irq(irq
);
1928 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1934 * Once we have recorded IRQ_PENDING already, we can mask the
1935 * interrupt for real. This prevents IRQ storms from unhandled
1938 static void ack_edge_ioapic_irq(unsigned int irq
)
1941 if ((irq_desc
[irq
].status
& (IRQ_PENDING
| IRQ_DISABLED
))
1942 == (IRQ_PENDING
| IRQ_DISABLED
))
1943 mask_IO_APIC_irq(irq
);
1948 * Level triggered interrupts can just be masked,
1949 * and shutting down and starting up the interrupt
1950 * is the same as enabling and disabling them -- except
1951 * with a startup need to return a "was pending" value.
1953 * Level triggered interrupts are special because we
1954 * do not touch any IO-APIC register while handling
1955 * them. We ack the APIC in the end-IRQ handler, not
1956 * in the start-IRQ-handler. Protection against reentrance
1957 * from the same interrupt is still provided, both by the
1958 * generic IRQ layer and by the fact that an unacked local
1959 * APIC does not accept IRQs.
1961 static unsigned int startup_level_ioapic_irq (unsigned int irq
)
1963 unmask_IO_APIC_irq(irq
);
1965 return 0; /* don't check for pending */
1968 static void end_level_ioapic_irq (unsigned int irq
)
1975 * It appears there is an erratum which affects at least version 0x11
1976 * of I/O APIC (that's the 82093AA and cores integrated into various
1977 * chipsets). Under certain conditions a level-triggered interrupt is
1978 * erroneously delivered as edge-triggered one but the respective IRR
1979 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1980 * message but it will never arrive and further interrupts are blocked
1981 * from the source. The exact reason is so far unknown, but the
1982 * phenomenon was observed when two consecutive interrupt requests
1983 * from a given source get delivered to the same CPU and the source is
1984 * temporarily disabled in between.
1986 * A workaround is to simulate an EOI message manually. We achieve it
1987 * by setting the trigger mode to edge and then to level when the edge
1988 * trigger mode gets detected in the TMR of a local APIC for a
1989 * level-triggered interrupt. We mask the source for the time of the
1990 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1991 * The idea is from Manfred Spraul. --macro
1993 i
= IO_APIC_VECTOR(irq
);
1995 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1999 if (!(v
& (1 << (i
& 0x1f)))) {
2000 atomic_inc(&irq_mis_count
);
2001 spin_lock(&ioapic_lock
);
2002 __mask_and_edge_IO_APIC_irq(irq
);
2003 __unmask_and_level_IO_APIC_irq(irq
);
2004 spin_unlock(&ioapic_lock
);
2008 #ifdef CONFIG_PCI_MSI
2009 static unsigned int startup_edge_ioapic_vector(unsigned int vector
)
2011 int irq
= vector_to_irq(vector
);
2013 return startup_edge_ioapic_irq(irq
);
2016 static void ack_edge_ioapic_vector(unsigned int vector
)
2018 int irq
= vector_to_irq(vector
);
2020 move_native_irq(vector
);
2021 ack_edge_ioapic_irq(irq
);
2024 static unsigned int startup_level_ioapic_vector (unsigned int vector
)
2026 int irq
= vector_to_irq(vector
);
2028 return startup_level_ioapic_irq (irq
);
2031 static void end_level_ioapic_vector (unsigned int vector
)
2033 int irq
= vector_to_irq(vector
);
2035 move_native_irq(vector
);
2036 end_level_ioapic_irq(irq
);
2039 static void mask_IO_APIC_vector (unsigned int vector
)
2041 int irq
= vector_to_irq(vector
);
2043 mask_IO_APIC_irq(irq
);
2046 static void unmask_IO_APIC_vector (unsigned int vector
)
2048 int irq
= vector_to_irq(vector
);
2050 unmask_IO_APIC_irq(irq
);
2054 static void set_ioapic_affinity_vector (unsigned int vector
,
2057 int irq
= vector_to_irq(vector
);
2059 set_native_irq_info(vector
, cpu_mask
);
2060 set_ioapic_affinity_irq(irq
, cpu_mask
);
2066 * Level and edge triggered IO-APIC interrupts need different handling,
2067 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2068 * handled with the level-triggered descriptor, but that one has slightly
2069 * more overhead. Level-triggered interrupts cannot be handled with the
2070 * edge-triggered handler, without risking IRQ storms and other ugly
2073 static struct hw_interrupt_type ioapic_edge_type __read_mostly
= {
2074 .typename
= "IO-APIC-edge",
2075 .startup
= startup_edge_ioapic
,
2076 .shutdown
= shutdown_edge_ioapic
,
2077 .enable
= enable_edge_ioapic
,
2078 .disable
= disable_edge_ioapic
,
2079 .ack
= ack_edge_ioapic
,
2080 .end
= end_edge_ioapic
,
2082 .set_affinity
= set_ioapic_affinity
,
2086 static struct hw_interrupt_type ioapic_level_type __read_mostly
= {
2087 .typename
= "IO-APIC-level",
2088 .startup
= startup_level_ioapic
,
2089 .shutdown
= shutdown_level_ioapic
,
2090 .enable
= enable_level_ioapic
,
2091 .disable
= disable_level_ioapic
,
2092 .ack
= mask_and_ack_level_ioapic
,
2093 .end
= end_level_ioapic
,
2095 .set_affinity
= set_ioapic_affinity
,
2099 static inline void init_IO_APIC_traps(void)
2104 * NOTE! The local APIC isn't very good at handling
2105 * multiple interrupts at the same interrupt level.
2106 * As the interrupt level is determined by taking the
2107 * vector number and shifting that right by 4, we
2108 * want to spread these out a bit so that they don't
2109 * all fall in the same interrupt level.
2111 * Also, we've got to be careful not to trash gate
2112 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2114 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
2116 if (use_pci_vector()) {
2117 if (!platform_legacy_irq(tmp
))
2118 if ((tmp
= vector_to_irq(tmp
)) == -1)
2121 if (IO_APIC_IRQ(tmp
) && !IO_APIC_VECTOR(tmp
)) {
2123 * Hmm.. We don't have an entry for this,
2124 * so default to an old-fashioned 8259
2125 * interrupt if we can..
2128 make_8259A_irq(irq
);
2130 /* Strange. Oh, well.. */
2131 irq_desc
[irq
].handler
= &no_irq_type
;
2136 static void enable_lapic_irq (unsigned int irq
)
2140 v
= apic_read(APIC_LVT0
);
2141 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2144 static void disable_lapic_irq (unsigned int irq
)
2148 v
= apic_read(APIC_LVT0
);
2149 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2152 static void ack_lapic_irq (unsigned int irq
)
2157 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
2159 static struct hw_interrupt_type lapic_irq_type __read_mostly
= {
2160 .typename
= "local-APIC-edge",
2161 .startup
= NULL
, /* startup_irq() not used for IRQ0 */
2162 .shutdown
= NULL
, /* shutdown_irq() not used for IRQ0 */
2163 .enable
= enable_lapic_irq
,
2164 .disable
= disable_lapic_irq
,
2165 .ack
= ack_lapic_irq
,
2166 .end
= end_lapic_irq
2169 static void setup_nmi (void)
2172 * Dirty trick to enable the NMI watchdog ...
2173 * We put the 8259A master into AEOI mode and
2174 * unmask on all local APICs LVT0 as NMI.
2176 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2177 * is from Maciej W. Rozycki - so we do not have to EOI from
2178 * the NMI handler or the timer interrupt.
2180 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2182 on_each_cpu(enable_NMI_through_LVT0
, NULL
, 1, 1);
2184 apic_printk(APIC_VERBOSE
, " done.\n");
2188 * This looks a bit hackish but it's about the only one way of sending
2189 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2190 * not support the ExtINT mode, unfortunately. We need to send these
2191 * cycles as some i82489DX-based boards have glue logic that keeps the
2192 * 8259A interrupt line asserted until INTA. --macro
2194 static inline void unlock_ExtINT_logic(void)
2197 struct IO_APIC_route_entry entry0
, entry1
;
2198 unsigned char save_control
, save_freq_select
;
2199 unsigned long flags
;
2201 pin
= find_isa_irq_pin(8, mp_INT
);
2202 apic
= find_isa_irq_apic(8, mp_INT
);
2206 spin_lock_irqsave(&ioapic_lock
, flags
);
2207 *(((int *)&entry0
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
2208 *(((int *)&entry0
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
2209 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2210 clear_IO_APIC_pin(apic
, pin
);
2212 memset(&entry1
, 0, sizeof(entry1
));
2214 entry1
.dest_mode
= 0; /* physical delivery */
2215 entry1
.mask
= 0; /* unmask IRQ now */
2216 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2217 entry1
.delivery_mode
= dest_ExtINT
;
2218 entry1
.polarity
= entry0
.polarity
;
2222 spin_lock_irqsave(&ioapic_lock
, flags
);
2223 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry1
) + 1));
2224 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry1
) + 0));
2225 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2227 save_control
= CMOS_READ(RTC_CONTROL
);
2228 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2229 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2231 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2236 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2240 CMOS_WRITE(save_control
, RTC_CONTROL
);
2241 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2242 clear_IO_APIC_pin(apic
, pin
);
2244 spin_lock_irqsave(&ioapic_lock
, flags
);
2245 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry0
) + 1));
2246 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry0
) + 0));
2247 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2250 int timer_uses_ioapic_pin_0
;
2253 * This code may look a bit paranoid, but it's supposed to cooperate with
2254 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2255 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2256 * fanatically on his truly buggy board.
2258 static inline void check_timer(void)
2260 int apic1
, pin1
, apic2
, pin2
;
2264 * get/set the timer IRQ vector:
2266 disable_8259A_irq(0);
2267 vector
= assign_irq_vector(0);
2268 set_intr_gate(vector
, interrupt
[0]);
2271 * Subtle, code in do_timer_interrupt() expects an AEOI
2272 * mode for the 8259A whenever interrupts are routed
2273 * through I/O APICs. Also IRQ0 has to be enabled in
2274 * the 8259A which implies the virtual wire has to be
2275 * disabled in the local APIC.
2277 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2280 if (timer_over_8254
> 0)
2281 enable_8259A_irq(0);
2283 pin1
= find_isa_irq_pin(0, mp_INT
);
2284 apic1
= find_isa_irq_apic(0, mp_INT
);
2285 pin2
= ioapic_i8259
.pin
;
2286 apic2
= ioapic_i8259
.apic
;
2289 timer_uses_ioapic_pin_0
= 1;
2291 printk(KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2292 vector
, apic1
, pin1
, apic2
, pin2
);
2296 * Ok, does IRQ0 through the IOAPIC work?
2298 unmask_IO_APIC_irq(0);
2299 if (timer_irq_works()) {
2300 if (nmi_watchdog
== NMI_IO_APIC
) {
2301 disable_8259A_irq(0);
2303 enable_8259A_irq(0);
2305 if (disable_timer_pin_1
> 0)
2306 clear_IO_APIC_pin(0, pin1
);
2309 clear_IO_APIC_pin(apic1
, pin1
);
2310 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to "
2314 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2316 printk("\n..... (found pin %d) ...", pin2
);
2318 * legacy devices should be connected to IO APIC #0
2320 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
2321 if (timer_irq_works()) {
2324 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2326 add_pin_to_irq(0, apic2
, pin2
);
2327 if (nmi_watchdog
== NMI_IO_APIC
) {
2333 * Cleanup, just in case ...
2335 clear_IO_APIC_pin(apic2
, pin2
);
2337 printk(" failed.\n");
2339 if (nmi_watchdog
== NMI_IO_APIC
) {
2340 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2344 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2346 disable_8259A_irq(0);
2347 irq_desc
[0].handler
= &lapic_irq_type
;
2348 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2349 enable_8259A_irq(0);
2351 if (timer_irq_works()) {
2352 printk(" works.\n");
2355 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2356 printk(" failed.\n");
2358 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2363 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2365 unlock_ExtINT_logic();
2367 if (timer_irq_works()) {
2368 printk(" works.\n");
2371 printk(" failed :(.\n");
2372 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2373 "report. Then try booting with the 'noapic' option");
2378 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2379 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2380 * Linux doesn't really care, as it's not actually used
2381 * for any interrupt handling anyway.
2383 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2385 void __init
setup_IO_APIC(void)
2390 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2392 io_apic_irqs
= ~PIC_IRQS
;
2394 printk("ENABLING IO-APIC IRQs\n");
2397 * Set up IO-APIC IRQ routing.
2400 setup_ioapic_ids_from_mpc();
2402 setup_IO_APIC_irqs();
2403 init_IO_APIC_traps();
2409 static int __init
setup_disable_8254_timer(char *s
)
2411 timer_over_8254
= -1;
2414 static int __init
setup_enable_8254_timer(char *s
)
2416 timer_over_8254
= 2;
2420 __setup("disable_8254_timer", setup_disable_8254_timer
);
2421 __setup("enable_8254_timer", setup_enable_8254_timer
);
2424 * Called after all the initialization is done. If we didnt find any
2425 * APIC bugs then we can allow the modify fast path
2428 static int __init
io_apic_bug_finalize(void)
2430 if(sis_apic_bug
== -1)
2435 late_initcall(io_apic_bug_finalize
);
2437 struct sysfs_ioapic_data
{
2438 struct sys_device dev
;
2439 struct IO_APIC_route_entry entry
[0];
2441 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2443 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2445 struct IO_APIC_route_entry
*entry
;
2446 struct sysfs_ioapic_data
*data
;
2447 unsigned long flags
;
2450 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2451 entry
= data
->entry
;
2452 spin_lock_irqsave(&ioapic_lock
, flags
);
2453 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ ) {
2454 *(((int *)entry
) + 1) = io_apic_read(dev
->id
, 0x11 + 2 * i
);
2455 *(((int *)entry
) + 0) = io_apic_read(dev
->id
, 0x10 + 2 * i
);
2457 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2462 static int ioapic_resume(struct sys_device
*dev
)
2464 struct IO_APIC_route_entry
*entry
;
2465 struct sysfs_ioapic_data
*data
;
2466 unsigned long flags
;
2467 union IO_APIC_reg_00 reg_00
;
2470 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2471 entry
= data
->entry
;
2473 spin_lock_irqsave(&ioapic_lock
, flags
);
2474 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2475 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2476 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2477 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2479 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ ) {
2480 io_apic_write(dev
->id
, 0x11+2*i
, *(((int *)entry
)+1));
2481 io_apic_write(dev
->id
, 0x10+2*i
, *(((int *)entry
)+0));
2483 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2488 static struct sysdev_class ioapic_sysdev_class
= {
2489 set_kset_name("ioapic"),
2490 .suspend
= ioapic_suspend
,
2491 .resume
= ioapic_resume
,
2494 static int __init
ioapic_init_sysfs(void)
2496 struct sys_device
* dev
;
2497 int i
, size
, error
= 0;
2499 error
= sysdev_class_register(&ioapic_sysdev_class
);
2503 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2504 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2505 * sizeof(struct IO_APIC_route_entry
);
2506 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2507 if (!mp_ioapic_data
[i
]) {
2508 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2511 memset(mp_ioapic_data
[i
], 0, size
);
2512 dev
= &mp_ioapic_data
[i
]->dev
;
2514 dev
->cls
= &ioapic_sysdev_class
;
2515 error
= sysdev_register(dev
);
2517 kfree(mp_ioapic_data
[i
]);
2518 mp_ioapic_data
[i
] = NULL
;
2519 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2527 device_initcall(ioapic_init_sysfs
);
2529 /* --------------------------------------------------------------------------
2530 ACPI-based IOAPIC Configuration
2531 -------------------------------------------------------------------------- */
2535 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2537 union IO_APIC_reg_00 reg_00
;
2538 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2540 unsigned long flags
;
2544 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2545 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2546 * supports up to 16 on one shared APIC bus.
2548 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2549 * advantage of new APIC bus architecture.
2552 if (physids_empty(apic_id_map
))
2553 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2555 spin_lock_irqsave(&ioapic_lock
, flags
);
2556 reg_00
.raw
= io_apic_read(ioapic
, 0);
2557 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2559 if (apic_id
>= get_physical_broadcast()) {
2560 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2561 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2562 apic_id
= reg_00
.bits
.ID
;
2566 * Every APIC in a system must have a unique ID or we get lots of nice
2567 * 'stuck on smp_invalidate_needed IPI wait' messages.
2569 if (check_apicid_used(apic_id_map
, apic_id
)) {
2571 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2572 if (!check_apicid_used(apic_id_map
, i
))
2576 if (i
== get_physical_broadcast())
2577 panic("Max apic_id exceeded!\n");
2579 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2580 "trying %d\n", ioapic
, apic_id
, i
);
2585 tmp
= apicid_to_cpu_present(apic_id
);
2586 physids_or(apic_id_map
, apic_id_map
, tmp
);
2588 if (reg_00
.bits
.ID
!= apic_id
) {
2589 reg_00
.bits
.ID
= apic_id
;
2591 spin_lock_irqsave(&ioapic_lock
, flags
);
2592 io_apic_write(ioapic
, 0, reg_00
.raw
);
2593 reg_00
.raw
= io_apic_read(ioapic
, 0);
2594 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2597 if (reg_00
.bits
.ID
!= apic_id
) {
2598 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2603 apic_printk(APIC_VERBOSE
, KERN_INFO
2604 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2610 int __init
io_apic_get_version (int ioapic
)
2612 union IO_APIC_reg_01 reg_01
;
2613 unsigned long flags
;
2615 spin_lock_irqsave(&ioapic_lock
, flags
);
2616 reg_01
.raw
= io_apic_read(ioapic
, 1);
2617 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2619 return reg_01
.bits
.version
;
2623 int __init
io_apic_get_redir_entries (int ioapic
)
2625 union IO_APIC_reg_01 reg_01
;
2626 unsigned long flags
;
2628 spin_lock_irqsave(&ioapic_lock
, flags
);
2629 reg_01
.raw
= io_apic_read(ioapic
, 1);
2630 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2632 return reg_01
.bits
.entries
;
2636 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2638 struct IO_APIC_route_entry entry
;
2639 unsigned long flags
;
2641 if (!IO_APIC_IRQ(irq
)) {
2642 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2648 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2649 * Note that we mask (disable) IRQs now -- these get enabled when the
2650 * corresponding device driver registers for this IRQ.
2653 memset(&entry
,0,sizeof(entry
));
2655 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2656 entry
.dest_mode
= INT_DEST_MODE
;
2657 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2658 entry
.trigger
= edge_level
;
2659 entry
.polarity
= active_high_low
;
2663 * IRQs < 16 are already in the irq_2_pin[] map
2666 add_pin_to_irq(irq
, ioapic
, pin
);
2668 entry
.vector
= assign_irq_vector(irq
);
2670 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2671 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2672 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2673 edge_level
, active_high_low
);
2675 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2677 if (!ioapic
&& (irq
< 16))
2678 disable_8259A_irq(irq
);
2680 spin_lock_irqsave(&ioapic_lock
, flags
);
2681 io_apic_write(ioapic
, 0x11+2*pin
, *(((int *)&entry
)+1));
2682 io_apic_write(ioapic
, 0x10+2*pin
, *(((int *)&entry
)+0));
2683 set_native_irq_info(use_pci_vector() ? entry
.vector
: irq
, TARGET_CPUS
);
2684 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2689 #endif /* CONFIG_ACPI */