arch/i386/kernel/nmi.c

   1 /*
   2  *  linux/arch/i386/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Mikael Pettersson   : Pentium 4 support for local APIC NMI watchdog.
  12  *  Pavel Machek and
  13  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/nmi.h>
  21 #include <linux/sysdev.h>
  22 #include <linux/sysctl.h>
  23 #include <linux/percpu.h>
  24
  25 #include <asm/smp.h>
  26 #include <asm/nmi.h>
  27 #include <asm/intel_arch_perfmon.h>
  28
  29 #include "mach_traps.h"
  30
  31 unsigned int nmi_watchdog = NMI_NONE;
  32 extern int unknown_nmi_panic;
  33 static unsigned int nmi_hz = HZ;
  34 static unsigned int nmi_perfctr_msr;    /* the MSR to reset in NMI handler */
  35 static unsigned int nmi_p4_cccr_val;
  36 extern void show_registers(struct pt_regs *regs);
  37
  38 /*
  39  * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
  40  * - it may be reserved by some other driver, or not
  41  * - when not reserved by some other driver, it may be used for
  42  *   the NMI watchdog, or not
  43  *
  44  * This is maintained separately from nmi_active because the NMI
  45  * watchdog may also be driven from the I/O APIC timer.
  46  */
  47 static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
  48 static unsigned int lapic_nmi_owner;
  49 #define LAPIC_NMI_WATCHDOG      (1<<0)
  50 #define LAPIC_NMI_RESERVED      (1<<1)
  51
  52 /* nmi_active:
  53  * +1: the lapic NMI watchdog is active, but can be disabled
  54  *  0: the lapic NMI watchdog has not been set up, and cannot
  55  *     be enabled
  56  * -1: the lapic NMI watchdog is disabled, but can be enabled
  57  */
  58 int nmi_active;
  59
  60 #define K7_EVNTSEL_ENABLE       (1 << 22)
  61 #define K7_EVNTSEL_INT          (1 << 20)
  62 #define K7_EVNTSEL_OS           (1 << 17)
  63 #define K7_EVNTSEL_USR          (1 << 16)
  64 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
  65 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
  66
  67 #define P6_EVNTSEL0_ENABLE      (1 << 22)
  68 #define P6_EVNTSEL_INT          (1 << 20)
  69 #define P6_EVNTSEL_OS           (1 << 17)
  70 #define P6_EVNTSEL_USR          (1 << 16)
  71 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED  0x79
  72 #define P6_NMI_EVENT            P6_EVENT_CPU_CLOCKS_NOT_HALTED
  73
  74 #define MSR_P4_MISC_ENABLE      0x1A0
  75 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
  76 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
  77 #define MSR_P4_PERFCTR0         0x300
  78 #define MSR_P4_CCCR0            0x360
  79 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
  80 #define P4_ESCR_OS              (1<<3)
  81 #define P4_ESCR_USR             (1<<2)
  82 #define P4_CCCR_OVF_PMI0        (1<<26)
  83 #define P4_CCCR_OVF_PMI1        (1<<27)
  84 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
  85 #define P4_CCCR_COMPLEMENT      (1<<19)
  86 #define P4_CCCR_COMPARE         (1<<18)
  87 #define P4_CCCR_REQUIRED        (3<<16)
  88 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
  89 #define P4_CCCR_ENABLE          (1<<12)
  90 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
  91    CRU_ESCR0 (with any non-null event selector) through a complemented
  92    max threshold. [IA32-Vol3, Section 14.9.9] */
  93 #define MSR_P4_IQ_COUNTER0      0x30C
  94 #define P4_NMI_CRU_ESCR0        (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
  95 #define P4_NMI_IQ_CCCR0 \
  96         (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT|     \
  97          P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
  98
  99 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
 100 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
 101
 102 #ifdef CONFIG_SMP
 103 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 104  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 105  * CPUs during the test make them busy.
 106  */
 107 static __init void nmi_cpu_busy(void *data)
 108 {
 109         volatile int *endflag = data;
 110         local_irq_enable_in_hardirq();
 111         /* Intentionally don't use cpu_relax here. This is
 112            to make sure that the performance counter really ticks,
 113            even if there is a simulator or similar that catches the
 114            pause instruction. On a real HT machine this is fine because
 115            all other CPUs are busy with "useless" delay loops and don't
 116            care if they get somewhat less cycles. */
 117         while (*endflag == 0)
 118                 barrier();
 119 }
 120 #endif
 121
 122 static int __init check_nmi_watchdog(void)
 123 {
 124         volatile int endflag = 0;
 125         unsigned int *prev_nmi_count;
 126         int cpu;
 127
 128         if (nmi_watchdog == NMI_NONE)
 129                 return 0;
 130
 131         prev_nmi_count = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 132         if (!prev_nmi_count)
 133                 return -1;
 134
 135         printk(KERN_INFO "Testing NMI watchdog ... ");
 136
 137         if (nmi_watchdog == NMI_LOCAL_APIC)
 138                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 139
 140         for_each_possible_cpu(cpu)
 141                 prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
 142         local_irq_enable();
 143         mdelay((10*1000)/nmi_hz); // wait 10 ticks
 144
 145         for_each_possible_cpu(cpu) {
 146 #ifdef CONFIG_SMP
 147                 /* Check cpu_callin_map here because that is set
 148                    after the timer is started. */
 149                 if (!cpu_isset(cpu, cpu_callin_map))
 150                         continue;
 151 #endif
 152                 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
 153                         endflag = 1;
 154                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 155                                 cpu,
 156                                 prev_nmi_count[cpu],
 157                                 nmi_count(cpu));
 158                         nmi_active = 0;
 159                         lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
 160                         kfree(prev_nmi_count);
 161                         return -1;
 162                 }
 163         }
 164         endflag = 1;
 165         printk("OK.\n");
 166
 167         /* now that we know it works we can reduce NMI frequency to
 168            something more reasonable; makes a difference in some configs */
 169         if (nmi_watchdog == NMI_LOCAL_APIC)
 170                 nmi_hz = 1;
 171
 172         kfree(prev_nmi_count);
 173         return 0;
 174 }
 175 /* This needs to happen later in boot so counters are working */
 176 late_initcall(check_nmi_watchdog);
 177
 178 static int __init setup_nmi_watchdog(char *str)
 179 {
 180         int nmi;
 181
 182         get_option(&str, &nmi);
 183
 184         if (nmi >= NMI_INVALID)
 185                 return 0;
 186         if (nmi == NMI_NONE)
 187                 nmi_watchdog = nmi;
 188         /*
 189          * If any other x86 CPU has a local APIC, then
 190          * please test the NMI stuff there and send me the
 191          * missing bits. Right now Intel P6/P4 and AMD K7 only.
 192          */
 193         if ((nmi == NMI_LOCAL_APIC) &&
 194                         (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
 195                         (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
 196                 nmi_watchdog = nmi;
 197         if ((nmi == NMI_LOCAL_APIC) &&
 198                         (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
 199                         (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
 200                 nmi_watchdog = nmi;
 201         /*
 202          * We can enable the IO-APIC watchdog
 203          * unconditionally.
 204          */
 205         if (nmi == NMI_IO_APIC) {
 206                 nmi_active = 1;
 207                 nmi_watchdog = nmi;
 208         }
 209         return 1;
 210 }
 211
 212 __setup("nmi_watchdog=", setup_nmi_watchdog);
 213
 214 static void disable_intel_arch_watchdog(void);
 215
 216 static void disable_lapic_nmi_watchdog(void)
 217 {
 218         if (nmi_active <= 0)
 219                 return;
 220         switch (boot_cpu_data.x86_vendor) {
 221         case X86_VENDOR_AMD:
 222                 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
 223                 break;
 224         case X86_VENDOR_INTEL:
 225                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 226                         disable_intel_arch_watchdog();
 227                         break;
 228                 }
 229                 switch (boot_cpu_data.x86) {
 230                 case 6:
 231                         if (boot_cpu_data.x86_model > 0xd)
 232                                 break;
 233
 234                         wrmsr(MSR_P6_EVNTSEL0, 0, 0);
 235                         break;
 236                 case 15:
 237                         if (boot_cpu_data.x86_model > 0x4)
 238                                 break;
 239
 240                         wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
 241                         wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
 242                         break;
 243                 }
 244                 break;
 245         }
 246         nmi_active = -1;
 247         /* tell do_nmi() and others that we're not active any more */
 248         nmi_watchdog = 0;
 249 }
 250
 251 static void enable_lapic_nmi_watchdog(void)
 252 {
 253         if (nmi_active < 0) {
 254                 nmi_watchdog = NMI_LOCAL_APIC;
 255                 setup_apic_nmi_watchdog();
 256         }
 257 }
 258
 259 int reserve_lapic_nmi(void)
 260 {
 261         unsigned int old_owner;
 262
 263         spin_lock(&lapic_nmi_owner_lock);
 264         old_owner = lapic_nmi_owner;
 265         lapic_nmi_owner |= LAPIC_NMI_RESERVED;
 266         spin_unlock(&lapic_nmi_owner_lock);
 267         if (old_owner & LAPIC_NMI_RESERVED)
 268                 return -EBUSY;
 269         if (old_owner & LAPIC_NMI_WATCHDOG)
 270                 disable_lapic_nmi_watchdog();
 271         return 0;
 272 }
 273
 274 void release_lapic_nmi(void)
 275 {
 276         unsigned int new_owner;
 277
 278         spin_lock(&lapic_nmi_owner_lock);
 279         new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
 280         lapic_nmi_owner = new_owner;
 281         spin_unlock(&lapic_nmi_owner_lock);
 282         if (new_owner & LAPIC_NMI_WATCHDOG)
 283                 enable_lapic_nmi_watchdog();
 284 }
 285
 286 void disable_timer_nmi_watchdog(void)
 287 {
 288         if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
 289                 return;
 290
 291         unset_nmi_callback();
 292         nmi_active = -1;
 293         nmi_watchdog = NMI_NONE;
 294 }
 295
 296 void enable_timer_nmi_watchdog(void)
 297 {
 298         if (nmi_active < 0) {
 299                 nmi_watchdog = NMI_IO_APIC;
 300                 touch_nmi_watchdog();
 301                 nmi_active = 1;
 302         }
 303 }
 304
 305 #ifdef CONFIG_PM
 306
 307 static int nmi_pm_active; /* nmi_active before suspend */
 308
 309 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 310 {
 311         nmi_pm_active = nmi_active;
 312         disable_lapic_nmi_watchdog();
 313         return 0;
 314 }
 315
 316 static int lapic_nmi_resume(struct sys_device *dev)
 317 {
 318         if (nmi_pm_active > 0)
 319                 enable_lapic_nmi_watchdog();
 320         return 0;
 321 }
 322
 323
 324 static struct sysdev_class nmi_sysclass = {
 325         set_kset_name("lapic_nmi"),
 326         .resume         = lapic_nmi_resume,
 327         .suspend        = lapic_nmi_suspend,
 328 };
 329
 330 static struct sys_device device_lapic_nmi = {
 331         .id     = 0,
 332         .cls    = &nmi_sysclass,
 333 };
 334
 335 static int __init init_lapic_nmi_sysfs(void)
 336 {
 337         int error;
 338
 339         if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
 340                 return 0;
 341
 342         error = sysdev_class_register(&nmi_sysclass);
 343         if (!error)
 344                 error = sysdev_register(&device_lapic_nmi);
 345         return error;
 346 }
 347 /* must come after the local APIC's device_initcall() */
 348 late_initcall(init_lapic_nmi_sysfs);
 349
 350 #endif  /* CONFIG_PM */
 351
 352 /*
 353  * Activate the NMI watchdog via the local APIC.
 354  * Original code written by Keith Owens.
 355  */
 356
 357 static void clear_msr_range(unsigned int base, unsigned int n)
 358 {
 359         unsigned int i;
 360
 361         for(i = 0; i < n; ++i)
 362                 wrmsr(base+i, 0, 0);
 363 }
 364
 365 static void write_watchdog_counter(const char *descr)
 366 {
 367         u64 count = (u64)cpu_khz * 1000;
 368
 369         do_div(count, nmi_hz);
 370         if(descr)
 371                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 372         wrmsrl(nmi_perfctr_msr, 0 - count);
 373 }
 374
 375 static void setup_k7_watchdog(void)
 376 {
 377         unsigned int evntsel;
 378
 379         nmi_perfctr_msr = MSR_K7_PERFCTR0;
 380
 381         clear_msr_range(MSR_K7_EVNTSEL0, 4);
 382         clear_msr_range(MSR_K7_PERFCTR0, 4);
 383
 384         evntsel = K7_EVNTSEL_INT
 385                 | K7_EVNTSEL_OS
 386                 | K7_EVNTSEL_USR
 387                 | K7_NMI_EVENT;
 388
 389         wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 390         write_watchdog_counter("K7_PERFCTR0");
 391         apic_write(APIC_LVTPC, APIC_DM_NMI);
 392         evntsel |= K7_EVNTSEL_ENABLE;
 393         wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 394 }
 395
 396 static void setup_p6_watchdog(void)
 397 {
 398         unsigned int evntsel;
 399
 400         nmi_perfctr_msr = MSR_P6_PERFCTR0;
 401
 402         clear_msr_range(MSR_P6_EVNTSEL0, 2);
 403         clear_msr_range(MSR_P6_PERFCTR0, 2);
 404
 405         evntsel = P6_EVNTSEL_INT
 406                 | P6_EVNTSEL_OS
 407                 | P6_EVNTSEL_USR
 408                 | P6_NMI_EVENT;
 409
 410         wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
 411         write_watchdog_counter("P6_PERFCTR0");
 412         apic_write(APIC_LVTPC, APIC_DM_NMI);
 413         evntsel |= P6_EVNTSEL0_ENABLE;
 414         wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
 415 }
 416
 417 static int setup_p4_watchdog(void)
 418 {
 419         unsigned int misc_enable, dummy;
 420
 421         rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
 422         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 423                 return 0;
 424
 425         nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
 426         nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
 427 #ifdef CONFIG_SMP
 428         if (smp_num_siblings == 2)
 429                 nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
 430 #endif
 431
 432         if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
 433                 clear_msr_range(0x3F1, 2);
 434         /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
 435            docs doesn't fully define it, so leave it alone for now. */
 436         if (boot_cpu_data.x86_model >= 0x3) {
 437                 /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
 438                 clear_msr_range(0x3A0, 26);
 439                 clear_msr_range(0x3BC, 3);
 440         } else {
 441                 clear_msr_range(0x3A0, 31);
 442         }
 443         clear_msr_range(0x3C0, 6);
 444         clear_msr_range(0x3C8, 6);
 445         clear_msr_range(0x3E0, 2);
 446         clear_msr_range(MSR_P4_CCCR0, 18);
 447         clear_msr_range(MSR_P4_PERFCTR0, 18);
 448
 449         wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
 450         wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
 451         write_watchdog_counter("P4_IQ_COUNTER0");
 452         apic_write(APIC_LVTPC, APIC_DM_NMI);
 453         wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
 454         return 1;
 455 }
 456
 457 static void disable_intel_arch_watchdog(void)
 458 {
 459         unsigned ebx;
 460
 461         /*
 462          * Check whether the Architectural PerfMon supports
 463          * Unhalted Core Cycles Event or not.
 464          * NOTE: Corresponding bit = 0 in ebp indicates event present.
 465          */
 466         ebx = cpuid_ebx(10);
 467         if (!(ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 468                 wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, 0, 0);
 469 }
 470
 471 static int setup_intel_arch_watchdog(void)
 472 {
 473         unsigned int evntsel;
 474         unsigned ebx;
 475
 476         /*
 477          * Check whether the Architectural PerfMon supports
 478          * Unhalted Core Cycles Event or not.
 479          * NOTE: Corresponding bit = 0 in ebp indicates event present.
 480          */
 481         ebx = cpuid_ebx(10);
 482         if ((ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 483                 return 0;
 484
 485         nmi_perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
 486
 487         clear_msr_range(MSR_ARCH_PERFMON_EVENTSEL0, 2);
 488         clear_msr_range(MSR_ARCH_PERFMON_PERFCTR0, 2);
 489
 490         evntsel = ARCH_PERFMON_EVENTSEL_INT
 491                 | ARCH_PERFMON_EVENTSEL_OS
 492                 | ARCH_PERFMON_EVENTSEL_USR
 493                 | ARCH_PERFMON_NMI_EVENT_SEL
 494                 | ARCH_PERFMON_NMI_EVENT_UMASK;
 495
 496         wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);
 497         write_watchdog_counter("INTEL_ARCH_PERFCTR0");
 498         apic_write(APIC_LVTPC, APIC_DM_NMI);
 499         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 500         wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);
 501         return 1;
 502 }
 503
 504 void setup_apic_nmi_watchdog (void)
 505 {
 506         switch (boot_cpu_data.x86_vendor) {
 507         case X86_VENDOR_AMD:
 508                 if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
 509                         return;
 510                 setup_k7_watchdog();
 511                 break;
 512         case X86_VENDOR_INTEL:
 513                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 514                         if (!setup_intel_arch_watchdog())
 515                                 return;
 516                         break;
 517                 }
 518                 switch (boot_cpu_data.x86) {
 519                 case 6:
 520                         if (boot_cpu_data.x86_model > 0xd)
 521                                 return;
 522
 523                         setup_p6_watchdog();
 524                         break;
 525                 case 15:
 526                         if (boot_cpu_data.x86_model > 0x4)
 527                                 return;
 528
 529                         if (!setup_p4_watchdog())
 530                                 return;
 531                         break;
 532                 default:
 533                         return;
 534                 }
 535                 break;
 536         default:
 537                 return;
 538         }
 539         lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
 540         nmi_active = 1;
 541 }
 542
 543 /*
 544  * the best way to detect whether a CPU has a 'hard lockup' problem
 545  * is to check it's local APIC timer IRQ counts. If they are not
 546  * changing then that CPU has some problem.
 547  *
 548  * as these watchdog NMI IRQs are generated on every CPU, we only
 549  * have to check the current processor.
 550  *
 551  * since NMIs don't listen to _any_ locks, we have to be extremely
 552  * careful not to rely on unsafe variables. The printk might lock
 553  * up though, so we have to break up any console locks first ...
 554  * [when there will be more tty-related locks, break them up
 555  *  here too!]
 556  */
 557
 558 static unsigned int
 559         last_irq_sums [NR_CPUS],
 560         alert_counter [NR_CPUS];
 561
 562 void touch_nmi_watchdog (void)
 563 {
 564         int i;
 565
 566         /*
 567          * Just reset the alert counters, (other CPUs might be
 568          * spinning on locks we hold):
 569          */
 570         for_each_possible_cpu(i)
 571                 alert_counter[i] = 0;
 572
 573         /*
 574          * Tickle the softlockup detector too:
 575          */
 576         touch_softlockup_watchdog();
 577 }
 578
 579 extern void die_nmi(struct pt_regs *, const char *msg);
 580
 581 void nmi_watchdog_tick (struct pt_regs * regs)
 582 {
 583
 584         /*
 585          * Since current_thread_info()-> is always on the stack, and we
 586          * always switch the stack NMI-atomically, it's safe to use
 587          * smp_processor_id().
 588          */
 589         unsigned int sum;
 590         int cpu = smp_processor_id();
 591
 592         sum = per_cpu(irq_stat, cpu).apic_timer_irqs;
 593
 594         if (last_irq_sums[cpu] == sum) {
 595                 /*
 596                  * Ayiee, looks like this CPU is stuck ...
 597                  * wait a few IRQs (5 seconds) before doing the oops ...
 598                  */
 599                 alert_counter[cpu]++;
 600                 if (alert_counter[cpu] == 5*nmi_hz)
 601                         /*
 602                          * die_nmi will return ONLY if NOTIFY_STOP happens..
 603                          */
 604                         die_nmi(regs, "BUG: NMI Watchdog detected LOCKUP");
 605         } else {
 606                 last_irq_sums[cpu] = sum;
 607                 alert_counter[cpu] = 0;
 608         }
 609         if (nmi_perfctr_msr) {
 610                 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
 611                         /*
 612                          * P4 quirks:
 613                          * - An overflown perfctr will assert its interrupt
 614                          *   until the OVF flag in its CCCR is cleared.
 615                          * - LVTPC is masked on interrupt and must be
 616                          *   unmasked by the LVTPC handler.
 617                          */
 618                         wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
 619                         apic_write(APIC_LVTPC, APIC_DM_NMI);
 620                 }
 621                 else if (nmi_perfctr_msr == MSR_P6_PERFCTR0 ||
 622                          nmi_perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
 623                         /* Only P6 based Pentium M need to re-unmask
 624                          * the apic vector but it doesn't hurt
 625                          * other P6 variant */
 626                         apic_write(APIC_LVTPC, APIC_DM_NMI);
 627                 }
 628                 write_watchdog_counter(NULL);
 629         }
 630 }
 631
 632 #ifdef CONFIG_SYSCTL
 633
 634 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
 635 {
 636         unsigned char reason = get_nmi_reason();
 637         char buf[64];
 638
 639         if (!(reason & 0xc0)) {
 640                 sprintf(buf, "NMI received for unknown reason %02x\n", reason);
 641                 die_nmi(regs, buf);
 642         }
 643         return 0;
 644 }
 645
 646 /*
 647  * proc handler for /proc/sys/kernel/unknown_nmi_panic
 648  */
 649 int proc_unknown_nmi_panic(ctl_table *table, int write, struct file *file,
 650                         void __user *buffer, size_t *length, loff_t *ppos)
 651 {
 652         int old_state;
 653
 654         old_state = unknown_nmi_panic;
 655         proc_dointvec(table, write, file, buffer, length, ppos);
 656         if (!!old_state == !!unknown_nmi_panic)
 657                 return 0;
 658
 659         if (unknown_nmi_panic) {
 660                 if (reserve_lapic_nmi() < 0) {
 661                         unknown_nmi_panic = 0;
 662                         return -EBUSY;
 663                 } else {
 664                         set_nmi_callback(unknown_nmi_panic_callback);
 665                 }
 666         } else {
 667                 release_lapic_nmi();
 668                 unset_nmi_callback();
 669         }
 670         return 0;
 671 }
 672
 673 #endif
 674
 675 EXPORT_SYMBOL(nmi_active);
 676 EXPORT_SYMBOL(nmi_watchdog);
 677 EXPORT_SYMBOL(reserve_lapic_nmi);
 678 EXPORT_SYMBOL(release_lapic_nmi);
 679 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
 680 EXPORT_SYMBOL(enable_timer_nmi_watchdog);