2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/init.h>
39 #include <linux/kernel.h>
42 #include <linux/sched.h>
43 #include <linux/kernel_stat.h>
44 #include <linux/smp_lock.h>
45 #include <linux/bootmem.h>
46 #include <linux/notifier.h>
47 #include <linux/cpu.h>
48 #include <linux/percpu.h>
50 #include <linux/delay.h>
51 #include <linux/mc146818rtc.h>
52 #include <asm/tlbflush.h>
54 #include <asm/arch_hooks.h>
57 #include <mach_apic.h>
58 #include <mach_wakecpu.h>
59 #include <smpboot_hooks.h>
61 /* Set if we find a B stepping CPU */
62 static int __devinitdata smp_b_stepping
;
64 /* Number of siblings per CPU package */
65 int smp_num_siblings
= 1;
67 EXPORT_SYMBOL(smp_num_siblings
);
70 /* Package ID of each logical CPU */
71 int phys_proc_id
[NR_CPUS
] __read_mostly
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
73 /* Core ID of each logical CPU */
74 int cpu_core_id
[NR_CPUS
] __read_mostly
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
76 /* Last level cache ID of each logical CPU */
77 int cpu_llc_id
[NR_CPUS
] __cpuinitdata
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
79 /* representing HT siblings of each logical CPU */
80 cpumask_t cpu_sibling_map
[NR_CPUS
] __read_mostly
;
81 EXPORT_SYMBOL(cpu_sibling_map
);
83 /* representing HT and core siblings of each logical CPU */
84 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
;
85 EXPORT_SYMBOL(cpu_core_map
);
87 /* bitmap of online cpus */
88 cpumask_t cpu_online_map __read_mostly
;
89 EXPORT_SYMBOL(cpu_online_map
);
91 cpumask_t cpu_callin_map
;
92 cpumask_t cpu_callout_map
;
93 EXPORT_SYMBOL(cpu_callout_map
);
94 cpumask_t cpu_possible_map
;
95 EXPORT_SYMBOL(cpu_possible_map
);
96 static cpumask_t smp_commenced_mask
;
98 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
99 * is no way to resync one AP against BP. TBD: for prescott and above, we
100 * should use IA64's algorithm
102 static int __devinitdata tsc_sync_disabled
;
104 /* Per CPU bogomips and other parameters */
105 struct cpuinfo_x86 cpu_data
[NR_CPUS
] __cacheline_aligned
;
106 EXPORT_SYMBOL(cpu_data
);
108 u8 x86_cpu_to_apicid
[NR_CPUS
] __read_mostly
=
109 { [0 ... NR_CPUS
-1] = 0xff };
110 EXPORT_SYMBOL(x86_cpu_to_apicid
);
113 * Trampoline 80x86 program as an array.
116 extern unsigned char trampoline_data
[];
117 extern unsigned char trampoline_end
[];
118 static unsigned char *trampoline_base
;
119 static int trampoline_exec
;
121 static void map_cpu_to_logical_apicid(void);
123 /* State of each CPU. */
124 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
127 * Currently trivial. Write the real->protected mode
128 * bootstrap into the page concerned. The caller
129 * has made sure it's suitably aligned.
132 static unsigned long __devinit
setup_trampoline(void)
134 memcpy(trampoline_base
, trampoline_data
, trampoline_end
- trampoline_data
);
135 return virt_to_phys(trampoline_base
);
139 * We are called very early to get the low memory for the
140 * SMP bootup trampoline page.
142 void __init
smp_alloc_memory(void)
144 trampoline_base
= (void *) alloc_bootmem_low_pages(PAGE_SIZE
);
146 * Has to be in very low memory so we can execute
149 if (__pa(trampoline_base
) >= 0x9F000)
152 * Make the SMP trampoline executable:
154 trampoline_exec
= set_kernel_exec((unsigned long)trampoline_base
, 1);
158 * The bootstrap kernel entry code has set these up. Save them for
162 static void __devinit
smp_store_cpu_info(int id
)
164 struct cpuinfo_x86
*c
= cpu_data
+ id
;
170 * Mask B, Pentium, but not Pentium MMX
172 if (c
->x86_vendor
== X86_VENDOR_INTEL
&&
174 c
->x86_mask
>= 1 && c
->x86_mask
<= 4 &&
177 * Remember we have B step Pentia with bugs
182 * Certain Athlons might work (for various values of 'work') in SMP
183 * but they are not certified as MP capable.
185 if ((c
->x86_vendor
== X86_VENDOR_AMD
) && (c
->x86
== 6)) {
187 /* Athlon 660/661 is valid. */
188 if ((c
->x86_model
==6) && ((c
->x86_mask
==0) || (c
->x86_mask
==1)))
191 /* Duron 670 is valid */
192 if ((c
->x86_model
==7) && (c
->x86_mask
==0))
196 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
197 * It's worth noting that the A5 stepping (662) of some Athlon XP's
198 * have the MP bit set.
199 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
201 if (((c
->x86_model
==6) && (c
->x86_mask
>=2)) ||
202 ((c
->x86_model
==7) && (c
->x86_mask
>=1)) ||
207 /* If we get here, it's not a certified SMP capable AMD system. */
208 add_taint(TAINT_UNSAFE_SMP
);
216 * TSC synchronization.
218 * We first check whether all CPUs have their TSC's synchronized,
219 * then we print a warning if not, and always resync.
222 static atomic_t tsc_start_flag
= ATOMIC_INIT(0);
223 static atomic_t tsc_count_start
= ATOMIC_INIT(0);
224 static atomic_t tsc_count_stop
= ATOMIC_INIT(0);
225 static unsigned long long tsc_values
[NR_CPUS
];
229 static void __init
synchronize_tsc_bp (void)
232 unsigned long long t0
;
233 unsigned long long sum
, avg
;
235 unsigned int one_usec
;
238 printk(KERN_INFO
"checking TSC synchronization across %u CPUs: ", num_booting_cpus());
240 /* convert from kcyc/sec to cyc/usec */
241 one_usec
= cpu_khz
/ 1000;
243 atomic_set(&tsc_start_flag
, 1);
247 * We loop a few times to get a primed instruction cache,
248 * then the last pass is more or less synchronized and
249 * the BP and APs set their cycle counters to zero all at
250 * once. This reduces the chance of having random offsets
251 * between the processors, and guarantees that the maximum
252 * delay between the cycle counters is never bigger than
253 * the latency of information-passing (cachelines) between
256 for (i
= 0; i
< NR_LOOPS
; i
++) {
258 * all APs synchronize but they loop on '== num_cpus'
260 while (atomic_read(&tsc_count_start
) != num_booting_cpus()-1)
262 atomic_set(&tsc_count_stop
, 0);
265 * this lets the APs save their current TSC:
267 atomic_inc(&tsc_count_start
);
269 rdtscll(tsc_values
[smp_processor_id()]);
271 * We clear the TSC in the last loop:
277 * Wait for all APs to leave the synchronization point:
279 while (atomic_read(&tsc_count_stop
) != num_booting_cpus()-1)
281 atomic_set(&tsc_count_start
, 0);
283 atomic_inc(&tsc_count_stop
);
287 for (i
= 0; i
< NR_CPUS
; i
++) {
288 if (cpu_isset(i
, cpu_callout_map
)) {
294 do_div(avg
, num_booting_cpus());
297 for (i
= 0; i
< NR_CPUS
; i
++) {
298 if (!cpu_isset(i
, cpu_callout_map
))
300 delta
= tsc_values
[i
] - avg
;
304 * We report bigger than 2 microseconds clock differences.
306 if (delta
> 2*one_usec
) {
313 do_div(realdelta
, one_usec
);
314 if (tsc_values
[i
] < avg
)
315 realdelta
= -realdelta
;
318 printk(KERN_INFO
"CPU#%d had %ld usecs TSC "
319 "skew, fixed it up.\n", i
, realdelta
);
328 static void __init
synchronize_tsc_ap (void)
333 * Not every cpu is online at the time
334 * this gets called, so we first wait for the BP to
335 * finish SMP initialization:
337 while (!atomic_read(&tsc_start_flag
))
340 for (i
= 0; i
< NR_LOOPS
; i
++) {
341 atomic_inc(&tsc_count_start
);
342 while (atomic_read(&tsc_count_start
) != num_booting_cpus())
345 rdtscll(tsc_values
[smp_processor_id()]);
349 atomic_inc(&tsc_count_stop
);
350 while (atomic_read(&tsc_count_stop
) != num_booting_cpus())
356 extern void calibrate_delay(void);
358 static atomic_t init_deasserted
;
360 static void __devinit
smp_callin(void)
363 unsigned long timeout
;
366 * If waken up by an INIT in an 82489DX configuration
367 * we may get here before an INIT-deassert IPI reaches
368 * our local APIC. We have to wait for the IPI or we'll
369 * lock up on an APIC access.
371 wait_for_init_deassert(&init_deasserted
);
374 * (This works even if the APIC is not enabled.)
376 phys_id
= GET_APIC_ID(apic_read(APIC_ID
));
377 cpuid
= smp_processor_id();
378 if (cpu_isset(cpuid
, cpu_callin_map
)) {
379 printk("huh, phys CPU#%d, CPU#%d already present??\n",
383 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
386 * STARTUP IPIs are fragile beasts as they might sometimes
387 * trigger some glue motherboard logic. Complete APIC bus
388 * silence for 1 second, this overestimates the time the
389 * boot CPU is spending to send the up to 2 STARTUP IPIs
390 * by a factor of two. This should be enough.
394 * Waiting 2s total for startup (udelay is not yet working)
396 timeout
= jiffies
+ 2*HZ
;
397 while (time_before(jiffies
, timeout
)) {
399 * Has the boot CPU finished it's STARTUP sequence?
401 if (cpu_isset(cpuid
, cpu_callout_map
))
406 if (!time_before(jiffies
, timeout
)) {
407 printk("BUG: CPU%d started up but did not get a callout!\n",
413 * the boot CPU has finished the init stage and is spinning
414 * on callin_map until we finish. We are free to set up this
415 * CPU, first the APIC. (this is probably redundant on most
419 Dprintk("CALLIN, before setup_local_APIC().\n");
420 smp_callin_clear_local_apic();
422 map_cpu_to_logical_apicid();
428 Dprintk("Stack at about %p\n",&cpuid
);
431 * Save our processor parameters
433 smp_store_cpu_info(cpuid
);
435 disable_APIC_timer();
438 * Allow the master to continue.
440 cpu_set(cpuid
, cpu_callin_map
);
443 * Synchronize the TSC with the BP
445 if (cpu_has_tsc
&& cpu_khz
&& !tsc_sync_disabled
)
446 synchronize_tsc_ap();
451 /* maps the cpu to the sched domain representing multi-core */
452 cpumask_t
cpu_coregroup_map(int cpu
)
454 struct cpuinfo_x86
*c
= cpu_data
+ cpu
;
456 * For perf, we return last level cache shared map.
457 * TBD: when power saving sched policy is added, we will return
458 * cpu_core_map when power saving policy is enabled
460 return c
->llc_shared_map
;
463 /* representing cpus for which sibling maps can be computed */
464 static cpumask_t cpu_sibling_setup_map
;
467 set_cpu_sibling_map(int cpu
)
470 struct cpuinfo_x86
*c
= cpu_data
;
472 cpu_set(cpu
, cpu_sibling_setup_map
);
474 if (smp_num_siblings
> 1) {
475 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
476 if (phys_proc_id
[cpu
] == phys_proc_id
[i
] &&
477 cpu_core_id
[cpu
] == cpu_core_id
[i
]) {
478 cpu_set(i
, cpu_sibling_map
[cpu
]);
479 cpu_set(cpu
, cpu_sibling_map
[i
]);
480 cpu_set(i
, cpu_core_map
[cpu
]);
481 cpu_set(cpu
, cpu_core_map
[i
]);
482 cpu_set(i
, c
[cpu
].llc_shared_map
);
483 cpu_set(cpu
, c
[i
].llc_shared_map
);
487 cpu_set(cpu
, cpu_sibling_map
[cpu
]);
490 cpu_set(cpu
, c
[cpu
].llc_shared_map
);
492 if (current_cpu_data
.x86_max_cores
== 1) {
493 cpu_core_map
[cpu
] = cpu_sibling_map
[cpu
];
494 c
[cpu
].booted_cores
= 1;
498 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
499 if (cpu_llc_id
[cpu
] != BAD_APICID
&&
500 cpu_llc_id
[cpu
] == cpu_llc_id
[i
]) {
501 cpu_set(i
, c
[cpu
].llc_shared_map
);
502 cpu_set(cpu
, c
[i
].llc_shared_map
);
504 if (phys_proc_id
[cpu
] == phys_proc_id
[i
]) {
505 cpu_set(i
, cpu_core_map
[cpu
]);
506 cpu_set(cpu
, cpu_core_map
[i
]);
508 * Does this new cpu bringup a new core?
510 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1) {
512 * for each core in package, increment
513 * the booted_cores for this new cpu
515 if (first_cpu(cpu_sibling_map
[i
]) == i
)
516 c
[cpu
].booted_cores
++;
518 * increment the core count for all
519 * the other cpus in this package
523 } else if (i
!= cpu
&& !c
[cpu
].booted_cores
)
524 c
[cpu
].booted_cores
= c
[i
].booted_cores
;
530 * Activate a secondary processor.
532 static void __devinit
start_secondary(void *unused
)
535 * Dont put anything before smp_callin(), SMP
536 * booting is too fragile that we want to limit the
537 * things done here to the most necessary things.
542 while (!cpu_isset(smp_processor_id(), smp_commenced_mask
))
544 setup_secondary_APIC_clock();
545 if (nmi_watchdog
== NMI_IO_APIC
) {
546 disable_8259A_irq(0);
547 enable_NMI_through_LVT0(NULL
);
552 * low-memory mappings have been cleared, flush them from
553 * the local TLBs too.
557 /* This must be done before setting cpu_online_map */
558 set_cpu_sibling_map(raw_smp_processor_id());
562 * We need to hold call_lock, so there is no inconsistency
563 * between the time smp_call_function() determines number of
564 * IPI receipients, and the time when the determination is made
565 * for which cpus receive the IPI. Holding this
566 * lock helps us to not include this cpu in a currently in progress
567 * smp_call_function().
569 lock_ipi_call_lock();
570 cpu_set(smp_processor_id(), cpu_online_map
);
571 unlock_ipi_call_lock();
572 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
574 /* We can take interrupts now: we're officially "up". */
582 * Everything has been set up for the secondary
583 * CPUs - they just need to reload everything
584 * from the task structure
585 * This function must not return.
587 void __devinit
initialize_secondary(void)
590 * We don't actually need to load the full TSS,
591 * basically just the stack pointer and the eip.
598 :"r" (current
->thread
.esp
),"r" (current
->thread
.eip
));
608 /* which logical CPUs are on which nodes */
609 cpumask_t node_2_cpu_mask
[MAX_NUMNODES
] __read_mostly
=
610 { [0 ... MAX_NUMNODES
-1] = CPU_MASK_NONE
};
611 /* which node each logical CPU is on */
612 int cpu_2_node
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = 0 };
613 EXPORT_SYMBOL(cpu_2_node
);
615 /* set up a mapping between cpu and node. */
616 static inline void map_cpu_to_node(int cpu
, int node
)
618 printk("Mapping cpu %d to node %d\n", cpu
, node
);
619 cpu_set(cpu
, node_2_cpu_mask
[node
]);
620 cpu_2_node
[cpu
] = node
;
623 /* undo a mapping between cpu and node. */
624 static inline void unmap_cpu_to_node(int cpu
)
628 printk("Unmapping cpu %d from all nodes\n", cpu
);
629 for (node
= 0; node
< MAX_NUMNODES
; node
++)
630 cpu_clear(cpu
, node_2_cpu_mask
[node
]);
633 #else /* !CONFIG_NUMA */
635 #define map_cpu_to_node(cpu, node) ({})
636 #define unmap_cpu_to_node(cpu) ({})
638 #endif /* CONFIG_NUMA */
640 u8 cpu_2_logical_apicid
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = BAD_APICID
};
642 static void map_cpu_to_logical_apicid(void)
644 int cpu
= smp_processor_id();
645 int apicid
= logical_smp_processor_id();
647 cpu_2_logical_apicid
[cpu
] = apicid
;
648 map_cpu_to_node(cpu
, apicid_to_node(apicid
));
651 static void unmap_cpu_to_logical_apicid(int cpu
)
653 cpu_2_logical_apicid
[cpu
] = BAD_APICID
;
654 unmap_cpu_to_node(cpu
);
658 static inline void __inquire_remote_apic(int apicid
)
660 int i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
661 char *names
[] = { "ID", "VERSION", "SPIV" };
664 printk("Inquiring remote APIC #%d...\n", apicid
);
666 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
667 printk("... APIC #%d %s: ", apicid
, names
[i
]);
672 apic_wait_icr_idle();
674 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(apicid
));
675 apic_write_around(APIC_ICR
, APIC_DM_REMRD
| regs
[i
]);
680 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
681 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
684 case APIC_ICR_RR_VALID
:
685 status
= apic_read(APIC_RRR
);
686 printk("%08x\n", status
);
695 #ifdef WAKE_SECONDARY_VIA_NMI
697 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
698 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
699 * won't ... remember to clear down the APIC, etc later.
702 wakeup_secondary_cpu(int logical_apicid
, unsigned long start_eip
)
704 unsigned long send_status
= 0, accept_status
= 0;
708 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(logical_apicid
));
710 /* Boot on the stack */
711 /* Kick the second */
712 apic_write_around(APIC_ICR
, APIC_DM_NMI
| APIC_DEST_LOGICAL
);
714 Dprintk("Waiting for send to finish...\n");
719 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
720 } while (send_status
&& (timeout
++ < 1000));
723 * Give the other CPU some time to accept the IPI.
727 * Due to the Pentium erratum 3AP.
729 maxlvt
= get_maxlvt();
731 apic_read_around(APIC_SPIV
);
732 apic_write(APIC_ESR
, 0);
734 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
735 Dprintk("NMI sent.\n");
738 printk("APIC never delivered???\n");
740 printk("APIC delivery error (%lx).\n", accept_status
);
742 return (send_status
| accept_status
);
744 #endif /* WAKE_SECONDARY_VIA_NMI */
746 #ifdef WAKE_SECONDARY_VIA_INIT
748 wakeup_secondary_cpu(int phys_apicid
, unsigned long start_eip
)
750 unsigned long send_status
= 0, accept_status
= 0;
751 int maxlvt
, timeout
, num_starts
, j
;
754 * Be paranoid about clearing APIC errors.
756 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
757 apic_read_around(APIC_SPIV
);
758 apic_write(APIC_ESR
, 0);
762 Dprintk("Asserting INIT.\n");
765 * Turn INIT on target chip
767 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
772 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
775 Dprintk("Waiting for send to finish...\n");
780 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
781 } while (send_status
&& (timeout
++ < 1000));
785 Dprintk("Deasserting INIT.\n");
788 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
791 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
793 Dprintk("Waiting for send to finish...\n");
798 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
799 } while (send_status
&& (timeout
++ < 1000));
801 atomic_set(&init_deasserted
, 1);
804 * Should we send STARTUP IPIs ?
806 * Determine this based on the APIC version.
807 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
809 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
815 * Run STARTUP IPI loop.
817 Dprintk("#startup loops: %d.\n", num_starts
);
819 maxlvt
= get_maxlvt();
821 for (j
= 1; j
<= num_starts
; j
++) {
822 Dprintk("Sending STARTUP #%d.\n",j
);
823 apic_read_around(APIC_SPIV
);
824 apic_write(APIC_ESR
, 0);
826 Dprintk("After apic_write.\n");
833 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
835 /* Boot on the stack */
836 /* Kick the second */
837 apic_write_around(APIC_ICR
, APIC_DM_STARTUP
838 | (start_eip
>> 12));
841 * Give the other CPU some time to accept the IPI.
845 Dprintk("Startup point 1.\n");
847 Dprintk("Waiting for send to finish...\n");
852 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
853 } while (send_status
&& (timeout
++ < 1000));
856 * Give the other CPU some time to accept the IPI.
860 * Due to the Pentium erratum 3AP.
863 apic_read_around(APIC_SPIV
);
864 apic_write(APIC_ESR
, 0);
866 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
867 if (send_status
|| accept_status
)
870 Dprintk("After Startup.\n");
873 printk("APIC never delivered???\n");
875 printk("APIC delivery error (%lx).\n", accept_status
);
877 return (send_status
| accept_status
);
879 #endif /* WAKE_SECONDARY_VIA_INIT */
881 extern cpumask_t cpu_initialized
;
882 static inline int alloc_cpu_id(void)
886 cpus_complement(tmp_map
, cpu_present_map
);
887 cpu
= first_cpu(tmp_map
);
893 #ifdef CONFIG_HOTPLUG_CPU
894 static struct task_struct
* __devinitdata cpu_idle_tasks
[NR_CPUS
];
895 static inline struct task_struct
* alloc_idle_task(int cpu
)
897 struct task_struct
*idle
;
899 if ((idle
= cpu_idle_tasks
[cpu
]) != NULL
) {
900 /* initialize thread_struct. we really want to avoid destroy
903 idle
->thread
.esp
= (unsigned long)task_pt_regs(idle
);
904 init_idle(idle
, cpu
);
907 idle
= fork_idle(cpu
);
910 cpu_idle_tasks
[cpu
] = idle
;
914 #define alloc_idle_task(cpu) fork_idle(cpu)
917 static int __devinit
do_boot_cpu(int apicid
, int cpu
)
919 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
920 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
921 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
924 struct task_struct
*idle
;
925 unsigned long boot_error
;
927 unsigned long start_eip
;
928 unsigned short nmi_high
= 0, nmi_low
= 0;
931 alternatives_smp_switch(1);
934 * We can't use kernel_thread since we must avoid to
935 * reschedule the child.
937 idle
= alloc_idle_task(cpu
);
939 panic("failed fork for CPU %d", cpu
);
940 idle
->thread
.eip
= (unsigned long) start_secondary
;
941 /* start_eip had better be page-aligned! */
942 start_eip
= setup_trampoline();
944 /* So we see what's up */
945 printk("Booting processor %d/%d eip %lx\n", cpu
, apicid
, start_eip
);
946 /* Stack for startup_32 can be just as for start_secondary onwards */
947 stack_start
.esp
= (void *) idle
->thread
.esp
;
952 * This grunge runs the startup process for
953 * the targeted processor.
956 atomic_set(&init_deasserted
, 0);
958 Dprintk("Setting warm reset code and vector.\n");
960 store_NMI_vector(&nmi_high
, &nmi_low
);
962 smpboot_setup_warm_reset_vector(start_eip
);
965 * Starting actual IPI sequence...
967 boot_error
= wakeup_secondary_cpu(apicid
, start_eip
);
971 * allow APs to start initializing.
973 Dprintk("Before Callout %d.\n", cpu
);
974 cpu_set(cpu
, cpu_callout_map
);
975 Dprintk("After Callout %d.\n", cpu
);
978 * Wait 5s total for a response
980 for (timeout
= 0; timeout
< 50000; timeout
++) {
981 if (cpu_isset(cpu
, cpu_callin_map
))
982 break; /* It has booted */
986 if (cpu_isset(cpu
, cpu_callin_map
)) {
987 /* number CPUs logically, starting from 1 (BSP is 0) */
989 printk("CPU%d: ", cpu
);
990 print_cpu_info(&cpu_data
[cpu
]);
991 Dprintk("CPU has booted.\n");
994 if (*((volatile unsigned char *)trampoline_base
)
996 /* trampoline started but...? */
997 printk("Stuck ??\n");
999 /* trampoline code not run */
1000 printk("Not responding.\n");
1001 inquire_remote_apic(apicid
);
1006 /* Try to put things back the way they were before ... */
1007 unmap_cpu_to_logical_apicid(cpu
);
1008 cpu_clear(cpu
, cpu_callout_map
); /* was set here (do_boot_cpu()) */
1009 cpu_clear(cpu
, cpu_initialized
); /* was set by cpu_init() */
1012 x86_cpu_to_apicid
[cpu
] = apicid
;
1013 cpu_set(cpu
, cpu_present_map
);
1016 /* mark "stuck" area as not stuck */
1017 *((volatile unsigned long *)trampoline_base
) = 0;
1022 #ifdef CONFIG_HOTPLUG_CPU
1023 void cpu_exit_clear(void)
1025 int cpu
= raw_smp_processor_id();
1033 cpu_clear(cpu
, cpu_callout_map
);
1034 cpu_clear(cpu
, cpu_callin_map
);
1036 cpu_clear(cpu
, smp_commenced_mask
);
1037 unmap_cpu_to_logical_apicid(cpu
);
1040 struct warm_boot_cpu_info
{
1041 struct completion
*complete
;
1046 static void __cpuinit
do_warm_boot_cpu(void *p
)
1048 struct warm_boot_cpu_info
*info
= p
;
1049 do_boot_cpu(info
->apicid
, info
->cpu
);
1050 complete(info
->complete
);
1053 static int __cpuinit
__smp_prepare_cpu(int cpu
)
1055 DECLARE_COMPLETION(done
);
1056 struct warm_boot_cpu_info info
;
1057 struct work_struct task
;
1060 apicid
= x86_cpu_to_apicid
[cpu
];
1061 if (apicid
== BAD_APICID
) {
1066 info
.complete
= &done
;
1067 info
.apicid
= apicid
;
1069 INIT_WORK(&task
, do_warm_boot_cpu
, &info
);
1071 tsc_sync_disabled
= 1;
1073 /* init low mem mapping */
1074 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ USER_PGD_PTRS
,
1077 schedule_work(&task
);
1078 wait_for_completion(&done
);
1080 tsc_sync_disabled
= 0;
1088 static void smp_tune_scheduling (void)
1090 unsigned long cachesize
; /* kB */
1091 unsigned long bandwidth
= 350; /* MB/s */
1093 * Rough estimation for SMP scheduling, this is the number of
1094 * cycles it takes for a fully memory-limited process to flush
1095 * the SMP-local cache.
1097 * (For a P5 this pretty much means we will choose another idle
1098 * CPU almost always at wakeup time (this is due to the small
1099 * L1 cache), on PIIs it's around 50-100 usecs, depending on
1105 * this basically disables processor-affinity
1106 * scheduling on SMP without a TSC.
1110 cachesize
= boot_cpu_data
.x86_cache_size
;
1111 if (cachesize
== -1) {
1112 cachesize
= 16; /* Pentiums, 2x8kB cache */
1115 max_cache_size
= cachesize
* 1024;
1120 * Cycle through the processors sending APIC IPIs to boot each.
1123 static int boot_cpu_logical_apicid
;
1124 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1126 #ifdef CONFIG_X86_NUMAQ
1127 EXPORT_SYMBOL(xquad_portio
);
1130 static void __init
smp_boot_cpus(unsigned int max_cpus
)
1132 int apicid
, cpu
, bit
, kicked
;
1133 unsigned long bogosum
= 0;
1136 * Setup boot CPU information
1138 smp_store_cpu_info(0); /* Final full version of the data */
1139 printk("CPU%d: ", 0);
1140 print_cpu_info(&cpu_data
[0]);
1142 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1143 boot_cpu_logical_apicid
= logical_smp_processor_id();
1144 x86_cpu_to_apicid
[0] = boot_cpu_physical_apicid
;
1146 current_thread_info()->cpu
= 0;
1147 smp_tune_scheduling();
1149 set_cpu_sibling_map(0);
1152 * If we couldn't find an SMP configuration at boot time,
1153 * get out of here now!
1155 if (!smp_found_config
&& !acpi_lapic
) {
1156 printk(KERN_NOTICE
"SMP motherboard not detected.\n");
1157 smpboot_clear_io_apic_irqs();
1158 phys_cpu_present_map
= physid_mask_of_physid(0);
1159 if (APIC_init_uniprocessor())
1160 printk(KERN_NOTICE
"Local APIC not detected."
1161 " Using dummy APIC emulation.\n");
1162 map_cpu_to_logical_apicid();
1163 cpu_set(0, cpu_sibling_map
[0]);
1164 cpu_set(0, cpu_core_map
[0]);
1169 * Should not be necessary because the MP table should list the boot
1170 * CPU too, but we do it for the sake of robustness anyway.
1171 * Makes no sense to do this check in clustered apic mode, so skip it
1173 if (!check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1174 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1175 boot_cpu_physical_apicid
);
1176 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1180 * If we couldn't find a local APIC, then get out of here now!
1182 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) && !cpu_has_apic
) {
1183 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1184 boot_cpu_physical_apicid
);
1185 printk(KERN_ERR
"... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1186 smpboot_clear_io_apic_irqs();
1187 phys_cpu_present_map
= physid_mask_of_physid(0);
1188 cpu_set(0, cpu_sibling_map
[0]);
1189 cpu_set(0, cpu_core_map
[0]);
1193 verify_local_APIC();
1196 * If SMP should be disabled, then really disable it!
1199 smp_found_config
= 0;
1200 printk(KERN_INFO
"SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1201 smpboot_clear_io_apic_irqs();
1202 phys_cpu_present_map
= physid_mask_of_physid(0);
1203 cpu_set(0, cpu_sibling_map
[0]);
1204 cpu_set(0, cpu_core_map
[0]);
1210 map_cpu_to_logical_apicid();
1213 setup_portio_remap();
1216 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1218 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1219 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1220 * clustered apic ID.
1222 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map
));
1225 for (bit
= 0; kicked
< NR_CPUS
&& bit
< MAX_APICS
; bit
++) {
1226 apicid
= cpu_present_to_apicid(bit
);
1228 * Don't even attempt to start the boot CPU!
1230 if ((apicid
== boot_cpu_apicid
) || (apicid
== BAD_APICID
))
1233 if (!check_apicid_present(bit
))
1235 if (max_cpus
<= cpucount
+1)
1238 if (((cpu
= alloc_cpu_id()) <= 0) || do_boot_cpu(apicid
, cpu
))
1239 printk("CPU #%d not responding - cannot use it.\n",
1246 * Cleanup possible dangling ends...
1248 smpboot_restore_warm_reset_vector();
1251 * Allow the user to impress friends.
1253 Dprintk("Before bogomips.\n");
1254 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++)
1255 if (cpu_isset(cpu
, cpu_callout_map
))
1256 bogosum
+= cpu_data
[cpu
].loops_per_jiffy
;
1258 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1260 bogosum
/(500000/HZ
),
1261 (bogosum
/(5000/HZ
))%100);
1263 Dprintk("Before bogocount - setting activated=1.\n");
1266 printk(KERN_WARNING
"WARNING: SMP operation may be unreliable with B stepping processors.\n");
1269 * Don't taint if we are running SMP kernel on a single non-MP
1272 if (tainted
& TAINT_UNSAFE_SMP
) {
1274 printk (KERN_INFO
"WARNING: This combination of AMD processors is not suitable for SMP.\n");
1276 tainted
&= ~TAINT_UNSAFE_SMP
;
1279 Dprintk("Boot done.\n");
1282 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1285 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++) {
1286 cpus_clear(cpu_sibling_map
[cpu
]);
1287 cpus_clear(cpu_core_map
[cpu
]);
1290 cpu_set(0, cpu_sibling_map
[0]);
1291 cpu_set(0, cpu_core_map
[0]);
1293 smpboot_setup_io_apic();
1295 setup_boot_APIC_clock();
1298 * Synchronize the TSC with the AP
1300 if (cpu_has_tsc
&& cpucount
&& cpu_khz
)
1301 synchronize_tsc_bp();
1304 /* These are wrappers to interface to the new boot process. Someone
1305 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1306 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1308 smp_commenced_mask
= cpumask_of_cpu(0);
1309 cpu_callin_map
= cpumask_of_cpu(0);
1311 smp_boot_cpus(max_cpus
);
1314 void __devinit
smp_prepare_boot_cpu(void)
1316 cpu_set(smp_processor_id(), cpu_online_map
);
1317 cpu_set(smp_processor_id(), cpu_callout_map
);
1318 cpu_set(smp_processor_id(), cpu_present_map
);
1319 cpu_set(smp_processor_id(), cpu_possible_map
);
1320 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
1323 #ifdef CONFIG_HOTPLUG_CPU
1325 remove_siblinginfo(int cpu
)
1328 struct cpuinfo_x86
*c
= cpu_data
;
1330 for_each_cpu_mask(sibling
, cpu_core_map
[cpu
]) {
1331 cpu_clear(cpu
, cpu_core_map
[sibling
]);
1333 * last thread sibling in this cpu core going down
1335 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1)
1336 c
[sibling
].booted_cores
--;
1339 for_each_cpu_mask(sibling
, cpu_sibling_map
[cpu
])
1340 cpu_clear(cpu
, cpu_sibling_map
[sibling
]);
1341 cpus_clear(cpu_sibling_map
[cpu
]);
1342 cpus_clear(cpu_core_map
[cpu
]);
1343 phys_proc_id
[cpu
] = BAD_APICID
;
1344 cpu_core_id
[cpu
] = BAD_APICID
;
1345 cpu_clear(cpu
, cpu_sibling_setup_map
);
1348 int __cpu_disable(void)
1350 cpumask_t map
= cpu_online_map
;
1351 int cpu
= smp_processor_id();
1354 * Perhaps use cpufreq to drop frequency, but that could go
1355 * into generic code.
1357 * We won't take down the boot processor on i386 due to some
1358 * interrupts only being able to be serviced by the BSP.
1359 * Especially so if we're not using an IOAPIC -zwane
1365 /* Allow any queued timer interrupts to get serviced */
1368 local_irq_disable();
1370 remove_siblinginfo(cpu
);
1372 cpu_clear(cpu
, map
);
1374 /* It's now safe to remove this processor from the online map */
1375 cpu_clear(cpu
, cpu_online_map
);
1379 void __cpu_die(unsigned int cpu
)
1381 /* We don't do anything here: idle task is faking death itself. */
1384 for (i
= 0; i
< 10; i
++) {
1385 /* They ack this in play_dead by setting CPU_DEAD */
1386 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1387 printk ("CPU %d is now offline\n", cpu
);
1388 if (1 == num_online_cpus())
1389 alternatives_smp_switch(0);
1394 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1396 #else /* ... !CONFIG_HOTPLUG_CPU */
1397 int __cpu_disable(void)
1402 void __cpu_die(unsigned int cpu
)
1404 /* We said "no" in __cpu_disable */
1407 #endif /* CONFIG_HOTPLUG_CPU */
1409 int __devinit
__cpu_up(unsigned int cpu
)
1411 #ifdef CONFIG_HOTPLUG_CPU
1415 * We do warm boot only on cpus that had booted earlier
1416 * Otherwise cold boot is all handled from smp_boot_cpus().
1417 * cpu_callin_map is set during AP kickstart process. Its reset
1418 * when a cpu is taken offline from cpu_exit_clear().
1420 if (!cpu_isset(cpu
, cpu_callin_map
))
1421 ret
= __smp_prepare_cpu(cpu
);
1427 /* In case one didn't come up */
1428 if (!cpu_isset(cpu
, cpu_callin_map
)) {
1429 printk(KERN_DEBUG
"skipping cpu%d, didn't come online\n", cpu
);
1435 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
1436 /* Unleash the CPU! */
1437 cpu_set(cpu
, smp_commenced_mask
);
1438 while (!cpu_isset(cpu
, cpu_online_map
))
1443 void __init
smp_cpus_done(unsigned int max_cpus
)
1445 #ifdef CONFIG_X86_IO_APIC
1446 setup_ioapic_dest();
1449 #ifndef CONFIG_HOTPLUG_CPU
1451 * Disable executability of the SMP trampoline:
1453 set_kernel_exec((unsigned long)trampoline_base
, trampoline_exec
);
1457 void __init
smp_intr_init(void)
1460 * IRQ0 must be given a fixed assignment and initialized,
1461 * because it's used before the IO-APIC is set up.
1463 set_intr_gate(FIRST_DEVICE_VECTOR
, interrupt
[0]);
1466 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1467 * IPI, driven by wakeup.
1469 set_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
1471 /* IPI for invalidation */
1472 set_intr_gate(INVALIDATE_TLB_VECTOR
, invalidate_interrupt
);
1474 /* IPI for generic function call */
1475 set_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);