2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/init.h>
39 #include <linux/kernel.h>
42 #include <linux/sched.h>
43 #include <linux/kernel_stat.h>
44 #include <linux/smp_lock.h>
45 #include <linux/bootmem.h>
46 #include <linux/notifier.h>
47 #include <linux/cpu.h>
48 #include <linux/percpu.h>
50 #include <linux/delay.h>
51 #include <linux/mc146818rtc.h>
52 #include <asm/tlbflush.h>
54 #include <asm/arch_hooks.h>
56 #include <mach_apic.h>
57 #include <mach_wakecpu.h>
58 #include <smpboot_hooks.h>
60 /* Set if we find a B stepping CPU */
61 static int __devinitdata smp_b_stepping
;
63 /* Number of siblings per CPU package */
64 int smp_num_siblings
= 1;
66 EXPORT_SYMBOL(smp_num_siblings
);
69 /* Package ID of each logical CPU */
70 int phys_proc_id
[NR_CPUS
] __read_mostly
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
72 /* Core ID of each logical CPU */
73 int cpu_core_id
[NR_CPUS
] __read_mostly
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
75 cpumask_t cpu_sibling_map
[NR_CPUS
] __read_mostly
;
76 EXPORT_SYMBOL(cpu_sibling_map
);
78 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
;
79 EXPORT_SYMBOL(cpu_core_map
);
81 /* bitmap of online cpus */
82 cpumask_t cpu_online_map __read_mostly
;
83 EXPORT_SYMBOL(cpu_online_map
);
85 cpumask_t cpu_callin_map
;
86 cpumask_t cpu_callout_map
;
87 EXPORT_SYMBOL(cpu_callout_map
);
88 #ifdef CONFIG_HOTPLUG_CPU
89 cpumask_t cpu_possible_map
= CPU_MASK_ALL
;
91 cpumask_t cpu_possible_map
;
93 EXPORT_SYMBOL(cpu_possible_map
);
94 static cpumask_t smp_commenced_mask
;
96 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
97 * is no way to resync one AP against BP. TBD: for prescott and above, we
98 * should use IA64's algorithm
100 static int __devinitdata tsc_sync_disabled
;
102 /* Per CPU bogomips and other parameters */
103 struct cpuinfo_x86 cpu_data
[NR_CPUS
] __cacheline_aligned
;
104 EXPORT_SYMBOL(cpu_data
);
106 u8 x86_cpu_to_apicid
[NR_CPUS
] __read_mostly
=
107 { [0 ... NR_CPUS
-1] = 0xff };
108 EXPORT_SYMBOL(x86_cpu_to_apicid
);
111 * Trampoline 80x86 program as an array.
114 extern unsigned char trampoline_data
[];
115 extern unsigned char trampoline_end
[];
116 static unsigned char *trampoline_base
;
117 static int trampoline_exec
;
119 static void map_cpu_to_logical_apicid(void);
121 /* State of each CPU. */
122 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
125 * Currently trivial. Write the real->protected mode
126 * bootstrap into the page concerned. The caller
127 * has made sure it's suitably aligned.
130 static unsigned long __devinit
setup_trampoline(void)
132 memcpy(trampoline_base
, trampoline_data
, trampoline_end
- trampoline_data
);
133 return virt_to_phys(trampoline_base
);
137 * We are called very early to get the low memory for the
138 * SMP bootup trampoline page.
140 void __init
smp_alloc_memory(void)
142 trampoline_base
= (void *) alloc_bootmem_low_pages(PAGE_SIZE
);
144 * Has to be in very low memory so we can execute
147 if (__pa(trampoline_base
) >= 0x9F000)
150 * Make the SMP trampoline executable:
152 trampoline_exec
= set_kernel_exec((unsigned long)trampoline_base
, 1);
156 * The bootstrap kernel entry code has set these up. Save them for
160 static void __devinit
smp_store_cpu_info(int id
)
162 struct cpuinfo_x86
*c
= cpu_data
+ id
;
168 * Mask B, Pentium, but not Pentium MMX
170 if (c
->x86_vendor
== X86_VENDOR_INTEL
&&
172 c
->x86_mask
>= 1 && c
->x86_mask
<= 4 &&
175 * Remember we have B step Pentia with bugs
180 * Certain Athlons might work (for various values of 'work') in SMP
181 * but they are not certified as MP capable.
183 if ((c
->x86_vendor
== X86_VENDOR_AMD
) && (c
->x86
== 6)) {
185 /* Athlon 660/661 is valid. */
186 if ((c
->x86_model
==6) && ((c
->x86_mask
==0) || (c
->x86_mask
==1)))
189 /* Duron 670 is valid */
190 if ((c
->x86_model
==7) && (c
->x86_mask
==0))
194 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
195 * It's worth noting that the A5 stepping (662) of some Athlon XP's
196 * have the MP bit set.
197 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
199 if (((c
->x86_model
==6) && (c
->x86_mask
>=2)) ||
200 ((c
->x86_model
==7) && (c
->x86_mask
>=1)) ||
205 /* If we get here, it's not a certified SMP capable AMD system. */
206 add_taint(TAINT_UNSAFE_SMP
);
214 * TSC synchronization.
216 * We first check whether all CPUs have their TSC's synchronized,
217 * then we print a warning if not, and always resync.
220 static atomic_t tsc_start_flag
= ATOMIC_INIT(0);
221 static atomic_t tsc_count_start
= ATOMIC_INIT(0);
222 static atomic_t tsc_count_stop
= ATOMIC_INIT(0);
223 static unsigned long long tsc_values
[NR_CPUS
];
227 static void __init
synchronize_tsc_bp (void)
230 unsigned long long t0
;
231 unsigned long long sum
, avg
;
233 unsigned int one_usec
;
236 printk(KERN_INFO
"checking TSC synchronization across %u CPUs: ", num_booting_cpus());
238 /* convert from kcyc/sec to cyc/usec */
239 one_usec
= cpu_khz
/ 1000;
241 atomic_set(&tsc_start_flag
, 1);
245 * We loop a few times to get a primed instruction cache,
246 * then the last pass is more or less synchronized and
247 * the BP and APs set their cycle counters to zero all at
248 * once. This reduces the chance of having random offsets
249 * between the processors, and guarantees that the maximum
250 * delay between the cycle counters is never bigger than
251 * the latency of information-passing (cachelines) between
254 for (i
= 0; i
< NR_LOOPS
; i
++) {
256 * all APs synchronize but they loop on '== num_cpus'
258 while (atomic_read(&tsc_count_start
) != num_booting_cpus()-1)
260 atomic_set(&tsc_count_stop
, 0);
263 * this lets the APs save their current TSC:
265 atomic_inc(&tsc_count_start
);
267 rdtscll(tsc_values
[smp_processor_id()]);
269 * We clear the TSC in the last loop:
275 * Wait for all APs to leave the synchronization point:
277 while (atomic_read(&tsc_count_stop
) != num_booting_cpus()-1)
279 atomic_set(&tsc_count_start
, 0);
281 atomic_inc(&tsc_count_stop
);
285 for (i
= 0; i
< NR_CPUS
; i
++) {
286 if (cpu_isset(i
, cpu_callout_map
)) {
292 do_div(avg
, num_booting_cpus());
295 for (i
= 0; i
< NR_CPUS
; i
++) {
296 if (!cpu_isset(i
, cpu_callout_map
))
298 delta
= tsc_values
[i
] - avg
;
302 * We report bigger than 2 microseconds clock differences.
304 if (delta
> 2*one_usec
) {
311 do_div(realdelta
, one_usec
);
312 if (tsc_values
[i
] < avg
)
313 realdelta
= -realdelta
;
315 printk(KERN_INFO
"CPU#%d had %ld usecs TSC skew, fixed it up.\n", i
, realdelta
);
324 static void __init
synchronize_tsc_ap (void)
329 * Not every cpu is online at the time
330 * this gets called, so we first wait for the BP to
331 * finish SMP initialization:
333 while (!atomic_read(&tsc_start_flag
)) mb();
335 for (i
= 0; i
< NR_LOOPS
; i
++) {
336 atomic_inc(&tsc_count_start
);
337 while (atomic_read(&tsc_count_start
) != num_booting_cpus())
340 rdtscll(tsc_values
[smp_processor_id()]);
344 atomic_inc(&tsc_count_stop
);
345 while (atomic_read(&tsc_count_stop
) != num_booting_cpus()) mb();
350 extern void calibrate_delay(void);
352 static atomic_t init_deasserted
;
354 static void __devinit
smp_callin(void)
357 unsigned long timeout
;
360 * If waken up by an INIT in an 82489DX configuration
361 * we may get here before an INIT-deassert IPI reaches
362 * our local APIC. We have to wait for the IPI or we'll
363 * lock up on an APIC access.
365 wait_for_init_deassert(&init_deasserted
);
368 * (This works even if the APIC is not enabled.)
370 phys_id
= GET_APIC_ID(apic_read(APIC_ID
));
371 cpuid
= smp_processor_id();
372 if (cpu_isset(cpuid
, cpu_callin_map
)) {
373 printk("huh, phys CPU#%d, CPU#%d already present??\n",
377 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
380 * STARTUP IPIs are fragile beasts as they might sometimes
381 * trigger some glue motherboard logic. Complete APIC bus
382 * silence for 1 second, this overestimates the time the
383 * boot CPU is spending to send the up to 2 STARTUP IPIs
384 * by a factor of two. This should be enough.
388 * Waiting 2s total for startup (udelay is not yet working)
390 timeout
= jiffies
+ 2*HZ
;
391 while (time_before(jiffies
, timeout
)) {
393 * Has the boot CPU finished it's STARTUP sequence?
395 if (cpu_isset(cpuid
, cpu_callout_map
))
400 if (!time_before(jiffies
, timeout
)) {
401 printk("BUG: CPU%d started up but did not get a callout!\n",
407 * the boot CPU has finished the init stage and is spinning
408 * on callin_map until we finish. We are free to set up this
409 * CPU, first the APIC. (this is probably redundant on most
413 Dprintk("CALLIN, before setup_local_APIC().\n");
414 smp_callin_clear_local_apic();
416 map_cpu_to_logical_apicid();
422 Dprintk("Stack at about %p\n",&cpuid
);
425 * Save our processor parameters
427 smp_store_cpu_info(cpuid
);
429 disable_APIC_timer();
432 * Allow the master to continue.
434 cpu_set(cpuid
, cpu_callin_map
);
437 * Synchronize the TSC with the BP
439 if (cpu_has_tsc
&& cpu_khz
&& !tsc_sync_disabled
)
440 synchronize_tsc_ap();
446 set_cpu_sibling_map(int cpu
)
450 if (smp_num_siblings
> 1) {
451 for (i
= 0; i
< NR_CPUS
; i
++) {
452 if (!cpu_isset(i
, cpu_callout_map
))
454 if (cpu_core_id
[cpu
] == cpu_core_id
[i
]) {
455 cpu_set(i
, cpu_sibling_map
[cpu
]);
456 cpu_set(cpu
, cpu_sibling_map
[i
]);
460 cpu_set(cpu
, cpu_sibling_map
[cpu
]);
463 if (current_cpu_data
.x86_num_cores
> 1) {
464 for (i
= 0; i
< NR_CPUS
; i
++) {
465 if (!cpu_isset(i
, cpu_callout_map
))
467 if (phys_proc_id
[cpu
] == phys_proc_id
[i
]) {
468 cpu_set(i
, cpu_core_map
[cpu
]);
469 cpu_set(cpu
, cpu_core_map
[i
]);
473 cpu_core_map
[cpu
] = cpu_sibling_map
[cpu
];
478 * Activate a secondary processor.
480 static void __devinit
start_secondary(void *unused
)
483 * Dont put anything before smp_callin(), SMP
484 * booting is too fragile that we want to limit the
485 * things done here to the most necessary things.
489 while (!cpu_isset(smp_processor_id(), smp_commenced_mask
))
491 setup_secondary_APIC_clock();
492 if (nmi_watchdog
== NMI_IO_APIC
) {
493 disable_8259A_irq(0);
494 enable_NMI_through_LVT0(NULL
);
499 * low-memory mappings have been cleared, flush them from
500 * the local TLBs too.
504 /* This must be done before setting cpu_online_map */
505 set_cpu_sibling_map(raw_smp_processor_id());
509 * We need to hold call_lock, so there is no inconsistency
510 * between the time smp_call_function() determines number of
511 * IPI receipients, and the time when the determination is made
512 * for which cpus receive the IPI. Holding this
513 * lock helps us to not include this cpu in a currently in progress
514 * smp_call_function().
516 lock_ipi_call_lock();
517 cpu_set(smp_processor_id(), cpu_online_map
);
518 unlock_ipi_call_lock();
519 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
521 /* We can take interrupts now: we're officially "up". */
529 * Everything has been set up for the secondary
530 * CPUs - they just need to reload everything
531 * from the task structure
532 * This function must not return.
534 void __devinit
initialize_secondary(void)
537 * We don't actually need to load the full TSS,
538 * basically just the stack pointer and the eip.
545 :"r" (current
->thread
.esp
),"r" (current
->thread
.eip
));
555 /* which logical CPUs are on which nodes */
556 cpumask_t node_2_cpu_mask
[MAX_NUMNODES
] __read_mostly
=
557 { [0 ... MAX_NUMNODES
-1] = CPU_MASK_NONE
};
558 /* which node each logical CPU is on */
559 int cpu_2_node
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = 0 };
560 EXPORT_SYMBOL(cpu_2_node
);
562 /* set up a mapping between cpu and node. */
563 static inline void map_cpu_to_node(int cpu
, int node
)
565 printk("Mapping cpu %d to node %d\n", cpu
, node
);
566 cpu_set(cpu
, node_2_cpu_mask
[node
]);
567 cpu_2_node
[cpu
] = node
;
570 /* undo a mapping between cpu and node. */
571 static inline void unmap_cpu_to_node(int cpu
)
575 printk("Unmapping cpu %d from all nodes\n", cpu
);
576 for (node
= 0; node
< MAX_NUMNODES
; node
++)
577 cpu_clear(cpu
, node_2_cpu_mask
[node
]);
580 #else /* !CONFIG_NUMA */
582 #define map_cpu_to_node(cpu, node) ({})
583 #define unmap_cpu_to_node(cpu) ({})
585 #endif /* CONFIG_NUMA */
587 u8 cpu_2_logical_apicid
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = BAD_APICID
};
589 static void map_cpu_to_logical_apicid(void)
591 int cpu
= smp_processor_id();
592 int apicid
= logical_smp_processor_id();
594 cpu_2_logical_apicid
[cpu
] = apicid
;
595 map_cpu_to_node(cpu
, apicid_to_node(apicid
));
598 static void unmap_cpu_to_logical_apicid(int cpu
)
600 cpu_2_logical_apicid
[cpu
] = BAD_APICID
;
601 unmap_cpu_to_node(cpu
);
605 static inline void __inquire_remote_apic(int apicid
)
607 int i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
608 char *names
[] = { "ID", "VERSION", "SPIV" };
611 printk("Inquiring remote APIC #%d...\n", apicid
);
613 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
614 printk("... APIC #%d %s: ", apicid
, names
[i
]);
619 apic_wait_icr_idle();
621 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(apicid
));
622 apic_write_around(APIC_ICR
, APIC_DM_REMRD
| regs
[i
]);
627 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
628 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
631 case APIC_ICR_RR_VALID
:
632 status
= apic_read(APIC_RRR
);
633 printk("%08x\n", status
);
642 #ifdef WAKE_SECONDARY_VIA_NMI
644 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
645 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
646 * won't ... remember to clear down the APIC, etc later.
649 wakeup_secondary_cpu(int logical_apicid
, unsigned long start_eip
)
651 unsigned long send_status
= 0, accept_status
= 0;
655 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(logical_apicid
));
657 /* Boot on the stack */
658 /* Kick the second */
659 apic_write_around(APIC_ICR
, APIC_DM_NMI
| APIC_DEST_LOGICAL
);
661 Dprintk("Waiting for send to finish...\n");
666 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
667 } while (send_status
&& (timeout
++ < 1000));
670 * Give the other CPU some time to accept the IPI.
674 * Due to the Pentium erratum 3AP.
676 maxlvt
= get_maxlvt();
678 apic_read_around(APIC_SPIV
);
679 apic_write(APIC_ESR
, 0);
681 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
682 Dprintk("NMI sent.\n");
685 printk("APIC never delivered???\n");
687 printk("APIC delivery error (%lx).\n", accept_status
);
689 return (send_status
| accept_status
);
691 #endif /* WAKE_SECONDARY_VIA_NMI */
693 #ifdef WAKE_SECONDARY_VIA_INIT
695 wakeup_secondary_cpu(int phys_apicid
, unsigned long start_eip
)
697 unsigned long send_status
= 0, accept_status
= 0;
698 int maxlvt
, timeout
, num_starts
, j
;
701 * Be paranoid about clearing APIC errors.
703 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
704 apic_read_around(APIC_SPIV
);
705 apic_write(APIC_ESR
, 0);
709 Dprintk("Asserting INIT.\n");
712 * Turn INIT on target chip
714 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
719 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
722 Dprintk("Waiting for send to finish...\n");
727 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
728 } while (send_status
&& (timeout
++ < 1000));
732 Dprintk("Deasserting INIT.\n");
735 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
738 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
740 Dprintk("Waiting for send to finish...\n");
745 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
746 } while (send_status
&& (timeout
++ < 1000));
748 atomic_set(&init_deasserted
, 1);
751 * Should we send STARTUP IPIs ?
753 * Determine this based on the APIC version.
754 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
756 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
762 * Run STARTUP IPI loop.
764 Dprintk("#startup loops: %d.\n", num_starts
);
766 maxlvt
= get_maxlvt();
768 for (j
= 1; j
<= num_starts
; j
++) {
769 Dprintk("Sending STARTUP #%d.\n",j
);
770 apic_read_around(APIC_SPIV
);
771 apic_write(APIC_ESR
, 0);
773 Dprintk("After apic_write.\n");
780 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
782 /* Boot on the stack */
783 /* Kick the second */
784 apic_write_around(APIC_ICR
, APIC_DM_STARTUP
785 | (start_eip
>> 12));
788 * Give the other CPU some time to accept the IPI.
792 Dprintk("Startup point 1.\n");
794 Dprintk("Waiting for send to finish...\n");
799 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
800 } while (send_status
&& (timeout
++ < 1000));
803 * Give the other CPU some time to accept the IPI.
807 * Due to the Pentium erratum 3AP.
810 apic_read_around(APIC_SPIV
);
811 apic_write(APIC_ESR
, 0);
813 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
814 if (send_status
|| accept_status
)
817 Dprintk("After Startup.\n");
820 printk("APIC never delivered???\n");
822 printk("APIC delivery error (%lx).\n", accept_status
);
824 return (send_status
| accept_status
);
826 #endif /* WAKE_SECONDARY_VIA_INIT */
828 extern cpumask_t cpu_initialized
;
829 static inline int alloc_cpu_id(void)
833 cpus_complement(tmp_map
, cpu_present_map
);
834 cpu
= first_cpu(tmp_map
);
840 #ifdef CONFIG_HOTPLUG_CPU
841 static struct task_struct
* __devinitdata cpu_idle_tasks
[NR_CPUS
];
842 static inline struct task_struct
* alloc_idle_task(int cpu
)
844 struct task_struct
*idle
;
846 if ((idle
= cpu_idle_tasks
[cpu
]) != NULL
) {
847 /* initialize thread_struct. we really want to avoid destroy
850 idle
->thread
.esp
= (unsigned long)(((struct pt_regs
*)
851 (THREAD_SIZE
+ (unsigned long) idle
->thread_info
)) - 1);
852 init_idle(idle
, cpu
);
855 idle
= fork_idle(cpu
);
858 cpu_idle_tasks
[cpu
] = idle
;
862 #define alloc_idle_task(cpu) fork_idle(cpu)
865 static int __devinit
do_boot_cpu(int apicid
, int cpu
)
867 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
868 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
869 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
872 struct task_struct
*idle
;
873 unsigned long boot_error
;
875 unsigned long start_eip
;
876 unsigned short nmi_high
= 0, nmi_low
= 0;
881 * We can't use kernel_thread since we must avoid to
882 * reschedule the child.
884 idle
= alloc_idle_task(cpu
);
886 panic("failed fork for CPU %d", cpu
);
887 idle
->thread
.eip
= (unsigned long) start_secondary
;
888 /* start_eip had better be page-aligned! */
889 start_eip
= setup_trampoline();
891 /* So we see what's up */
892 printk("Booting processor %d/%d eip %lx\n", cpu
, apicid
, start_eip
);
893 /* Stack for startup_32 can be just as for start_secondary onwards */
894 stack_start
.esp
= (void *) idle
->thread
.esp
;
899 * This grunge runs the startup process for
900 * the targeted processor.
903 atomic_set(&init_deasserted
, 0);
905 Dprintk("Setting warm reset code and vector.\n");
907 store_NMI_vector(&nmi_high
, &nmi_low
);
909 smpboot_setup_warm_reset_vector(start_eip
);
912 * Starting actual IPI sequence...
914 boot_error
= wakeup_secondary_cpu(apicid
, start_eip
);
918 * allow APs to start initializing.
920 Dprintk("Before Callout %d.\n", cpu
);
921 cpu_set(cpu
, cpu_callout_map
);
922 Dprintk("After Callout %d.\n", cpu
);
925 * Wait 5s total for a response
927 for (timeout
= 0; timeout
< 50000; timeout
++) {
928 if (cpu_isset(cpu
, cpu_callin_map
))
929 break; /* It has booted */
933 if (cpu_isset(cpu
, cpu_callin_map
)) {
934 /* number CPUs logically, starting from 1 (BSP is 0) */
936 printk("CPU%d: ", cpu
);
937 print_cpu_info(&cpu_data
[cpu
]);
938 Dprintk("CPU has booted.\n");
941 if (*((volatile unsigned char *)trampoline_base
)
943 /* trampoline started but...? */
944 printk("Stuck ??\n");
946 /* trampoline code not run */
947 printk("Not responding.\n");
948 inquire_remote_apic(apicid
);
953 /* Try to put things back the way they were before ... */
954 unmap_cpu_to_logical_apicid(cpu
);
955 cpu_clear(cpu
, cpu_callout_map
); /* was set here (do_boot_cpu()) */
956 cpu_clear(cpu
, cpu_initialized
); /* was set by cpu_init() */
959 x86_cpu_to_apicid
[cpu
] = apicid
;
960 cpu_set(cpu
, cpu_present_map
);
963 /* mark "stuck" area as not stuck */
964 *((volatile unsigned long *)trampoline_base
) = 0;
969 #ifdef CONFIG_HOTPLUG_CPU
970 void cpu_exit_clear(void)
972 int cpu
= raw_smp_processor_id();
980 cpu_clear(cpu
, cpu_callout_map
);
981 cpu_clear(cpu
, cpu_callin_map
);
982 cpu_clear(cpu
, cpu_present_map
);
984 cpu_clear(cpu
, smp_commenced_mask
);
985 unmap_cpu_to_logical_apicid(cpu
);
988 struct warm_boot_cpu_info
{
989 struct completion
*complete
;
994 static void __devinit
do_warm_boot_cpu(void *p
)
996 struct warm_boot_cpu_info
*info
= p
;
997 do_boot_cpu(info
->apicid
, info
->cpu
);
998 complete(info
->complete
);
1001 int __devinit
smp_prepare_cpu(int cpu
)
1003 DECLARE_COMPLETION(done
);
1004 struct warm_boot_cpu_info info
;
1005 struct work_struct task
;
1009 apicid
= x86_cpu_to_apicid
[cpu
];
1010 if (apicid
== BAD_APICID
) {
1015 info
.complete
= &done
;
1016 info
.apicid
= apicid
;
1018 INIT_WORK(&task
, do_warm_boot_cpu
, &info
);
1020 tsc_sync_disabled
= 1;
1022 /* init low mem mapping */
1023 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ USER_PGD_PTRS
,
1026 schedule_work(&task
);
1027 wait_for_completion(&done
);
1029 tsc_sync_disabled
= 0;
1033 unlock_cpu_hotplug();
1038 static void smp_tune_scheduling (void)
1040 unsigned long cachesize
; /* kB */
1041 unsigned long bandwidth
= 350; /* MB/s */
1043 * Rough estimation for SMP scheduling, this is the number of
1044 * cycles it takes for a fully memory-limited process to flush
1045 * the SMP-local cache.
1047 * (For a P5 this pretty much means we will choose another idle
1048 * CPU almost always at wakeup time (this is due to the small
1049 * L1 cache), on PIIs it's around 50-100 usecs, depending on
1055 * this basically disables processor-affinity
1056 * scheduling on SMP without a TSC.
1060 cachesize
= boot_cpu_data
.x86_cache_size
;
1061 if (cachesize
== -1) {
1062 cachesize
= 16; /* Pentiums, 2x8kB cache */
1069 * Cycle through the processors sending APIC IPIs to boot each.
1072 static int boot_cpu_logical_apicid
;
1073 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1075 #ifdef CONFIG_X86_NUMAQ
1076 EXPORT_SYMBOL(xquad_portio
);
1079 static void __init
smp_boot_cpus(unsigned int max_cpus
)
1081 int apicid
, cpu
, bit
, kicked
;
1082 unsigned long bogosum
= 0;
1085 * Setup boot CPU information
1087 smp_store_cpu_info(0); /* Final full version of the data */
1088 printk("CPU%d: ", 0);
1089 print_cpu_info(&cpu_data
[0]);
1091 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1092 boot_cpu_logical_apicid
= logical_smp_processor_id();
1093 x86_cpu_to_apicid
[0] = boot_cpu_physical_apicid
;
1095 current_thread_info()->cpu
= 0;
1096 smp_tune_scheduling();
1097 cpus_clear(cpu_sibling_map
[0]);
1098 cpu_set(0, cpu_sibling_map
[0]);
1100 cpus_clear(cpu_core_map
[0]);
1101 cpu_set(0, cpu_core_map
[0]);
1104 * If we couldn't find an SMP configuration at boot time,
1105 * get out of here now!
1107 if (!smp_found_config
&& !acpi_lapic
) {
1108 printk(KERN_NOTICE
"SMP motherboard not detected.\n");
1109 smpboot_clear_io_apic_irqs();
1110 phys_cpu_present_map
= physid_mask_of_physid(0);
1111 if (APIC_init_uniprocessor())
1112 printk(KERN_NOTICE
"Local APIC not detected."
1113 " Using dummy APIC emulation.\n");
1114 map_cpu_to_logical_apicid();
1115 cpu_set(0, cpu_sibling_map
[0]);
1116 cpu_set(0, cpu_core_map
[0]);
1121 * Should not be necessary because the MP table should list the boot
1122 * CPU too, but we do it for the sake of robustness anyway.
1123 * Makes no sense to do this check in clustered apic mode, so skip it
1125 if (!check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1126 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1127 boot_cpu_physical_apicid
);
1128 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1132 * If we couldn't find a local APIC, then get out of here now!
1134 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) && !cpu_has_apic
) {
1135 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1136 boot_cpu_physical_apicid
);
1137 printk(KERN_ERR
"... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1138 smpboot_clear_io_apic_irqs();
1139 phys_cpu_present_map
= physid_mask_of_physid(0);
1140 cpu_set(0, cpu_sibling_map
[0]);
1141 cpu_set(0, cpu_core_map
[0]);
1145 verify_local_APIC();
1148 * If SMP should be disabled, then really disable it!
1151 smp_found_config
= 0;
1152 printk(KERN_INFO
"SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1153 smpboot_clear_io_apic_irqs();
1154 phys_cpu_present_map
= physid_mask_of_physid(0);
1155 cpu_set(0, cpu_sibling_map
[0]);
1156 cpu_set(0, cpu_core_map
[0]);
1162 map_cpu_to_logical_apicid();
1165 setup_portio_remap();
1168 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1170 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1171 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1172 * clustered apic ID.
1174 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map
));
1177 for (bit
= 0; kicked
< NR_CPUS
&& bit
< MAX_APICS
; bit
++) {
1178 apicid
= cpu_present_to_apicid(bit
);
1180 * Don't even attempt to start the boot CPU!
1182 if ((apicid
== boot_cpu_apicid
) || (apicid
== BAD_APICID
))
1185 if (!check_apicid_present(bit
))
1187 if (max_cpus
<= cpucount
+1)
1190 if (((cpu
= alloc_cpu_id()) <= 0) || do_boot_cpu(apicid
, cpu
))
1191 printk("CPU #%d not responding - cannot use it.\n",
1198 * Cleanup possible dangling ends...
1200 smpboot_restore_warm_reset_vector();
1203 * Allow the user to impress friends.
1205 Dprintk("Before bogomips.\n");
1206 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++)
1207 if (cpu_isset(cpu
, cpu_callout_map
))
1208 bogosum
+= cpu_data
[cpu
].loops_per_jiffy
;
1210 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1212 bogosum
/(500000/HZ
),
1213 (bogosum
/(5000/HZ
))%100);
1215 Dprintk("Before bogocount - setting activated=1.\n");
1218 printk(KERN_WARNING
"WARNING: SMP operation may be unreliable with B stepping processors.\n");
1221 * Don't taint if we are running SMP kernel on a single non-MP
1224 if (tainted
& TAINT_UNSAFE_SMP
) {
1226 printk (KERN_INFO
"WARNING: This combination of AMD processors is not suitable for SMP.\n");
1228 tainted
&= ~TAINT_UNSAFE_SMP
;
1231 Dprintk("Boot done.\n");
1234 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1237 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++) {
1238 cpus_clear(cpu_sibling_map
[cpu
]);
1239 cpus_clear(cpu_core_map
[cpu
]);
1242 cpu_set(0, cpu_sibling_map
[0]);
1243 cpu_set(0, cpu_core_map
[0]);
1245 smpboot_setup_io_apic();
1247 setup_boot_APIC_clock();
1250 * Synchronize the TSC with the AP
1252 if (cpu_has_tsc
&& cpucount
&& cpu_khz
)
1253 synchronize_tsc_bp();
1256 /* These are wrappers to interface to the new boot process. Someone
1257 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1258 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1260 smp_commenced_mask
= cpumask_of_cpu(0);
1261 cpu_callin_map
= cpumask_of_cpu(0);
1263 smp_boot_cpus(max_cpus
);
1266 void __devinit
smp_prepare_boot_cpu(void)
1268 cpu_set(smp_processor_id(), cpu_online_map
);
1269 cpu_set(smp_processor_id(), cpu_callout_map
);
1270 cpu_set(smp_processor_id(), cpu_present_map
);
1271 cpu_set(smp_processor_id(), cpu_possible_map
);
1272 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
1275 #ifdef CONFIG_HOTPLUG_CPU
1277 remove_siblinginfo(int cpu
)
1281 for_each_cpu_mask(sibling
, cpu_sibling_map
[cpu
])
1282 cpu_clear(cpu
, cpu_sibling_map
[sibling
]);
1283 for_each_cpu_mask(sibling
, cpu_core_map
[cpu
])
1284 cpu_clear(cpu
, cpu_core_map
[sibling
]);
1285 cpus_clear(cpu_sibling_map
[cpu
]);
1286 cpus_clear(cpu_core_map
[cpu
]);
1287 phys_proc_id
[cpu
] = BAD_APICID
;
1288 cpu_core_id
[cpu
] = BAD_APICID
;
1291 int __cpu_disable(void)
1293 cpumask_t map
= cpu_online_map
;
1294 int cpu
= smp_processor_id();
1297 * Perhaps use cpufreq to drop frequency, but that could go
1298 * into generic code.
1300 * We won't take down the boot processor on i386 due to some
1301 * interrupts only being able to be serviced by the BSP.
1302 * Especially so if we're not using an IOAPIC -zwane
1307 /* We enable the timer again on the exit path of the death loop */
1308 disable_APIC_timer();
1309 /* Allow any queued timer interrupts to get serviced */
1312 local_irq_disable();
1314 remove_siblinginfo(cpu
);
1316 cpu_clear(cpu
, map
);
1318 /* It's now safe to remove this processor from the online map */
1319 cpu_clear(cpu
, cpu_online_map
);
1323 void __cpu_die(unsigned int cpu
)
1325 /* We don't do anything here: idle task is faking death itself. */
1328 for (i
= 0; i
< 10; i
++) {
1329 /* They ack this in play_dead by setting CPU_DEAD */
1330 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1331 printk ("CPU %d is now offline\n", cpu
);
1336 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1338 #else /* ... !CONFIG_HOTPLUG_CPU */
1339 int __cpu_disable(void)
1344 void __cpu_die(unsigned int cpu
)
1346 /* We said "no" in __cpu_disable */
1349 #endif /* CONFIG_HOTPLUG_CPU */
1351 int __devinit
__cpu_up(unsigned int cpu
)
1353 /* In case one didn't come up */
1354 if (!cpu_isset(cpu
, cpu_callin_map
)) {
1355 printk(KERN_DEBUG
"skipping cpu%d, didn't come online\n", cpu
);
1361 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
1362 /* Unleash the CPU! */
1363 cpu_set(cpu
, smp_commenced_mask
);
1364 while (!cpu_isset(cpu
, cpu_online_map
))
1369 void __init
smp_cpus_done(unsigned int max_cpus
)
1371 #ifdef CONFIG_X86_IO_APIC
1372 setup_ioapic_dest();
1375 #ifndef CONFIG_HOTPLUG_CPU
1377 * Disable executability of the SMP trampoline:
1379 set_kernel_exec((unsigned long)trampoline_base
, trampoline_exec
);
1383 void __init
smp_intr_init(void)
1386 * IRQ0 must be given a fixed assignment and initialized,
1387 * because it's used before the IO-APIC is set up.
1389 set_intr_gate(FIRST_DEVICE_VECTOR
, interrupt
[0]);
1392 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1393 * IPI, driven by wakeup.
1395 set_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
1397 /* IPI for invalidation */
1398 set_intr_gate(INVALIDATE_TLB_VECTOR
, invalidate_interrupt
);
1400 /* IPI for generic function call */
1401 set_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);