2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/kernel.h>
41 #include <linux/sched.h>
42 #include <linux/kernel_stat.h>
43 #include <linux/smp_lock.h>
44 #include <linux/bootmem.h>
45 #include <linux/notifier.h>
46 #include <linux/cpu.h>
47 #include <linux/percpu.h>
49 #include <linux/delay.h>
50 #include <linux/mc146818rtc.h>
51 #include <asm/tlbflush.h>
53 #include <asm/arch_hooks.h>
56 #include <mach_apic.h>
57 #include <mach_wakecpu.h>
58 #include <smpboot_hooks.h>
60 /* Set if we find a B stepping CPU */
61 static int __devinitdata smp_b_stepping
;
63 /* Number of siblings per CPU package */
64 int smp_num_siblings
= 1;
66 EXPORT_SYMBOL(smp_num_siblings
);
69 /* Last level cache ID of each logical CPU */
70 int cpu_llc_id
[NR_CPUS
] __cpuinitdata
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
72 /* representing HT siblings of each logical CPU */
73 cpumask_t cpu_sibling_map
[NR_CPUS
] __read_mostly
;
74 EXPORT_SYMBOL(cpu_sibling_map
);
76 /* representing HT and core siblings of each logical CPU */
77 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
;
78 EXPORT_SYMBOL(cpu_core_map
);
80 /* bitmap of online cpus */
81 cpumask_t cpu_online_map __read_mostly
;
82 EXPORT_SYMBOL(cpu_online_map
);
84 cpumask_t cpu_callin_map
;
85 cpumask_t cpu_callout_map
;
86 EXPORT_SYMBOL(cpu_callout_map
);
87 cpumask_t cpu_possible_map
;
88 EXPORT_SYMBOL(cpu_possible_map
);
89 static cpumask_t smp_commenced_mask
;
91 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
92 * is no way to resync one AP against BP. TBD: for prescott and above, we
93 * should use IA64's algorithm
95 static int __devinitdata tsc_sync_disabled
;
97 /* Per CPU bogomips and other parameters */
98 struct cpuinfo_x86 cpu_data
[NR_CPUS
] __cacheline_aligned
;
99 EXPORT_SYMBOL(cpu_data
);
101 u8 x86_cpu_to_apicid
[NR_CPUS
] __read_mostly
=
102 { [0 ... NR_CPUS
-1] = 0xff };
103 EXPORT_SYMBOL(x86_cpu_to_apicid
);
106 * Trampoline 80x86 program as an array.
109 extern unsigned char trampoline_data
[];
110 extern unsigned char trampoline_end
[];
111 static unsigned char *trampoline_base
;
112 static int trampoline_exec
;
114 static void map_cpu_to_logical_apicid(void);
116 /* State of each CPU. */
117 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
120 * Currently trivial. Write the real->protected mode
121 * bootstrap into the page concerned. The caller
122 * has made sure it's suitably aligned.
125 static unsigned long __devinit
setup_trampoline(void)
127 memcpy(trampoline_base
, trampoline_data
, trampoline_end
- trampoline_data
);
128 return virt_to_phys(trampoline_base
);
132 * We are called very early to get the low memory for the
133 * SMP bootup trampoline page.
135 void __init
smp_alloc_memory(void)
137 trampoline_base
= (void *) alloc_bootmem_low_pages(PAGE_SIZE
);
139 * Has to be in very low memory so we can execute
142 if (__pa(trampoline_base
) >= 0x9F000)
145 * Make the SMP trampoline executable:
147 trampoline_exec
= set_kernel_exec((unsigned long)trampoline_base
, 1);
151 * The bootstrap kernel entry code has set these up. Save them for
155 static void __devinit
smp_store_cpu_info(int id
)
157 struct cpuinfo_x86
*c
= cpu_data
+ id
;
163 * Mask B, Pentium, but not Pentium MMX
165 if (c
->x86_vendor
== X86_VENDOR_INTEL
&&
167 c
->x86_mask
>= 1 && c
->x86_mask
<= 4 &&
170 * Remember we have B step Pentia with bugs
175 * Certain Athlons might work (for various values of 'work') in SMP
176 * but they are not certified as MP capable.
178 if ((c
->x86_vendor
== X86_VENDOR_AMD
) && (c
->x86
== 6)) {
180 /* Athlon 660/661 is valid. */
181 if ((c
->x86_model
==6) && ((c
->x86_mask
==0) || (c
->x86_mask
==1)))
184 /* Duron 670 is valid */
185 if ((c
->x86_model
==7) && (c
->x86_mask
==0))
189 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
190 * It's worth noting that the A5 stepping (662) of some Athlon XP's
191 * have the MP bit set.
192 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
194 if (((c
->x86_model
==6) && (c
->x86_mask
>=2)) ||
195 ((c
->x86_model
==7) && (c
->x86_mask
>=1)) ||
200 /* If we get here, it's not a certified SMP capable AMD system. */
201 add_taint(TAINT_UNSAFE_SMP
);
209 * TSC synchronization.
211 * We first check whether all CPUs have their TSC's synchronized,
212 * then we print a warning if not, and always resync.
217 atomic_t count_start
;
219 unsigned long long values
[NR_CPUS
];
221 .start_flag
= ATOMIC_INIT(0),
222 .count_start
= ATOMIC_INIT(0),
223 .count_stop
= ATOMIC_INIT(0),
228 static void __init
synchronize_tsc_bp(void)
231 unsigned long long t0
;
232 unsigned long long sum
, avg
;
234 unsigned int one_usec
;
237 printk(KERN_INFO
"checking TSC synchronization across %u CPUs: ", num_booting_cpus());
239 /* convert from kcyc/sec to cyc/usec */
240 one_usec
= cpu_khz
/ 1000;
242 atomic_set(&tsc
.start_flag
, 1);
246 * We loop a few times to get a primed instruction cache,
247 * then the last pass is more or less synchronized and
248 * the BP and APs set their cycle counters to zero all at
249 * once. This reduces the chance of having random offsets
250 * between the processors, and guarantees that the maximum
251 * delay between the cycle counters is never bigger than
252 * the latency of information-passing (cachelines) between
255 for (i
= 0; i
< NR_LOOPS
; i
++) {
257 * all APs synchronize but they loop on '== num_cpus'
259 while (atomic_read(&tsc
.count_start
) != num_booting_cpus()-1)
261 atomic_set(&tsc
.count_stop
, 0);
264 * this lets the APs save their current TSC:
266 atomic_inc(&tsc
.count_start
);
268 rdtscll(tsc
.values
[smp_processor_id()]);
270 * We clear the TSC in the last loop:
276 * Wait for all APs to leave the synchronization point:
278 while (atomic_read(&tsc
.count_stop
) != num_booting_cpus()-1)
280 atomic_set(&tsc
.count_start
, 0);
282 atomic_inc(&tsc
.count_stop
);
286 for (i
= 0; i
< NR_CPUS
; i
++) {
287 if (cpu_isset(i
, cpu_callout_map
)) {
293 do_div(avg
, num_booting_cpus());
295 for (i
= 0; i
< NR_CPUS
; i
++) {
296 if (!cpu_isset(i
, cpu_callout_map
))
298 delta
= tsc
.values
[i
] - avg
;
302 * We report bigger than 2 microseconds clock differences.
304 if (delta
> 2*one_usec
) {
312 do_div(realdelta
, one_usec
);
313 if (tsc
.values
[i
] < avg
)
314 realdelta
= -realdelta
;
317 printk(KERN_INFO
"CPU#%d had %Ld usecs TSC "
318 "skew, fixed it up.\n", i
, realdelta
);
325 static void __init
synchronize_tsc_ap(void)
330 * Not every cpu is online at the time
331 * this gets called, so we first wait for the BP to
332 * finish SMP initialization:
334 while (!atomic_read(&tsc
.start_flag
))
337 for (i
= 0; i
< NR_LOOPS
; i
++) {
338 atomic_inc(&tsc
.count_start
);
339 while (atomic_read(&tsc
.count_start
) != num_booting_cpus())
342 rdtscll(tsc
.values
[smp_processor_id()]);
346 atomic_inc(&tsc
.count_stop
);
347 while (atomic_read(&tsc
.count_stop
) != num_booting_cpus())
353 extern void calibrate_delay(void);
355 static atomic_t init_deasserted
;
357 static void __devinit
smp_callin(void)
360 unsigned long timeout
;
363 * If waken up by an INIT in an 82489DX configuration
364 * we may get here before an INIT-deassert IPI reaches
365 * our local APIC. We have to wait for the IPI or we'll
366 * lock up on an APIC access.
368 wait_for_init_deassert(&init_deasserted
);
371 * (This works even if the APIC is not enabled.)
373 phys_id
= GET_APIC_ID(apic_read(APIC_ID
));
374 cpuid
= smp_processor_id();
375 if (cpu_isset(cpuid
, cpu_callin_map
)) {
376 printk("huh, phys CPU#%d, CPU#%d already present??\n",
380 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
383 * STARTUP IPIs are fragile beasts as they might sometimes
384 * trigger some glue motherboard logic. Complete APIC bus
385 * silence for 1 second, this overestimates the time the
386 * boot CPU is spending to send the up to 2 STARTUP IPIs
387 * by a factor of two. This should be enough.
391 * Waiting 2s total for startup (udelay is not yet working)
393 timeout
= jiffies
+ 2*HZ
;
394 while (time_before(jiffies
, timeout
)) {
396 * Has the boot CPU finished it's STARTUP sequence?
398 if (cpu_isset(cpuid
, cpu_callout_map
))
403 if (!time_before(jiffies
, timeout
)) {
404 printk("BUG: CPU%d started up but did not get a callout!\n",
410 * the boot CPU has finished the init stage and is spinning
411 * on callin_map until we finish. We are free to set up this
412 * CPU, first the APIC. (this is probably redundant on most
416 Dprintk("CALLIN, before setup_local_APIC().\n");
417 smp_callin_clear_local_apic();
419 map_cpu_to_logical_apicid();
425 Dprintk("Stack at about %p\n",&cpuid
);
428 * Save our processor parameters
430 smp_store_cpu_info(cpuid
);
432 disable_APIC_timer();
435 * Allow the master to continue.
437 cpu_set(cpuid
, cpu_callin_map
);
440 * Synchronize the TSC with the BP
442 if (cpu_has_tsc
&& cpu_khz
&& !tsc_sync_disabled
)
443 synchronize_tsc_ap();
448 /* maps the cpu to the sched domain representing multi-core */
449 cpumask_t
cpu_coregroup_map(int cpu
)
451 struct cpuinfo_x86
*c
= cpu_data
+ cpu
;
453 * For perf, we return last level cache shared map.
454 * And for power savings, we return cpu_core_map
456 if (sched_mc_power_savings
|| sched_smt_power_savings
)
457 return cpu_core_map
[cpu
];
459 return c
->llc_shared_map
;
462 /* representing cpus for which sibling maps can be computed */
463 static cpumask_t cpu_sibling_setup_map
;
466 set_cpu_sibling_map(int cpu
)
469 struct cpuinfo_x86
*c
= cpu_data
;
471 cpu_set(cpu
, cpu_sibling_setup_map
);
473 if (smp_num_siblings
> 1) {
474 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
475 if (c
[cpu
].phys_proc_id
== c
[i
].phys_proc_id
&&
476 c
[cpu
].cpu_core_id
== c
[i
].cpu_core_id
) {
477 cpu_set(i
, cpu_sibling_map
[cpu
]);
478 cpu_set(cpu
, cpu_sibling_map
[i
]);
479 cpu_set(i
, cpu_core_map
[cpu
]);
480 cpu_set(cpu
, cpu_core_map
[i
]);
481 cpu_set(i
, c
[cpu
].llc_shared_map
);
482 cpu_set(cpu
, c
[i
].llc_shared_map
);
486 cpu_set(cpu
, cpu_sibling_map
[cpu
]);
489 cpu_set(cpu
, c
[cpu
].llc_shared_map
);
491 if (current_cpu_data
.x86_max_cores
== 1) {
492 cpu_core_map
[cpu
] = cpu_sibling_map
[cpu
];
493 c
[cpu
].booted_cores
= 1;
497 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
498 if (cpu_llc_id
[cpu
] != BAD_APICID
&&
499 cpu_llc_id
[cpu
] == cpu_llc_id
[i
]) {
500 cpu_set(i
, c
[cpu
].llc_shared_map
);
501 cpu_set(cpu
, c
[i
].llc_shared_map
);
503 if (c
[cpu
].phys_proc_id
== c
[i
].phys_proc_id
) {
504 cpu_set(i
, cpu_core_map
[cpu
]);
505 cpu_set(cpu
, cpu_core_map
[i
]);
507 * Does this new cpu bringup a new core?
509 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1) {
511 * for each core in package, increment
512 * the booted_cores for this new cpu
514 if (first_cpu(cpu_sibling_map
[i
]) == i
)
515 c
[cpu
].booted_cores
++;
517 * increment the core count for all
518 * the other cpus in this package
522 } else if (i
!= cpu
&& !c
[cpu
].booted_cores
)
523 c
[cpu
].booted_cores
= c
[i
].booted_cores
;
529 * Activate a secondary processor.
531 static void __devinit
start_secondary(void *unused
)
534 * Dont put anything before smp_callin(), SMP
535 * booting is too fragile that we want to limit the
536 * things done here to the most necessary things.
541 while (!cpu_isset(smp_processor_id(), smp_commenced_mask
))
543 setup_secondary_APIC_clock();
544 if (nmi_watchdog
== NMI_IO_APIC
) {
545 disable_8259A_irq(0);
546 enable_NMI_through_LVT0(NULL
);
551 * low-memory mappings have been cleared, flush them from
552 * the local TLBs too.
556 /* This must be done before setting cpu_online_map */
557 set_cpu_sibling_map(raw_smp_processor_id());
561 * We need to hold call_lock, so there is no inconsistency
562 * between the time smp_call_function() determines number of
563 * IPI receipients, and the time when the determination is made
564 * for which cpus receive the IPI. Holding this
565 * lock helps us to not include this cpu in a currently in progress
566 * smp_call_function().
568 lock_ipi_call_lock();
569 cpu_set(smp_processor_id(), cpu_online_map
);
570 unlock_ipi_call_lock();
571 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
573 /* We can take interrupts now: we're officially "up". */
581 * Everything has been set up for the secondary
582 * CPUs - they just need to reload everything
583 * from the task structure
584 * This function must not return.
586 void __devinit
initialize_secondary(void)
589 * We don't actually need to load the full TSS,
590 * basically just the stack pointer and the eip.
597 :"r" (current
->thread
.esp
),"r" (current
->thread
.eip
));
607 /* which logical CPUs are on which nodes */
608 cpumask_t node_2_cpu_mask
[MAX_NUMNODES
] __read_mostly
=
609 { [0 ... MAX_NUMNODES
-1] = CPU_MASK_NONE
};
610 /* which node each logical CPU is on */
611 int cpu_2_node
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = 0 };
612 EXPORT_SYMBOL(cpu_2_node
);
614 /* set up a mapping between cpu and node. */
615 static inline void map_cpu_to_node(int cpu
, int node
)
617 printk("Mapping cpu %d to node %d\n", cpu
, node
);
618 cpu_set(cpu
, node_2_cpu_mask
[node
]);
619 cpu_2_node
[cpu
] = node
;
622 /* undo a mapping between cpu and node. */
623 static inline void unmap_cpu_to_node(int cpu
)
627 printk("Unmapping cpu %d from all nodes\n", cpu
);
628 for (node
= 0; node
< MAX_NUMNODES
; node
++)
629 cpu_clear(cpu
, node_2_cpu_mask
[node
]);
632 #else /* !CONFIG_NUMA */
634 #define map_cpu_to_node(cpu, node) ({})
635 #define unmap_cpu_to_node(cpu) ({})
637 #endif /* CONFIG_NUMA */
639 u8 cpu_2_logical_apicid
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = BAD_APICID
};
641 static void map_cpu_to_logical_apicid(void)
643 int cpu
= smp_processor_id();
644 int apicid
= logical_smp_processor_id();
646 cpu_2_logical_apicid
[cpu
] = apicid
;
647 map_cpu_to_node(cpu
, apicid_to_node(apicid
));
650 static void unmap_cpu_to_logical_apicid(int cpu
)
652 cpu_2_logical_apicid
[cpu
] = BAD_APICID
;
653 unmap_cpu_to_node(cpu
);
657 static inline void __inquire_remote_apic(int apicid
)
659 int i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
660 char *names
[] = { "ID", "VERSION", "SPIV" };
663 printk("Inquiring remote APIC #%d...\n", apicid
);
665 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
666 printk("... APIC #%d %s: ", apicid
, names
[i
]);
671 apic_wait_icr_idle();
673 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(apicid
));
674 apic_write_around(APIC_ICR
, APIC_DM_REMRD
| regs
[i
]);
679 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
680 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
683 case APIC_ICR_RR_VALID
:
684 status
= apic_read(APIC_RRR
);
685 printk("%08x\n", status
);
694 #ifdef WAKE_SECONDARY_VIA_NMI
696 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
697 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
698 * won't ... remember to clear down the APIC, etc later.
701 wakeup_secondary_cpu(int logical_apicid
, unsigned long start_eip
)
703 unsigned long send_status
= 0, accept_status
= 0;
707 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(logical_apicid
));
709 /* Boot on the stack */
710 /* Kick the second */
711 apic_write_around(APIC_ICR
, APIC_DM_NMI
| APIC_DEST_LOGICAL
);
713 Dprintk("Waiting for send to finish...\n");
718 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
719 } while (send_status
&& (timeout
++ < 1000));
722 * Give the other CPU some time to accept the IPI.
726 * Due to the Pentium erratum 3AP.
728 maxlvt
= get_maxlvt();
730 apic_read_around(APIC_SPIV
);
731 apic_write(APIC_ESR
, 0);
733 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
734 Dprintk("NMI sent.\n");
737 printk("APIC never delivered???\n");
739 printk("APIC delivery error (%lx).\n", accept_status
);
741 return (send_status
| accept_status
);
743 #endif /* WAKE_SECONDARY_VIA_NMI */
745 #ifdef WAKE_SECONDARY_VIA_INIT
747 wakeup_secondary_cpu(int phys_apicid
, unsigned long start_eip
)
749 unsigned long send_status
= 0, accept_status
= 0;
750 int maxlvt
, timeout
, num_starts
, j
;
753 * Be paranoid about clearing APIC errors.
755 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
756 apic_read_around(APIC_SPIV
);
757 apic_write(APIC_ESR
, 0);
761 Dprintk("Asserting INIT.\n");
764 * Turn INIT on target chip
766 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
771 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
774 Dprintk("Waiting for send to finish...\n");
779 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
780 } while (send_status
&& (timeout
++ < 1000));
784 Dprintk("Deasserting INIT.\n");
787 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
790 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
792 Dprintk("Waiting for send to finish...\n");
797 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
798 } while (send_status
&& (timeout
++ < 1000));
800 atomic_set(&init_deasserted
, 1);
803 * Should we send STARTUP IPIs ?
805 * Determine this based on the APIC version.
806 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
808 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
814 * Run STARTUP IPI loop.
816 Dprintk("#startup loops: %d.\n", num_starts
);
818 maxlvt
= get_maxlvt();
820 for (j
= 1; j
<= num_starts
; j
++) {
821 Dprintk("Sending STARTUP #%d.\n",j
);
822 apic_read_around(APIC_SPIV
);
823 apic_write(APIC_ESR
, 0);
825 Dprintk("After apic_write.\n");
832 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
834 /* Boot on the stack */
835 /* Kick the second */
836 apic_write_around(APIC_ICR
, APIC_DM_STARTUP
837 | (start_eip
>> 12));
840 * Give the other CPU some time to accept the IPI.
844 Dprintk("Startup point 1.\n");
846 Dprintk("Waiting for send to finish...\n");
851 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
852 } while (send_status
&& (timeout
++ < 1000));
855 * Give the other CPU some time to accept the IPI.
859 * Due to the Pentium erratum 3AP.
862 apic_read_around(APIC_SPIV
);
863 apic_write(APIC_ESR
, 0);
865 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
866 if (send_status
|| accept_status
)
869 Dprintk("After Startup.\n");
872 printk("APIC never delivered???\n");
874 printk("APIC delivery error (%lx).\n", accept_status
);
876 return (send_status
| accept_status
);
878 #endif /* WAKE_SECONDARY_VIA_INIT */
880 extern cpumask_t cpu_initialized
;
881 static inline int alloc_cpu_id(void)
885 cpus_complement(tmp_map
, cpu_present_map
);
886 cpu
= first_cpu(tmp_map
);
892 #ifdef CONFIG_HOTPLUG_CPU
893 static struct task_struct
* __devinitdata cpu_idle_tasks
[NR_CPUS
];
894 static inline struct task_struct
* alloc_idle_task(int cpu
)
896 struct task_struct
*idle
;
898 if ((idle
= cpu_idle_tasks
[cpu
]) != NULL
) {
899 /* initialize thread_struct. we really want to avoid destroy
902 idle
->thread
.esp
= (unsigned long)task_pt_regs(idle
);
903 init_idle(idle
, cpu
);
906 idle
= fork_idle(cpu
);
909 cpu_idle_tasks
[cpu
] = idle
;
913 #define alloc_idle_task(cpu) fork_idle(cpu)
916 static int __devinit
do_boot_cpu(int apicid
, int cpu
)
918 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
919 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
920 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
923 struct task_struct
*idle
;
924 unsigned long boot_error
;
926 unsigned long start_eip
;
927 unsigned short nmi_high
= 0, nmi_low
= 0;
930 alternatives_smp_switch(1);
933 * We can't use kernel_thread since we must avoid to
934 * reschedule the child.
936 idle
= alloc_idle_task(cpu
);
938 panic("failed fork for CPU %d", cpu
);
939 idle
->thread
.eip
= (unsigned long) start_secondary
;
940 /* start_eip had better be page-aligned! */
941 start_eip
= setup_trampoline();
943 /* So we see what's up */
944 printk("Booting processor %d/%d eip %lx\n", cpu
, apicid
, start_eip
);
945 /* Stack for startup_32 can be just as for start_secondary onwards */
946 stack_start
.esp
= (void *) idle
->thread
.esp
;
951 * This grunge runs the startup process for
952 * the targeted processor.
955 atomic_set(&init_deasserted
, 0);
957 Dprintk("Setting warm reset code and vector.\n");
959 store_NMI_vector(&nmi_high
, &nmi_low
);
961 smpboot_setup_warm_reset_vector(start_eip
);
964 * Starting actual IPI sequence...
966 boot_error
= wakeup_secondary_cpu(apicid
, start_eip
);
970 * allow APs to start initializing.
972 Dprintk("Before Callout %d.\n", cpu
);
973 cpu_set(cpu
, cpu_callout_map
);
974 Dprintk("After Callout %d.\n", cpu
);
977 * Wait 5s total for a response
979 for (timeout
= 0; timeout
< 50000; timeout
++) {
980 if (cpu_isset(cpu
, cpu_callin_map
))
981 break; /* It has booted */
985 if (cpu_isset(cpu
, cpu_callin_map
)) {
986 /* number CPUs logically, starting from 1 (BSP is 0) */
988 printk("CPU%d: ", cpu
);
989 print_cpu_info(&cpu_data
[cpu
]);
990 Dprintk("CPU has booted.\n");
993 if (*((volatile unsigned char *)trampoline_base
)
995 /* trampoline started but...? */
996 printk("Stuck ??\n");
998 /* trampoline code not run */
999 printk("Not responding.\n");
1000 inquire_remote_apic(apicid
);
1005 /* Try to put things back the way they were before ... */
1006 unmap_cpu_to_logical_apicid(cpu
);
1007 cpu_clear(cpu
, cpu_callout_map
); /* was set here (do_boot_cpu()) */
1008 cpu_clear(cpu
, cpu_initialized
); /* was set by cpu_init() */
1011 x86_cpu_to_apicid
[cpu
] = apicid
;
1012 cpu_set(cpu
, cpu_present_map
);
1015 /* mark "stuck" area as not stuck */
1016 *((volatile unsigned long *)trampoline_base
) = 0;
1021 #ifdef CONFIG_HOTPLUG_CPU
1022 void cpu_exit_clear(void)
1024 int cpu
= raw_smp_processor_id();
1032 cpu_clear(cpu
, cpu_callout_map
);
1033 cpu_clear(cpu
, cpu_callin_map
);
1035 cpu_clear(cpu
, smp_commenced_mask
);
1036 unmap_cpu_to_logical_apicid(cpu
);
1039 struct warm_boot_cpu_info
{
1040 struct completion
*complete
;
1045 static void __cpuinit
do_warm_boot_cpu(void *p
)
1047 struct warm_boot_cpu_info
*info
= p
;
1048 do_boot_cpu(info
->apicid
, info
->cpu
);
1049 complete(info
->complete
);
1052 static int __cpuinit
__smp_prepare_cpu(int cpu
)
1054 DECLARE_COMPLETION(done
);
1055 struct warm_boot_cpu_info info
;
1056 struct work_struct task
;
1058 struct Xgt_desc_struct
*cpu_gdt_descr
= &per_cpu(cpu_gdt_descr
, cpu
);
1060 apicid
= x86_cpu_to_apicid
[cpu
];
1061 if (apicid
== BAD_APICID
) {
1067 * the CPU isn't initialized at boot time, allocate gdt table here.
1068 * cpu_init will initialize it
1070 if (!cpu_gdt_descr
->address
) {
1071 cpu_gdt_descr
->address
= get_zeroed_page(GFP_KERNEL
);
1072 if (!cpu_gdt_descr
->address
)
1073 printk(KERN_CRIT
"CPU%d failed to allocate GDT\n", cpu
);
1078 info
.complete
= &done
;
1079 info
.apicid
= apicid
;
1081 INIT_WORK(&task
, do_warm_boot_cpu
, &info
);
1083 tsc_sync_disabled
= 1;
1085 /* init low mem mapping */
1086 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ USER_PGD_PTRS
,
1089 schedule_work(&task
);
1090 wait_for_completion(&done
);
1092 tsc_sync_disabled
= 0;
1100 static void smp_tune_scheduling (void)
1102 unsigned long cachesize
; /* kB */
1103 unsigned long bandwidth
= 350; /* MB/s */
1105 * Rough estimation for SMP scheduling, this is the number of
1106 * cycles it takes for a fully memory-limited process to flush
1107 * the SMP-local cache.
1109 * (For a P5 this pretty much means we will choose another idle
1110 * CPU almost always at wakeup time (this is due to the small
1111 * L1 cache), on PIIs it's around 50-100 usecs, depending on
1117 * this basically disables processor-affinity
1118 * scheduling on SMP without a TSC.
1122 cachesize
= boot_cpu_data
.x86_cache_size
;
1123 if (cachesize
== -1) {
1124 cachesize
= 16; /* Pentiums, 2x8kB cache */
1127 max_cache_size
= cachesize
* 1024;
1132 * Cycle through the processors sending APIC IPIs to boot each.
1135 static int boot_cpu_logical_apicid
;
1136 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1138 #ifdef CONFIG_X86_NUMAQ
1139 EXPORT_SYMBOL(xquad_portio
);
1142 static void __init
smp_boot_cpus(unsigned int max_cpus
)
1144 int apicid
, cpu
, bit
, kicked
;
1145 unsigned long bogosum
= 0;
1148 * Setup boot CPU information
1150 smp_store_cpu_info(0); /* Final full version of the data */
1151 printk("CPU%d: ", 0);
1152 print_cpu_info(&cpu_data
[0]);
1154 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1155 boot_cpu_logical_apicid
= logical_smp_processor_id();
1156 x86_cpu_to_apicid
[0] = boot_cpu_physical_apicid
;
1158 current_thread_info()->cpu
= 0;
1159 smp_tune_scheduling();
1161 set_cpu_sibling_map(0);
1164 * If we couldn't find an SMP configuration at boot time,
1165 * get out of here now!
1167 if (!smp_found_config
&& !acpi_lapic
) {
1168 printk(KERN_NOTICE
"SMP motherboard not detected.\n");
1169 smpboot_clear_io_apic_irqs();
1170 phys_cpu_present_map
= physid_mask_of_physid(0);
1171 if (APIC_init_uniprocessor())
1172 printk(KERN_NOTICE
"Local APIC not detected."
1173 " Using dummy APIC emulation.\n");
1174 map_cpu_to_logical_apicid();
1175 cpu_set(0, cpu_sibling_map
[0]);
1176 cpu_set(0, cpu_core_map
[0]);
1181 * Should not be necessary because the MP table should list the boot
1182 * CPU too, but we do it for the sake of robustness anyway.
1183 * Makes no sense to do this check in clustered apic mode, so skip it
1185 if (!check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1186 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1187 boot_cpu_physical_apicid
);
1188 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1192 * If we couldn't find a local APIC, then get out of here now!
1194 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) && !cpu_has_apic
) {
1195 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1196 boot_cpu_physical_apicid
);
1197 printk(KERN_ERR
"... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1198 smpboot_clear_io_apic_irqs();
1199 phys_cpu_present_map
= physid_mask_of_physid(0);
1200 cpu_set(0, cpu_sibling_map
[0]);
1201 cpu_set(0, cpu_core_map
[0]);
1205 verify_local_APIC();
1208 * If SMP should be disabled, then really disable it!
1211 smp_found_config
= 0;
1212 printk(KERN_INFO
"SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1213 smpboot_clear_io_apic_irqs();
1214 phys_cpu_present_map
= physid_mask_of_physid(0);
1215 cpu_set(0, cpu_sibling_map
[0]);
1216 cpu_set(0, cpu_core_map
[0]);
1222 map_cpu_to_logical_apicid();
1225 setup_portio_remap();
1228 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1230 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1231 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1232 * clustered apic ID.
1234 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map
));
1237 for (bit
= 0; kicked
< NR_CPUS
&& bit
< MAX_APICS
; bit
++) {
1238 apicid
= cpu_present_to_apicid(bit
);
1240 * Don't even attempt to start the boot CPU!
1242 if ((apicid
== boot_cpu_apicid
) || (apicid
== BAD_APICID
))
1245 if (!check_apicid_present(bit
))
1247 if (max_cpus
<= cpucount
+1)
1250 if (((cpu
= alloc_cpu_id()) <= 0) || do_boot_cpu(apicid
, cpu
))
1251 printk("CPU #%d not responding - cannot use it.\n",
1258 * Cleanup possible dangling ends...
1260 smpboot_restore_warm_reset_vector();
1263 * Allow the user to impress friends.
1265 Dprintk("Before bogomips.\n");
1266 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++)
1267 if (cpu_isset(cpu
, cpu_callout_map
))
1268 bogosum
+= cpu_data
[cpu
].loops_per_jiffy
;
1270 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1272 bogosum
/(500000/HZ
),
1273 (bogosum
/(5000/HZ
))%100);
1275 Dprintk("Before bogocount - setting activated=1.\n");
1278 printk(KERN_WARNING
"WARNING: SMP operation may be unreliable with B stepping processors.\n");
1281 * Don't taint if we are running SMP kernel on a single non-MP
1284 if (tainted
& TAINT_UNSAFE_SMP
) {
1286 printk (KERN_INFO
"WARNING: This combination of AMD processors is not suitable for SMP.\n");
1288 tainted
&= ~TAINT_UNSAFE_SMP
;
1291 Dprintk("Boot done.\n");
1294 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1297 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++) {
1298 cpus_clear(cpu_sibling_map
[cpu
]);
1299 cpus_clear(cpu_core_map
[cpu
]);
1302 cpu_set(0, cpu_sibling_map
[0]);
1303 cpu_set(0, cpu_core_map
[0]);
1305 smpboot_setup_io_apic();
1307 setup_boot_APIC_clock();
1310 * Synchronize the TSC with the AP
1312 if (cpu_has_tsc
&& cpucount
&& cpu_khz
)
1313 synchronize_tsc_bp();
1316 /* These are wrappers to interface to the new boot process. Someone
1317 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1318 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1320 smp_commenced_mask
= cpumask_of_cpu(0);
1321 cpu_callin_map
= cpumask_of_cpu(0);
1323 smp_boot_cpus(max_cpus
);
1326 void __devinit
smp_prepare_boot_cpu(void)
1328 cpu_set(smp_processor_id(), cpu_online_map
);
1329 cpu_set(smp_processor_id(), cpu_callout_map
);
1330 cpu_set(smp_processor_id(), cpu_present_map
);
1331 cpu_set(smp_processor_id(), cpu_possible_map
);
1332 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
1335 #ifdef CONFIG_HOTPLUG_CPU
1337 remove_siblinginfo(int cpu
)
1340 struct cpuinfo_x86
*c
= cpu_data
;
1342 for_each_cpu_mask(sibling
, cpu_core_map
[cpu
]) {
1343 cpu_clear(cpu
, cpu_core_map
[sibling
]);
1345 * last thread sibling in this cpu core going down
1347 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1)
1348 c
[sibling
].booted_cores
--;
1351 for_each_cpu_mask(sibling
, cpu_sibling_map
[cpu
])
1352 cpu_clear(cpu
, cpu_sibling_map
[sibling
]);
1353 cpus_clear(cpu_sibling_map
[cpu
]);
1354 cpus_clear(cpu_core_map
[cpu
]);
1355 c
[cpu
].phys_proc_id
= 0;
1356 c
[cpu
].cpu_core_id
= 0;
1357 cpu_clear(cpu
, cpu_sibling_setup_map
);
1360 int __cpu_disable(void)
1362 cpumask_t map
= cpu_online_map
;
1363 int cpu
= smp_processor_id();
1366 * Perhaps use cpufreq to drop frequency, but that could go
1367 * into generic code.
1369 * We won't take down the boot processor on i386 due to some
1370 * interrupts only being able to be serviced by the BSP.
1371 * Especially so if we're not using an IOAPIC -zwane
1377 /* Allow any queued timer interrupts to get serviced */
1380 local_irq_disable();
1382 remove_siblinginfo(cpu
);
1384 cpu_clear(cpu
, map
);
1386 /* It's now safe to remove this processor from the online map */
1387 cpu_clear(cpu
, cpu_online_map
);
1391 void __cpu_die(unsigned int cpu
)
1393 /* We don't do anything here: idle task is faking death itself. */
1396 for (i
= 0; i
< 10; i
++) {
1397 /* They ack this in play_dead by setting CPU_DEAD */
1398 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1399 printk ("CPU %d is now offline\n", cpu
);
1400 if (1 == num_online_cpus())
1401 alternatives_smp_switch(0);
1406 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1408 #else /* ... !CONFIG_HOTPLUG_CPU */
1409 int __cpu_disable(void)
1414 void __cpu_die(unsigned int cpu
)
1416 /* We said "no" in __cpu_disable */
1419 #endif /* CONFIG_HOTPLUG_CPU */
1421 int __devinit
__cpu_up(unsigned int cpu
)
1423 #ifdef CONFIG_HOTPLUG_CPU
1427 * We do warm boot only on cpus that had booted earlier
1428 * Otherwise cold boot is all handled from smp_boot_cpus().
1429 * cpu_callin_map is set during AP kickstart process. Its reset
1430 * when a cpu is taken offline from cpu_exit_clear().
1432 if (!cpu_isset(cpu
, cpu_callin_map
))
1433 ret
= __smp_prepare_cpu(cpu
);
1439 /* In case one didn't come up */
1440 if (!cpu_isset(cpu
, cpu_callin_map
)) {
1441 printk(KERN_DEBUG
"skipping cpu%d, didn't come online\n", cpu
);
1447 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
1448 /* Unleash the CPU! */
1449 cpu_set(cpu
, smp_commenced_mask
);
1450 while (!cpu_isset(cpu
, cpu_online_map
))
1455 void __init
smp_cpus_done(unsigned int max_cpus
)
1457 #ifdef CONFIG_X86_IO_APIC
1458 setup_ioapic_dest();
1461 #ifndef CONFIG_HOTPLUG_CPU
1463 * Disable executability of the SMP trampoline:
1465 set_kernel_exec((unsigned long)trampoline_base
, trampoline_exec
);
1469 void __init
smp_intr_init(void)
1472 * IRQ0 must be given a fixed assignment and initialized,
1473 * because it's used before the IO-APIC is set up.
1475 set_intr_gate(FIRST_DEVICE_VECTOR
, interrupt
[0]);
1478 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1479 * IPI, driven by wakeup.
1481 set_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
1483 /* IPI for invalidation */
1484 set_intr_gate(INVALIDATE_TLB_VECTOR
, invalidate_interrupt
);
1486 /* IPI for generic function call */
1487 set_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);