arch/i386/pci/i386.c

   1 /*
   2  *      Low-Level PCI Access for i386 machines
   3  *
   4  * Copyright 1993, 1994 Drew Eckhardt
   5  *      Visionary Computing
   6  *      (Unix and Linux consulting and custom programming)
   7  *      Drew@Colorado.EDU
   8  *      +1 (303) 786-7975
   9  *
  10  * Drew's work was sponsored by:
  11  *      iX Multiuser Multitasking Magazine
  12  *      Hannover, Germany
  13  *      hm@ix.de
  14  *
  15  * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
  16  *
  17  * For more information, please consult the following manuals (look at
  18  * http://www.pcisig.com/ for how to get them):
  19  *
  20  * PCI BIOS Specification
  21  * PCI Local Bus Specification
  22  * PCI to PCI Bridge Specification
  23  * PCI System Design Guide
  24  *
  25  */
  26
  27 #include <linux/types.h>
  28 #include <linux/kernel.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/ioport.h>
  32 #include <linux/errno.h>
  33
  34 #include "pci.h"
  35
  36 /*
  37  * We need to avoid collisions with `mirrored' VGA ports
  38  * and other strange ISA hardware, so we always want the
  39  * addresses to be allocated in the 0x000-0x0ff region
  40  * modulo 0x400.
  41  *
  42  * Why? Because some silly external IO cards only decode
  43  * the low 10 bits of the IO address. The 0x00-0xff region
  44  * is reserved for motherboard devices that decode all 16
  45  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  46  * but we want to try to avoid allocating at 0x2900-0x2bff
  47  * which might have be mirrored at 0x0100-0x03ff..
  48  */
  49 void
  50 pcibios_align_resource(void *data, struct resource *res,
  51                        unsigned long size, unsigned long align)
  52 {
  53         if (res->flags & IORESOURCE_IO) {
  54                 unsigned long start = res->start;
  55
  56                 if (start & 0x300) {
  57                         start = (start + 0x3ff) & ~0x3ff;
  58                         res->start = start;
  59                 }
  60         }
  61 }
  62
  63
  64 /*
  65  *  Handle resources of PCI devices.  If the world were perfect, we could
  66  *  just allocate all the resource regions and do nothing more.  It isn't.
  67  *  On the other hand, we cannot just re-allocate all devices, as it would
  68  *  require us to know lots of host bridge internals.  So we attempt to
  69  *  keep as much of the original configuration as possible, but tweak it
  70  *  when it's found to be wrong.
  71  *
  72  *  Known BIOS problems we have to work around:
  73  *      - I/O or memory regions not configured
  74  *      - regions configured, but not enabled in the command register
  75  *      - bogus I/O addresses above 64K used
  76  *      - expansion ROMs left enabled (this may sound harmless, but given
  77  *        the fact the PCI specs explicitly allow address decoders to be
  78  *        shared between expansion ROMs and other resource regions, it's
  79  *        at least dangerous)
  80  *
  81  *  Our solution:
  82  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
  83  *          This gives us fixed barriers on where we can allocate.
  84  *      (2) Allocate resources for all enabled devices.  If there is
  85  *          a collision, just mark the resource as unallocated. Also
  86  *          disable expansion ROMs during this step.
  87  *      (3) Try to allocate resources for disabled devices.  If the
  88  *          resources were assigned correctly, everything goes well,
  89  *          if they weren't, they won't disturb allocation of other
  90  *          resources.
  91  *      (4) Assign new addresses to resources which were either
  92  *          not configured at all or misconfigured.  If explicitly
  93  *          requested by the user, configure expansion ROM address
  94  *          as well.
  95  */
  96
  97 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
  98 {
  99         struct pci_bus *bus;
 100         struct pci_dev *dev;
 101         int idx;
 102         struct resource *r, *pr;
 103
 104         /* Depth-First Search on bus tree */
 105         list_for_each_entry(bus, bus_list, node) {
 106                 if ((dev = bus->self)) {
 107                         for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
 108                                 r = &dev->resource[idx];
 109                                 if (!r->flags)
 110                                         continue;
 111                                 pr = pci_find_parent_resource(dev, r);
 112                                 if (!r->start || !pr || request_resource(pr, r) < 0) {
 113                                         printk(KERN_ERR "PCI: Cannot allocate resource region %d of bridge %s\n", idx, pci_name(dev));
 114                                         /* Something is wrong with the region.
 115                                            Invalidate the resource to prevent child
 116                                            resource allocations in this range. */
 117                                         r->flags = 0;
 118                                 }
 119                         }
 120                 }
 121                 pcibios_allocate_bus_resources(&bus->children);
 122         }
 123 }
 124
 125 static void __init pcibios_allocate_resources(int pass)
 126 {
 127         struct pci_dev *dev = NULL;
 128         int idx, disabled;
 129         u16 command;
 130         struct resource *r, *pr;
 131
 132         for_each_pci_dev(dev) {
 133                 pci_read_config_word(dev, PCI_COMMAND, &command);
 134                 for(idx = 0; idx < 6; idx++) {
 135                         r = &dev->resource[idx];
 136                         if (r->parent)          /* Already allocated */
 137                                 continue;
 138                         if (!r->start)          /* Address not assigned at all */
 139                                 continue;
 140                         if (r->flags & IORESOURCE_IO)
 141                                 disabled = !(command & PCI_COMMAND_IO);
 142                         else
 143                                 disabled = !(command & PCI_COMMAND_MEMORY);
 144                         if (pass == disabled) {
 145                                 DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
 146                                     r->start, r->end, r->flags, disabled, pass);
 147                                 pr = pci_find_parent_resource(dev, r);
 148                                 if (!pr || request_resource(pr, r) < 0) {
 149                                         printk(KERN_ERR "PCI: Cannot allocate resource region %d of device %s\n", idx, pci_name(dev));
 150                                         /* We'll assign a new address later */
 151                                         r->end -= r->start;
 152                                         r->start = 0;
 153                                 }
 154                         }
 155                 }
 156                 if (!pass) {
 157                         r = &dev->resource[PCI_ROM_RESOURCE];
 158                         if (r->flags & IORESOURCE_ROM_ENABLE) {
 159                                 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
 160                                 u32 reg;
 161                                 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
 162                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
 163                                 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
 164                                 pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
 165                         }
 166                 }
 167         }
 168 }
 169
 170 static int __init pcibios_assign_resources(void)
 171 {
 172         struct pci_dev *dev = NULL;
 173         int idx;
 174         struct resource *r;
 175
 176         for_each_pci_dev(dev) {
 177                 int class = dev->class >> 8;
 178
 179                 /* Don't touch classless devices and host bridges */
 180                 if (!class || class == PCI_CLASS_BRIDGE_HOST)
 181                         continue;
 182
 183                 for(idx=0; idx<6; idx++) {
 184                         r = &dev->resource[idx];
 185
 186                         /*
 187                          *  Don't touch IDE controllers and I/O ports of video cards!
 188                          */
 189                         if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) ||
 190                             (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO)))
 191                                 continue;
 192
 193                         /*
 194                          *  We shall assign a new address to this resource, either because
 195                          *  the BIOS forgot to do so or because we have decided the old
 196                          *  address was unusable for some reason.
 197                          */
 198                         if (!r->start && r->end)
 199                                 pci_assign_resource(dev, idx);
 200                 }
 201
 202                 if (pci_probe & PCI_ASSIGN_ROMS) {
 203                         r = &dev->resource[PCI_ROM_RESOURCE];
 204                         r->end -= r->start;
 205                         r->start = 0;
 206                         if (r->end)
 207                                 pci_assign_resource(dev, PCI_ROM_RESOURCE);
 208                 }
 209         }
 210         return 0;
 211 }
 212
 213 void __init pcibios_resource_survey(void)
 214 {
 215         DBG("PCI: Allocating resources\n");
 216         pcibios_allocate_bus_resources(&pci_root_buses);
 217         pcibios_allocate_resources(0);
 218         pcibios_allocate_resources(1);
 219 }
 220
 221 /**
 222  * called in fs_initcall (one below subsys_initcall),
 223  * give a chance for motherboard reserve resources
 224  */
 225 fs_initcall(pcibios_assign_resources);
 226
 227 int pcibios_enable_resources(struct pci_dev *dev, int mask)
 228 {
 229         u16 cmd, old_cmd;
 230         int idx;
 231         struct resource *r;
 232
 233         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 234         old_cmd = cmd;
 235         for(idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
 236                 /* Only set up the requested stuff */
 237                 if (!(mask & (1<<idx)))
 238                         continue;
 239
 240                 r = &dev->resource[idx];
 241                 if (!r->start && r->end) {
 242                         printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
 243                         return -EINVAL;
 244                 }
 245                 if (r->flags & IORESOURCE_IO)
 246                         cmd |= PCI_COMMAND_IO;
 247                 if (r->flags & IORESOURCE_MEM)
 248                         cmd |= PCI_COMMAND_MEMORY;
 249         }
 250         if (dev->resource[PCI_ROM_RESOURCE].start)
 251                 cmd |= PCI_COMMAND_MEMORY;
 252         if (cmd != old_cmd) {
 253                 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
 254                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 255         }
 256         return 0;
 257 }
 258
 259 /*
 260  *  If we set up a device for bus mastering, we need to check the latency
 261  *  timer as certain crappy BIOSes forget to set it properly.
 262  */
 263 unsigned int pcibios_max_latency = 255;
 264
 265 void pcibios_set_master(struct pci_dev *dev)
 266 {
 267         u8 lat;
 268         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 269         if (lat < 16)
 270                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 271         else if (lat > pcibios_max_latency)
 272                 lat = pcibios_max_latency;
 273         else
 274                 return;
 275         printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
 276         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 277 }
 278
 279 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 280                         enum pci_mmap_state mmap_state, int write_combine)
 281 {
 282         unsigned long prot;
 283
 284         /* I/O space cannot be accessed via normal processor loads and
 285          * stores on this platform.
 286          */
 287         if (mmap_state == pci_mmap_io)
 288                 return -EINVAL;
 289
 290         /* Leave vm_pgoff as-is, the PCI space address is the physical
 291          * address on this platform.
 292          */
 293         vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO);
 294
 295         prot = pgprot_val(vma->vm_page_prot);
 296         if (boot_cpu_data.x86 > 3)
 297                 prot |= _PAGE_PCD | _PAGE_PWT;
 298         vma->vm_page_prot = __pgprot(prot);
 299
 300         /* Write-combine setting is ignored, it is changed via the mtrr
 301          * interfaces on this platform.
 302          */
 303         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 304                              vma->vm_end - vma->vm_start,
 305                              vma->vm_page_prot))
 306                 return -EAGAIN;
 307
 308         return 0;
 309 }