numa: ia64: use generic percpu var numa_node_id() implementation
[deliverable/linux.git] / arch / ia64 / include / asm / topology.h
1 /*
2 * Copyright (C) 2002, Erich Focht, NEC
3 *
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11 #ifndef _ASM_IA64_TOPOLOGY_H
12 #define _ASM_IA64_TOPOLOGY_H
13
14 #include <asm/acpi.h>
15 #include <asm/numa.h>
16 #include <asm/smp.h>
17
18 #ifdef CONFIG_NUMA
19
20 /* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
21 #define PENALTY_FOR_NODE_WITH_CPUS 255
22
23 /*
24 * Distance above which we begin to use zone reclaim
25 */
26 #define RECLAIM_DISTANCE 15
27
28 /*
29 * Returns a bitmask of CPUs on Node 'node'.
30 */
31 #define cpumask_of_node(node) ((node) == -1 ? \
32 cpu_all_mask : \
33 &node_to_cpu_mask[node])
34
35 /*
36 * Returns the number of the node containing Node 'nid'.
37 * Not implemented here. Multi-level hierarchies detected with
38 * the help of node_distance().
39 */
40 #define parent_node(nid) (nid)
41
42 /*
43 * Determines the node for a given pci bus
44 */
45 #define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
46
47 void build_cpu_to_node_map(void);
48
49 #define SD_CPU_INIT (struct sched_domain) { \
50 .parent = NULL, \
51 .child = NULL, \
52 .groups = NULL, \
53 .min_interval = 1, \
54 .max_interval = 4, \
55 .busy_factor = 64, \
56 .imbalance_pct = 125, \
57 .cache_nice_tries = 2, \
58 .busy_idx = 2, \
59 .idle_idx = 1, \
60 .newidle_idx = 0, \
61 .wake_idx = 0, \
62 .forkexec_idx = 0, \
63 .flags = SD_LOAD_BALANCE \
64 | SD_BALANCE_NEWIDLE \
65 | SD_BALANCE_EXEC \
66 | SD_BALANCE_FORK \
67 | SD_WAKE_AFFINE, \
68 .last_balance = jiffies, \
69 .balance_interval = 1, \
70 .nr_balance_failed = 0, \
71 }
72
73 /* sched_domains SD_NODE_INIT for IA64 NUMA machines */
74 #define SD_NODE_INIT (struct sched_domain) { \
75 .parent = NULL, \
76 .child = NULL, \
77 .groups = NULL, \
78 .min_interval = 8, \
79 .max_interval = 8*(min(num_online_cpus(), 32U)), \
80 .busy_factor = 64, \
81 .imbalance_pct = 125, \
82 .cache_nice_tries = 2, \
83 .busy_idx = 3, \
84 .idle_idx = 2, \
85 .newidle_idx = 0, \
86 .wake_idx = 0, \
87 .forkexec_idx = 0, \
88 .flags = SD_LOAD_BALANCE \
89 | SD_BALANCE_NEWIDLE \
90 | SD_BALANCE_EXEC \
91 | SD_BALANCE_FORK \
92 | SD_SERIALIZE, \
93 .last_balance = jiffies, \
94 .balance_interval = 64, \
95 .nr_balance_failed = 0, \
96 }
97
98 #endif /* CONFIG_NUMA */
99
100 #ifdef CONFIG_SMP
101 #define topology_physical_package_id(cpu) (cpu_data(cpu)->socket_id)
102 #define topology_core_id(cpu) (cpu_data(cpu)->core_id)
103 #define topology_core_cpumask(cpu) (&cpu_core_map[cpu])
104 #define topology_thread_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu))
105 #define smt_capable() (smp_num_siblings > 1)
106 #endif
107
108 extern void arch_fix_phys_package_id(int num, u32 slot);
109
110 #define cpumask_of_pcibus(bus) (pcibus_to_node(bus) == -1 ? \
111 cpu_all_mask : \
112 cpumask_of_node(pcibus_to_node(bus)))
113
114 #include <asm-generic/topology.h>
115
116 #endif /* _ASM_IA64_TOPOLOGY_H */
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