arch/ia64/include/asm/topology.h

   1 /*
   2  * Copyright (C) 2002, Erich Focht, NEC
   3  *
   4  * All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11 #ifndef _ASM_IA64_TOPOLOGY_H
  12 #define _ASM_IA64_TOPOLOGY_H
  13
  14 #include <asm/acpi.h>
  15 #include <asm/numa.h>
  16 #include <asm/smp.h>
  17
  18 #ifdef CONFIG_NUMA
  19
  20 /* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
  21 #define PENALTY_FOR_NODE_WITH_CPUS 255
  22
  23 /*
  24  * Distance above which we begin to use zone reclaim
  25  */
  26 #define RECLAIM_DISTANCE 15
  27
  28 /*
  29  * Returns the number of the node containing CPU 'cpu'
  30  */
  31 #define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu])
  32
  33 /*
  34  * Returns a bitmask of CPUs on Node 'node'.
  35  */
  36 #define node_to_cpumask(node) (node_to_cpu_mask[node])
  37 #define cpumask_of_node(node) (&node_to_cpu_mask[node])
  38
  39 /*
  40  * Returns the number of the node containing Node 'nid'.
  41  * Not implemented here. Multi-level hierarchies detected with
  42  * the help of node_distance().
  43  */
  44 #define parent_node(nid) (nid)
  45
  46 /*
  47  * Determines the node for a given pci bus
  48  */
  49 #define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
  50
  51 void build_cpu_to_node_map(void);
  52
  53 #define SD_CPU_INIT (struct sched_domain) {             \
  54         .parent                 = NULL,                 \
  55         .child                  = NULL,                 \
  56         .groups                 = NULL,                 \
  57         .min_interval           = 1,                    \
  58         .max_interval           = 4,                    \
  59         .busy_factor            = 64,                   \
  60         .imbalance_pct          = 125,                  \
  61         .cache_nice_tries       = 2,                    \
  62         .busy_idx               = 2,                    \
  63         .idle_idx               = 1,                    \
  64         .newidle_idx            = 0,                    \
  65         .wake_idx               = 0,                    \
  66         .forkexec_idx           = 0,                    \
  67         .flags                  = SD_LOAD_BALANCE       \
  68                                 | SD_BALANCE_NEWIDLE    \
  69                                 | SD_BALANCE_EXEC       \
  70                                 | SD_BALANCE_FORK       \
  71                                 | SD_WAKE_AFFINE,       \
  72         .last_balance           = jiffies,              \
  73         .balance_interval       = 1,                    \
  74         .nr_balance_failed      = 0,                    \
  75 }
  76
  77 /* sched_domains SD_NODE_INIT for IA64 NUMA machines */
  78 #define SD_NODE_INIT (struct sched_domain) {            \
  79         .parent                 = NULL,                 \
  80         .child                  = NULL,                 \
  81         .groups                 = NULL,                 \
  82         .min_interval           = 8,                    \
  83         .max_interval           = 8*(min(num_online_cpus(), 32U)), \
  84         .busy_factor            = 64,                   \
  85         .imbalance_pct          = 125,                  \
  86         .cache_nice_tries       = 2,                    \
  87         .busy_idx               = 3,                    \
  88         .idle_idx               = 2,                    \
  89         .newidle_idx            = 0,                    \
  90         .wake_idx               = 0,                    \
  91         .forkexec_idx           = 0,                    \
  92         .flags                  = SD_LOAD_BALANCE       \
  93                                 | SD_BALANCE_NEWIDLE    \
  94                                 | SD_BALANCE_EXEC       \
  95                                 | SD_BALANCE_FORK       \
  96                                 | SD_SERIALIZE,         \
  97         .last_balance           = jiffies,              \
  98         .balance_interval       = 64,                   \
  99         .nr_balance_failed      = 0,                    \
 100 }
 101
 102 #endif /* CONFIG_NUMA */
 103
 104 #ifdef CONFIG_SMP
 105 #define topology_physical_package_id(cpu)       (cpu_data(cpu)->socket_id)
 106 #define topology_core_id(cpu)                   (cpu_data(cpu)->core_id)
 107 #define topology_core_siblings(cpu)             (cpu_core_map[cpu])
 108 #define topology_thread_siblings(cpu)           (per_cpu(cpu_sibling_map, cpu))
 109 #define topology_core_cpumask(cpu)              (&cpu_core_map[cpu])
 110 #define topology_thread_cpumask(cpu)            (&per_cpu(cpu_sibling_map, cpu))
 111 #define smt_capable()                           (smp_num_siblings > 1)
 112 #endif
 113
 114 extern void arch_fix_phys_package_id(int num, u32 slot);
 115
 116 #define cpumask_of_pcibus(bus)  (pcibus_to_node(bus) == -1 ?            \
 117                                  cpu_all_mask :                         \
 118                                  cpumask_of_node(pcibus_to_node(bus)))
 119
 120 #include <asm-generic/topology.h>
 121
 122 #endif /* _ASM_IA64_TOPOLOGY_H */