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ext3: Flush disk caches on fsync when needed
[deliverable/linux.git] / arch / ia64 / kernel / head.S
1 /*
2 * Here is where the ball gets rolling as far as the kernel is concerned.
3 * When control is transferred to _start, the bootload has already
4 * loaded us to the correct address. All that's left to do here is
5 * to set up the kernel's global pointer and jump to the kernel
6 * entry point.
7 *
8 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 * Copyright (C) 1999 Intel Corp.
14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
17 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
18 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com>
19 * Support for CPU Hotplug
20 */
21
22
23 #include <asm/asmmacro.h>
24 #include <asm/fpu.h>
25 #include <asm/kregs.h>
26 #include <asm/mmu_context.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/pal.h>
29 #include <asm/paravirt.h>
30 #include <asm/pgtable.h>
31 #include <asm/processor.h>
32 #include <asm/ptrace.h>
33 #include <asm/system.h>
34 #include <asm/mca_asm.h>
35 #include <linux/init.h>
36 #include <linux/linkage.h>
37 #include "head.h"
38
39 #ifdef CONFIG_HOTPLUG_CPU
40 #define SAL_PSR_BITS_TO_SET \
41 (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL)
42
43 #define SAVE_FROM_REG(src, ptr, dest) \
44 mov dest=src;; \
45 st8 [ptr]=dest,0x08
46
47 #define RESTORE_REG(reg, ptr, _tmp) \
48 ld8 _tmp=[ptr],0x08;; \
49 mov reg=_tmp
50
51 #define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\
52 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
53 mov _idx=0;; \
54 1: \
55 SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \
56 add _idx=1,_idx;; \
57 br.cloop.sptk.many 1b
58
59 #define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\
60 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
61 mov _idx=0;; \
62 _lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \
63 add _idx=1, _idx;; \
64 br.cloop.sptk.many _lbl
65
66 #define SAVE_ONE_RR(num, _reg, _tmp) \
67 movl _tmp=(num<<61);; \
68 mov _reg=rr[_tmp]
69
70 #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
71 SAVE_ONE_RR(0,_r0, _tmp);; \
72 SAVE_ONE_RR(1,_r1, _tmp);; \
73 SAVE_ONE_RR(2,_r2, _tmp);; \
74 SAVE_ONE_RR(3,_r3, _tmp);; \
75 SAVE_ONE_RR(4,_r4, _tmp);; \
76 SAVE_ONE_RR(5,_r5, _tmp);; \
77 SAVE_ONE_RR(6,_r6, _tmp);; \
78 SAVE_ONE_RR(7,_r7, _tmp);;
79
80 #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
81 st8 [ptr]=_r0, 8;; \
82 st8 [ptr]=_r1, 8;; \
83 st8 [ptr]=_r2, 8;; \
84 st8 [ptr]=_r3, 8;; \
85 st8 [ptr]=_r4, 8;; \
86 st8 [ptr]=_r5, 8;; \
87 st8 [ptr]=_r6, 8;; \
88 st8 [ptr]=_r7, 8;;
89
90 #define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \
91 mov ar.lc=0x08-1;; \
92 movl _idx1=0x00;; \
93 RestRR: \
94 dep.z _idx2=_idx1,61,3;; \
95 ld8 _tmp=[ptr],8;; \
96 mov rr[_idx2]=_tmp;; \
97 srlz.d;; \
98 add _idx1=1,_idx1;; \
99 br.cloop.sptk.few RestRR
100
101 #define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \
102 movl reg1=sal_state_for_booting_cpu;; \
103 ld8 reg2=[reg1];;
104
105 /*
106 * Adjust region registers saved before starting to save
107 * break regs and rest of the states that need to be preserved.
108 */
109 #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \
110 SAVE_FROM_REG(b0,_reg1,_reg2);; \
111 SAVE_FROM_REG(b1,_reg1,_reg2);; \
112 SAVE_FROM_REG(b2,_reg1,_reg2);; \
113 SAVE_FROM_REG(b3,_reg1,_reg2);; \
114 SAVE_FROM_REG(b4,_reg1,_reg2);; \
115 SAVE_FROM_REG(b5,_reg1,_reg2);; \
116 st8 [_reg1]=r1,0x08;; \
117 st8 [_reg1]=r12,0x08;; \
118 st8 [_reg1]=r13,0x08;; \
119 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \
120 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \
121 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \
122 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \
123 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \
124 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \
125 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \
126 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \
127 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \
128 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \
129 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \
130 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \
131 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \
132 st8 [_reg1]=r4,0x08;; \
133 st8 [_reg1]=r5,0x08;; \
134 st8 [_reg1]=r6,0x08;; \
135 st8 [_reg1]=r7,0x08;; \
136 st8 [_reg1]=_pred,0x08;; \
137 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \
138 stf.spill.nta [_reg1]=f2,16;; \
139 stf.spill.nta [_reg1]=f3,16;; \
140 stf.spill.nta [_reg1]=f4,16;; \
141 stf.spill.nta [_reg1]=f5,16;; \
142 stf.spill.nta [_reg1]=f16,16;; \
143 stf.spill.nta [_reg1]=f17,16;; \
144 stf.spill.nta [_reg1]=f18,16;; \
145 stf.spill.nta [_reg1]=f19,16;; \
146 stf.spill.nta [_reg1]=f20,16;; \
147 stf.spill.nta [_reg1]=f21,16;; \
148 stf.spill.nta [_reg1]=f22,16;; \
149 stf.spill.nta [_reg1]=f23,16;; \
150 stf.spill.nta [_reg1]=f24,16;; \
151 stf.spill.nta [_reg1]=f25,16;; \
152 stf.spill.nta [_reg1]=f26,16;; \
153 stf.spill.nta [_reg1]=f27,16;; \
154 stf.spill.nta [_reg1]=f28,16;; \
155 stf.spill.nta [_reg1]=f29,16;; \
156 stf.spill.nta [_reg1]=f30,16;; \
157 stf.spill.nta [_reg1]=f31,16;;
158
159 #else
160 #define SET_AREA_FOR_BOOTING_CPU(a1, a2)
161 #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3)
162 #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
163 #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
164 #endif
165
166 #define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
167 movl _tmp1=(num << 61);; \
168 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
169 mov rr[_tmp1]=_tmp2
170
171 .section __special_page_section,"ax"
172
173 .global empty_zero_page
174 empty_zero_page:
175 .skip PAGE_SIZE
176
177 .global swapper_pg_dir
178 swapper_pg_dir:
179 .skip PAGE_SIZE
180
181 .rodata
182 halt_msg:
183 stringz "Halting kernel\n"
184
185 .section .text.head,"ax"
186
187 .global start_ap
188
189 /*
190 * Start the kernel. When the bootloader passes control to _start(), r28
191 * points to the address of the boot parameter area. Execution reaches
192 * here in physical mode.
193 */
194 GLOBAL_ENTRY(_start)
195 start_ap:
196 .prologue
197 .save rp, r0 // terminate unwind chain with a NULL rp
198 .body
199
200 rsm psr.i | psr.ic
201 ;;
202 srlz.i
203 ;;
204 {
205 flushrs // must be first insn in group
206 srlz.i
207 }
208 ;;
209 /*
210 * Save the region registers, predicate before they get clobbered
211 */
212 SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15);
213 mov r25=pr;;
214
215 /*
216 * Initialize kernel region registers:
217 * rr[0]: VHPT enabled, page size = PAGE_SHIFT
218 * rr[1]: VHPT enabled, page size = PAGE_SHIFT
219 * rr[2]: VHPT enabled, page size = PAGE_SHIFT
220 * rr[3]: VHPT enabled, page size = PAGE_SHIFT
221 * rr[4]: VHPT enabled, page size = PAGE_SHIFT
222 * rr[5]: VHPT enabled, page size = PAGE_SHIFT
223 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
224 * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
225 * We initialize all of them to prevent inadvertently assuming
226 * something about the state of address translation early in boot.
227 */
228 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
229 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
230 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
231 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
232 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
233 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
234 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
235 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
236 /*
237 * Now pin mappings into the TLB for kernel text and data
238 */
239 mov r18=KERNEL_TR_PAGE_SHIFT<<2
240 movl r17=KERNEL_START
241 ;;
242 mov cr.itir=r18
243 mov cr.ifa=r17
244 mov r16=IA64_TR_KERNEL
245 mov r3=ip
246 movl r18=PAGE_KERNEL
247 ;;
248 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
249 ;;
250 or r18=r2,r18
251 ;;
252 srlz.i
253 ;;
254 itr.i itr[r16]=r18
255 ;;
256 itr.d dtr[r16]=r18
257 ;;
258 srlz.i
259
260 /*
261 * Switch into virtual mode:
262 */
263 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
264 |IA64_PSR_DI|IA64_PSR_AC)
265 ;;
266 mov cr.ipsr=r16
267 movl r17=1f
268 ;;
269 mov cr.iip=r17
270 mov cr.ifs=r0
271 ;;
272 rfi
273 ;;
274 1: // now we are in virtual mode
275
276 SET_AREA_FOR_BOOTING_CPU(r2, r16);
277
278 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15);
279 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
280 ;;
281
282 // set IVT entry point---can't access I/O ports without it
283 movl r3=ia64_ivt
284 ;;
285 mov cr.iva=r3
286 movl r2=FPSR_DEFAULT
287 ;;
288 srlz.i
289 movl gp=__gp
290
291 mov ar.fpsr=r2
292 ;;
293
294 #define isAP p2 // are we an Application Processor?
295 #define isBP p3 // are we the Bootstrap Processor?
296
297 #ifdef CONFIG_SMP
298 /*
299 * Find the init_task for the currently booting CPU. At poweron, and in
300 * UP mode, task_for_booting_cpu is NULL.
301 */
302 movl r3=task_for_booting_cpu
303 ;;
304 ld8 r3=[r3]
305 movl r2=init_task
306 ;;
307 cmp.eq isBP,isAP=r3,r0
308 ;;
309 (isAP) mov r2=r3
310 #else
311 movl r2=init_task
312 cmp.eq isBP,isAP=r0,r0
313 #endif
314 ;;
315 tpa r3=r2 // r3 == phys addr of task struct
316 mov r16=-1
317 (isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
318
319 // load mapping for stack (virtaddr in r2, physaddr in r3)
320 rsm psr.ic
321 movl r17=PAGE_KERNEL
322 ;;
323 srlz.d
324 dep r18=0,r3,0,12
325 ;;
326 or r18=r17,r18
327 dep r2=-1,r3,61,3 // IMVA of task
328 ;;
329 mov r17=rr[r2]
330 shr.u r16=r3,IA64_GRANULE_SHIFT
331 ;;
332 dep r17=0,r17,8,24
333 ;;
334 mov cr.itir=r17
335 mov cr.ifa=r2
336
337 mov r19=IA64_TR_CURRENT_STACK
338 ;;
339 itr.d dtr[r19]=r18
340 ;;
341 ssm psr.ic
342 srlz.d
343 ;;
344
345 .load_current:
346 // load the "current" pointer (r13) and ar.k6 with the current task
347 mov IA64_KR(CURRENT)=r2 // virtual address
348 mov IA64_KR(CURRENT_STACK)=r16
349 mov r13=r2
350 /*
351 * Reserve space at the top of the stack for "struct pt_regs". Kernel
352 * threads don't store interesting values in that structure, but the space
353 * still needs to be there because time-critical stuff such as the context
354 * switching can be implemented more efficiently (for example, __switch_to()
355 * always sets the psr.dfh bit of the task it is switching to).
356 */
357
358 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
359 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
360 mov ar.rsc=0 // place RSE in enforced lazy mode
361 ;;
362 loadrs // clear the dirty partition
363 movl r19=__phys_per_cpu_start
364 mov r18=PERCPU_PAGE_SIZE
365 ;;
366 #ifndef CONFIG_SMP
367 add r19=r19,r18
368 ;;
369 #else
370 (isAP) br.few 2f
371 movl r20=__cpu0_per_cpu
372 ;;
373 shr.u r18=r18,3
374 1:
375 ld8 r21=[r19],8;;
376 st8[r20]=r21,8
377 adds r18=-1,r18;;
378 cmp4.lt p7,p6=0,r18
379 (p7) br.cond.dptk.few 1b
380 mov r19=r20
381 ;;
382 2:
383 #endif
384 tpa r19=r19
385 ;;
386 .pred.rel.mutex isBP,isAP
387 (isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0
388 (isAP) mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base
389 ;;
390 mov ar.bspstore=r2 // establish the new RSE stack
391 ;;
392 mov ar.rsc=0x3 // place RSE in eager mode
393
394 (isBP) dep r28=-1,r28,61,3 // make address virtual
395 (isBP) movl r2=ia64_boot_param
396 ;;
397 (isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader
398
399 #ifdef CONFIG_PARAVIRT
400
401 movl r14=hypervisor_setup_hooks
402 movl r15=hypervisor_type
403 mov r16=num_hypervisor_hooks
404 ;;
405 ld8 r2=[r15]
406 ;;
407 cmp.ltu p7,p0=r2,r16 // array size check
408 shladd r8=r2,3,r14
409 ;;
410 (p7) ld8 r9=[r8]
411 ;;
412 (p7) mov b1=r9
413 (p7) cmp.ne.unc p7,p0=r9,r0 // no actual branch to NULL
414 ;;
415 (p7) br.call.sptk.many rp=b1
416
417 __INITDATA
418
419 default_setup_hook = 0 // Currently nothing needs to be done.
420
421 .weak xen_setup_hook
422
423 .global hypervisor_type
424 hypervisor_type:
425 data8 PARAVIRT_HYPERVISOR_TYPE_DEFAULT
426
427 // must have the same order with PARAVIRT_HYPERVISOR_TYPE_xxx
428
429 hypervisor_setup_hooks:
430 data8 default_setup_hook
431 data8 xen_setup_hook
432 num_hypervisor_hooks = (. - hypervisor_setup_hooks) / 8
433 .previous
434
435 #endif
436
437 #ifdef CONFIG_SMP
438 (isAP) br.call.sptk.many rp=start_secondary
439 .ret0:
440 (isAP) br.cond.sptk self
441 #endif
442
443 // This is executed by the bootstrap processor (bsp) only:
444
445 #ifdef CONFIG_IA64_FW_EMU
446 // initialize PAL & SAL emulator:
447 br.call.sptk.many rp=sys_fw_init
448 .ret1:
449 #endif
450 br.call.sptk.many rp=start_kernel
451 .ret2: addl r3=@ltoff(halt_msg),gp
452 ;;
453 alloc r2=ar.pfs,8,0,2,0
454 ;;
455 ld8 out0=[r3]
456 br.call.sptk.many b0=console_print
457
458 self: hint @pause
459 br.sptk.many self // endless loop
460 END(_start)
461
462 .text
463
464 GLOBAL_ENTRY(ia64_save_debug_regs)
465 alloc r16=ar.pfs,1,0,0,0
466 mov r20=ar.lc // preserve ar.lc
467 mov ar.lc=IA64_NUM_DBG_REGS-1
468 mov r18=0
469 add r19=IA64_NUM_DBG_REGS*8,in0
470 ;;
471 1: mov r16=dbr[r18]
472 #ifdef CONFIG_ITANIUM
473 ;;
474 srlz.d
475 #endif
476 mov r17=ibr[r18]
477 add r18=1,r18
478 ;;
479 st8.nta [in0]=r16,8
480 st8.nta [r19]=r17,8
481 br.cloop.sptk.many 1b
482 ;;
483 mov ar.lc=r20 // restore ar.lc
484 br.ret.sptk.many rp
485 END(ia64_save_debug_regs)
486
487 GLOBAL_ENTRY(ia64_load_debug_regs)
488 alloc r16=ar.pfs,1,0,0,0
489 lfetch.nta [in0]
490 mov r20=ar.lc // preserve ar.lc
491 add r19=IA64_NUM_DBG_REGS*8,in0
492 mov ar.lc=IA64_NUM_DBG_REGS-1
493 mov r18=-1
494 ;;
495 1: ld8.nta r16=[in0],8
496 ld8.nta r17=[r19],8
497 add r18=1,r18
498 ;;
499 mov dbr[r18]=r16
500 #ifdef CONFIG_ITANIUM
501 ;;
502 srlz.d // Errata 132 (NoFix status)
503 #endif
504 mov ibr[r18]=r17
505 br.cloop.sptk.many 1b
506 ;;
507 mov ar.lc=r20 // restore ar.lc
508 br.ret.sptk.many rp
509 END(ia64_load_debug_regs)
510
511 GLOBAL_ENTRY(__ia64_save_fpu)
512 alloc r2=ar.pfs,1,4,0,0
513 adds loc0=96*16-16,in0
514 adds loc1=96*16-16-128,in0
515 ;;
516 stf.spill.nta [loc0]=f127,-256
517 stf.spill.nta [loc1]=f119,-256
518 ;;
519 stf.spill.nta [loc0]=f111,-256
520 stf.spill.nta [loc1]=f103,-256
521 ;;
522 stf.spill.nta [loc0]=f95,-256
523 stf.spill.nta [loc1]=f87,-256
524 ;;
525 stf.spill.nta [loc0]=f79,-256
526 stf.spill.nta [loc1]=f71,-256
527 ;;
528 stf.spill.nta [loc0]=f63,-256
529 stf.spill.nta [loc1]=f55,-256
530 adds loc2=96*16-32,in0
531 ;;
532 stf.spill.nta [loc0]=f47,-256
533 stf.spill.nta [loc1]=f39,-256
534 adds loc3=96*16-32-128,in0
535 ;;
536 stf.spill.nta [loc2]=f126,-256
537 stf.spill.nta [loc3]=f118,-256
538 ;;
539 stf.spill.nta [loc2]=f110,-256
540 stf.spill.nta [loc3]=f102,-256
541 ;;
542 stf.spill.nta [loc2]=f94,-256
543 stf.spill.nta [loc3]=f86,-256
544 ;;
545 stf.spill.nta [loc2]=f78,-256
546 stf.spill.nta [loc3]=f70,-256
547 ;;
548 stf.spill.nta [loc2]=f62,-256
549 stf.spill.nta [loc3]=f54,-256
550 adds loc0=96*16-48,in0
551 ;;
552 stf.spill.nta [loc2]=f46,-256
553 stf.spill.nta [loc3]=f38,-256
554 adds loc1=96*16-48-128,in0
555 ;;
556 stf.spill.nta [loc0]=f125,-256
557 stf.spill.nta [loc1]=f117,-256
558 ;;
559 stf.spill.nta [loc0]=f109,-256
560 stf.spill.nta [loc1]=f101,-256
561 ;;
562 stf.spill.nta [loc0]=f93,-256
563 stf.spill.nta [loc1]=f85,-256
564 ;;
565 stf.spill.nta [loc0]=f77,-256
566 stf.spill.nta [loc1]=f69,-256
567 ;;
568 stf.spill.nta [loc0]=f61,-256
569 stf.spill.nta [loc1]=f53,-256
570 adds loc2=96*16-64,in0
571 ;;
572 stf.spill.nta [loc0]=f45,-256
573 stf.spill.nta [loc1]=f37,-256
574 adds loc3=96*16-64-128,in0
575 ;;
576 stf.spill.nta [loc2]=f124,-256
577 stf.spill.nta [loc3]=f116,-256
578 ;;
579 stf.spill.nta [loc2]=f108,-256
580 stf.spill.nta [loc3]=f100,-256
581 ;;
582 stf.spill.nta [loc2]=f92,-256
583 stf.spill.nta [loc3]=f84,-256
584 ;;
585 stf.spill.nta [loc2]=f76,-256
586 stf.spill.nta [loc3]=f68,-256
587 ;;
588 stf.spill.nta [loc2]=f60,-256
589 stf.spill.nta [loc3]=f52,-256
590 adds loc0=96*16-80,in0
591 ;;
592 stf.spill.nta [loc2]=f44,-256
593 stf.spill.nta [loc3]=f36,-256
594 adds loc1=96*16-80-128,in0
595 ;;
596 stf.spill.nta [loc0]=f123,-256
597 stf.spill.nta [loc1]=f115,-256
598 ;;
599 stf.spill.nta [loc0]=f107,-256
600 stf.spill.nta [loc1]=f99,-256
601 ;;
602 stf.spill.nta [loc0]=f91,-256
603 stf.spill.nta [loc1]=f83,-256
604 ;;
605 stf.spill.nta [loc0]=f75,-256
606 stf.spill.nta [loc1]=f67,-256
607 ;;
608 stf.spill.nta [loc0]=f59,-256
609 stf.spill.nta [loc1]=f51,-256
610 adds loc2=96*16-96,in0
611 ;;
612 stf.spill.nta [loc0]=f43,-256
613 stf.spill.nta [loc1]=f35,-256
614 adds loc3=96*16-96-128,in0
615 ;;
616 stf.spill.nta [loc2]=f122,-256
617 stf.spill.nta [loc3]=f114,-256
618 ;;
619 stf.spill.nta [loc2]=f106,-256
620 stf.spill.nta [loc3]=f98,-256
621 ;;
622 stf.spill.nta [loc2]=f90,-256
623 stf.spill.nta [loc3]=f82,-256
624 ;;
625 stf.spill.nta [loc2]=f74,-256
626 stf.spill.nta [loc3]=f66,-256
627 ;;
628 stf.spill.nta [loc2]=f58,-256
629 stf.spill.nta [loc3]=f50,-256
630 adds loc0=96*16-112,in0
631 ;;
632 stf.spill.nta [loc2]=f42,-256
633 stf.spill.nta [loc3]=f34,-256
634 adds loc1=96*16-112-128,in0
635 ;;
636 stf.spill.nta [loc0]=f121,-256
637 stf.spill.nta [loc1]=f113,-256
638 ;;
639 stf.spill.nta [loc0]=f105,-256
640 stf.spill.nta [loc1]=f97,-256
641 ;;
642 stf.spill.nta [loc0]=f89,-256
643 stf.spill.nta [loc1]=f81,-256
644 ;;
645 stf.spill.nta [loc0]=f73,-256
646 stf.spill.nta [loc1]=f65,-256
647 ;;
648 stf.spill.nta [loc0]=f57,-256
649 stf.spill.nta [loc1]=f49,-256
650 adds loc2=96*16-128,in0
651 ;;
652 stf.spill.nta [loc0]=f41,-256
653 stf.spill.nta [loc1]=f33,-256
654 adds loc3=96*16-128-128,in0
655 ;;
656 stf.spill.nta [loc2]=f120,-256
657 stf.spill.nta [loc3]=f112,-256
658 ;;
659 stf.spill.nta [loc2]=f104,-256
660 stf.spill.nta [loc3]=f96,-256
661 ;;
662 stf.spill.nta [loc2]=f88,-256
663 stf.spill.nta [loc3]=f80,-256
664 ;;
665 stf.spill.nta [loc2]=f72,-256
666 stf.spill.nta [loc3]=f64,-256
667 ;;
668 stf.spill.nta [loc2]=f56,-256
669 stf.spill.nta [loc3]=f48,-256
670 ;;
671 stf.spill.nta [loc2]=f40
672 stf.spill.nta [loc3]=f32
673 br.ret.sptk.many rp
674 END(__ia64_save_fpu)
675
676 GLOBAL_ENTRY(__ia64_load_fpu)
677 alloc r2=ar.pfs,1,2,0,0
678 adds r3=128,in0
679 adds r14=256,in0
680 adds r15=384,in0
681 mov loc0=512
682 mov loc1=-1024+16
683 ;;
684 ldf.fill.nta f32=[in0],loc0
685 ldf.fill.nta f40=[ r3],loc0
686 ldf.fill.nta f48=[r14],loc0
687 ldf.fill.nta f56=[r15],loc0
688 ;;
689 ldf.fill.nta f64=[in0],loc0
690 ldf.fill.nta f72=[ r3],loc0
691 ldf.fill.nta f80=[r14],loc0
692 ldf.fill.nta f88=[r15],loc0
693 ;;
694 ldf.fill.nta f96=[in0],loc1
695 ldf.fill.nta f104=[ r3],loc1
696 ldf.fill.nta f112=[r14],loc1
697 ldf.fill.nta f120=[r15],loc1
698 ;;
699 ldf.fill.nta f33=[in0],loc0
700 ldf.fill.nta f41=[ r3],loc0
701 ldf.fill.nta f49=[r14],loc0
702 ldf.fill.nta f57=[r15],loc0
703 ;;
704 ldf.fill.nta f65=[in0],loc0
705 ldf.fill.nta f73=[ r3],loc0
706 ldf.fill.nta f81=[r14],loc0
707 ldf.fill.nta f89=[r15],loc0
708 ;;
709 ldf.fill.nta f97=[in0],loc1
710 ldf.fill.nta f105=[ r3],loc1
711 ldf.fill.nta f113=[r14],loc1
712 ldf.fill.nta f121=[r15],loc1
713 ;;
714 ldf.fill.nta f34=[in0],loc0
715 ldf.fill.nta f42=[ r3],loc0
716 ldf.fill.nta f50=[r14],loc0
717 ldf.fill.nta f58=[r15],loc0
718 ;;
719 ldf.fill.nta f66=[in0],loc0
720 ldf.fill.nta f74=[ r3],loc0
721 ldf.fill.nta f82=[r14],loc0
722 ldf.fill.nta f90=[r15],loc0
723 ;;
724 ldf.fill.nta f98=[in0],loc1
725 ldf.fill.nta f106=[ r3],loc1
726 ldf.fill.nta f114=[r14],loc1
727 ldf.fill.nta f122=[r15],loc1
728 ;;
729 ldf.fill.nta f35=[in0],loc0
730 ldf.fill.nta f43=[ r3],loc0
731 ldf.fill.nta f51=[r14],loc0
732 ldf.fill.nta f59=[r15],loc0
733 ;;
734 ldf.fill.nta f67=[in0],loc0
735 ldf.fill.nta f75=[ r3],loc0
736 ldf.fill.nta f83=[r14],loc0
737 ldf.fill.nta f91=[r15],loc0
738 ;;
739 ldf.fill.nta f99=[in0],loc1
740 ldf.fill.nta f107=[ r3],loc1
741 ldf.fill.nta f115=[r14],loc1
742 ldf.fill.nta f123=[r15],loc1
743 ;;
744 ldf.fill.nta f36=[in0],loc0
745 ldf.fill.nta f44=[ r3],loc0
746 ldf.fill.nta f52=[r14],loc0
747 ldf.fill.nta f60=[r15],loc0
748 ;;
749 ldf.fill.nta f68=[in0],loc0
750 ldf.fill.nta f76=[ r3],loc0
751 ldf.fill.nta f84=[r14],loc0
752 ldf.fill.nta f92=[r15],loc0
753 ;;
754 ldf.fill.nta f100=[in0],loc1
755 ldf.fill.nta f108=[ r3],loc1
756 ldf.fill.nta f116=[r14],loc1
757 ldf.fill.nta f124=[r15],loc1
758 ;;
759 ldf.fill.nta f37=[in0],loc0
760 ldf.fill.nta f45=[ r3],loc0
761 ldf.fill.nta f53=[r14],loc0
762 ldf.fill.nta f61=[r15],loc0
763 ;;
764 ldf.fill.nta f69=[in0],loc0
765 ldf.fill.nta f77=[ r3],loc0
766 ldf.fill.nta f85=[r14],loc0
767 ldf.fill.nta f93=[r15],loc0
768 ;;
769 ldf.fill.nta f101=[in0],loc1
770 ldf.fill.nta f109=[ r3],loc1
771 ldf.fill.nta f117=[r14],loc1
772 ldf.fill.nta f125=[r15],loc1
773 ;;
774 ldf.fill.nta f38 =[in0],loc0
775 ldf.fill.nta f46 =[ r3],loc0
776 ldf.fill.nta f54 =[r14],loc0
777 ldf.fill.nta f62 =[r15],loc0
778 ;;
779 ldf.fill.nta f70 =[in0],loc0
780 ldf.fill.nta f78 =[ r3],loc0
781 ldf.fill.nta f86 =[r14],loc0
782 ldf.fill.nta f94 =[r15],loc0
783 ;;
784 ldf.fill.nta f102=[in0],loc1
785 ldf.fill.nta f110=[ r3],loc1
786 ldf.fill.nta f118=[r14],loc1
787 ldf.fill.nta f126=[r15],loc1
788 ;;
789 ldf.fill.nta f39 =[in0],loc0
790 ldf.fill.nta f47 =[ r3],loc0
791 ldf.fill.nta f55 =[r14],loc0
792 ldf.fill.nta f63 =[r15],loc0
793 ;;
794 ldf.fill.nta f71 =[in0],loc0
795 ldf.fill.nta f79 =[ r3],loc0
796 ldf.fill.nta f87 =[r14],loc0
797 ldf.fill.nta f95 =[r15],loc0
798 ;;
799 ldf.fill.nta f103=[in0]
800 ldf.fill.nta f111=[ r3]
801 ldf.fill.nta f119=[r14]
802 ldf.fill.nta f127=[r15]
803 br.ret.sptk.many rp
804 END(__ia64_load_fpu)
805
806 GLOBAL_ENTRY(__ia64_init_fpu)
807 stf.spill [sp]=f0 // M3
808 mov f32=f0 // F
809 nop.b 0
810
811 ldfps f33,f34=[sp] // M0
812 ldfps f35,f36=[sp] // M1
813 mov f37=f0 // F
814 ;;
815
816 setf.s f38=r0 // M2
817 setf.s f39=r0 // M3
818 mov f40=f0 // F
819
820 ldfps f41,f42=[sp] // M0
821 ldfps f43,f44=[sp] // M1
822 mov f45=f0 // F
823
824 setf.s f46=r0 // M2
825 setf.s f47=r0 // M3
826 mov f48=f0 // F
827
828 ldfps f49,f50=[sp] // M0
829 ldfps f51,f52=[sp] // M1
830 mov f53=f0 // F
831
832 setf.s f54=r0 // M2
833 setf.s f55=r0 // M3
834 mov f56=f0 // F
835
836 ldfps f57,f58=[sp] // M0
837 ldfps f59,f60=[sp] // M1
838 mov f61=f0 // F
839
840 setf.s f62=r0 // M2
841 setf.s f63=r0 // M3
842 mov f64=f0 // F
843
844 ldfps f65,f66=[sp] // M0
845 ldfps f67,f68=[sp] // M1
846 mov f69=f0 // F
847
848 setf.s f70=r0 // M2
849 setf.s f71=r0 // M3
850 mov f72=f0 // F
851
852 ldfps f73,f74=[sp] // M0
853 ldfps f75,f76=[sp] // M1
854 mov f77=f0 // F
855
856 setf.s f78=r0 // M2
857 setf.s f79=r0 // M3
858 mov f80=f0 // F
859
860 ldfps f81,f82=[sp] // M0
861 ldfps f83,f84=[sp] // M1
862 mov f85=f0 // F
863
864 setf.s f86=r0 // M2
865 setf.s f87=r0 // M3
866 mov f88=f0 // F
867
868 /*
869 * When the instructions are cached, it would be faster to initialize
870 * the remaining registers with simply mov instructions (F-unit).
871 * This gets the time down to ~29 cycles. However, this would use up
872 * 33 bundles, whereas continuing with the above pattern yields
873 * 10 bundles and ~30 cycles.
874 */
875
876 ldfps f89,f90=[sp] // M0
877 ldfps f91,f92=[sp] // M1
878 mov f93=f0 // F
879
880 setf.s f94=r0 // M2
881 setf.s f95=r0 // M3
882 mov f96=f0 // F
883
884 ldfps f97,f98=[sp] // M0
885 ldfps f99,f100=[sp] // M1
886 mov f101=f0 // F
887
888 setf.s f102=r0 // M2
889 setf.s f103=r0 // M3
890 mov f104=f0 // F
891
892 ldfps f105,f106=[sp] // M0
893 ldfps f107,f108=[sp] // M1
894 mov f109=f0 // F
895
896 setf.s f110=r0 // M2
897 setf.s f111=r0 // M3
898 mov f112=f0 // F
899
900 ldfps f113,f114=[sp] // M0
901 ldfps f115,f116=[sp] // M1
902 mov f117=f0 // F
903
904 setf.s f118=r0 // M2
905 setf.s f119=r0 // M3
906 mov f120=f0 // F
907
908 ldfps f121,f122=[sp] // M0
909 ldfps f123,f124=[sp] // M1
910 mov f125=f0 // F
911
912 setf.s f126=r0 // M2
913 setf.s f127=r0 // M3
914 br.ret.sptk.many rp // F
915 END(__ia64_init_fpu)
916
917 /*
918 * Switch execution mode from virtual to physical
919 *
920 * Inputs:
921 * r16 = new psr to establish
922 * Output:
923 * r19 = old virtual address of ar.bsp
924 * r20 = old virtual address of sp
925 *
926 * Note: RSE must already be in enforced lazy mode
927 */
928 GLOBAL_ENTRY(ia64_switch_mode_phys)
929 {
930 rsm psr.i | psr.ic // disable interrupts and interrupt collection
931 mov r15=ip
932 }
933 ;;
934 {
935 flushrs // must be first insn in group
936 srlz.i
937 }
938 ;;
939 mov cr.ipsr=r16 // set new PSR
940 add r3=1f-ia64_switch_mode_phys,r15
941
942 mov r19=ar.bsp
943 mov r20=sp
944 mov r14=rp // get return address into a general register
945 ;;
946
947 // going to physical mode, use tpa to translate virt->phys
948 tpa r17=r19
949 tpa r3=r3
950 tpa sp=sp
951 tpa r14=r14
952 ;;
953
954 mov r18=ar.rnat // save ar.rnat
955 mov ar.bspstore=r17 // this steps on ar.rnat
956 mov cr.iip=r3
957 mov cr.ifs=r0
958 ;;
959 mov ar.rnat=r18 // restore ar.rnat
960 rfi // must be last insn in group
961 ;;
962 1: mov rp=r14
963 br.ret.sptk.many rp
964 END(ia64_switch_mode_phys)
965
966 /*
967 * Switch execution mode from physical to virtual
968 *
969 * Inputs:
970 * r16 = new psr to establish
971 * r19 = new bspstore to establish
972 * r20 = new sp to establish
973 *
974 * Note: RSE must already be in enforced lazy mode
975 */
976 GLOBAL_ENTRY(ia64_switch_mode_virt)
977 {
978 rsm psr.i | psr.ic // disable interrupts and interrupt collection
979 mov r15=ip
980 }
981 ;;
982 {
983 flushrs // must be first insn in group
984 srlz.i
985 }
986 ;;
987 mov cr.ipsr=r16 // set new PSR
988 add r3=1f-ia64_switch_mode_virt,r15
989
990 mov r14=rp // get return address into a general register
991 ;;
992
993 // going to virtual
994 // - for code addresses, set upper bits of addr to KERNEL_START
995 // - for stack addresses, copy from input argument
996 movl r18=KERNEL_START
997 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
998 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
999 mov sp=r20
1000 ;;
1001 or r3=r3,r18
1002 or r14=r14,r18
1003 ;;
1004
1005 mov r18=ar.rnat // save ar.rnat
1006 mov ar.bspstore=r19 // this steps on ar.rnat
1007 mov cr.iip=r3
1008 mov cr.ifs=r0
1009 ;;
1010 mov ar.rnat=r18 // restore ar.rnat
1011 rfi // must be last insn in group
1012 ;;
1013 1: mov rp=r14
1014 br.ret.sptk.many rp
1015 END(ia64_switch_mode_virt)
1016
1017 GLOBAL_ENTRY(ia64_delay_loop)
1018 .prologue
1019 { nop 0 // work around GAS unwind info generation bug...
1020 .save ar.lc,r2
1021 mov r2=ar.lc
1022 .body
1023 ;;
1024 mov ar.lc=r32
1025 }
1026 ;;
1027 // force loop to be 32-byte aligned (GAS bug means we cannot use .align
1028 // inside function body without corrupting unwind info).
1029 { nop 0 }
1030 1: br.cloop.sptk.few 1b
1031 ;;
1032 mov ar.lc=r2
1033 br.ret.sptk.many rp
1034 END(ia64_delay_loop)
1035
1036 /*
1037 * Return a CPU-local timestamp in nano-seconds. This timestamp is
1038 * NOT synchronized across CPUs its return value must never be
1039 * compared against the values returned on another CPU. The usage in
1040 * kernel/sched.c ensures that.
1041 *
1042 * The return-value of sched_clock() is NOT supposed to wrap-around.
1043 * If it did, it would cause some scheduling hiccups (at the worst).
1044 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
1045 * that would happen only once every 5+ years.
1046 *
1047 * The code below basically calculates:
1048 *
1049 * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
1050 *
1051 * except that the multiplication and the shift are done with 128-bit
1052 * intermediate precision so that we can produce a full 64-bit result.
1053 */
1054 GLOBAL_ENTRY(ia64_native_sched_clock)
1055 addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1056 mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
1057 ;;
1058 ldf8 f8=[r8]
1059 ;;
1060 setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8...
1061 ;;
1062 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1063 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
1064 ;;
1065 getf.sig r8=f10 // (5 cyc)
1066 getf.sig r9=f11
1067 ;;
1068 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1069 br.ret.sptk.many rp
1070 END(ia64_native_sched_clock)
1071 #ifndef CONFIG_PARAVIRT
1072 //unsigned long long
1073 //sched_clock(void) __attribute__((alias("ia64_native_sched_clock")));
1074 .global sched_clock
1075 sched_clock = ia64_native_sched_clock
1076 #endif
1077
1078 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
1079 GLOBAL_ENTRY(cycle_to_cputime)
1080 alloc r16=ar.pfs,1,0,0,0
1081 addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1082 ;;
1083 ldf8 f8=[r8]
1084 ;;
1085 setf.sig f9=r32
1086 ;;
1087 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1088 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
1089 ;;
1090 getf.sig r8=f10 // (5 cyc)
1091 getf.sig r9=f11
1092 ;;
1093 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1094 br.ret.sptk.many rp
1095 END(cycle_to_cputime)
1096 #endif /* CONFIG_VIRT_CPU_ACCOUNTING */
1097
1098 GLOBAL_ENTRY(start_kernel_thread)
1099 .prologue
1100 .save rp, r0 // this is the end of the call-chain
1101 .body
1102 alloc r2 = ar.pfs, 0, 0, 2, 0
1103 mov out0 = r9
1104 mov out1 = r11;;
1105 br.call.sptk.many rp = kernel_thread_helper;;
1106 mov out0 = r8
1107 br.call.sptk.many rp = sys_exit;;
1108 1: br.sptk.few 1b // not reached
1109 END(start_kernel_thread)
1110
1111 #ifdef CONFIG_IA64_BRL_EMU
1112
1113 /*
1114 * Assembly routines used by brl_emu.c to set preserved register state.
1115 */
1116
1117 #define SET_REG(reg) \
1118 GLOBAL_ENTRY(ia64_set_##reg); \
1119 alloc r16=ar.pfs,1,0,0,0; \
1120 mov reg=r32; \
1121 ;; \
1122 br.ret.sptk.many rp; \
1123 END(ia64_set_##reg)
1124
1125 SET_REG(b1);
1126 SET_REG(b2);
1127 SET_REG(b3);
1128 SET_REG(b4);
1129 SET_REG(b5);
1130
1131 #endif /* CONFIG_IA64_BRL_EMU */
1132
1133 #ifdef CONFIG_SMP
1134 /*
1135 * This routine handles spinlock contention. It uses a non-standard calling
1136 * convention to avoid converting leaf routines into interior routines. Because
1137 * of this special convention, there are several restrictions:
1138 *
1139 * - do not use gp relative variables, this code is called from the kernel
1140 * and from modules, r1 is undefined.
1141 * - do not use stacked registers, the caller owns them.
1142 * - do not use the scratch stack space, the caller owns it.
1143 * - do not use any registers other than the ones listed below
1144 *
1145 * Inputs:
1146 * ar.pfs - saved CFM of caller
1147 * ar.ccv - 0 (and available for use)
1148 * r27 - flags from spin_lock_irqsave or 0. Must be preserved.
1149 * r28 - available for use.
1150 * r29 - available for use.
1151 * r30 - available for use.
1152 * r31 - address of lock, available for use.
1153 * b6 - return address
1154 * p14 - available for use.
1155 * p15 - used to track flag status.
1156 *
1157 * If you patch this code to use more registers, do not forget to update
1158 * the clobber lists for spin_lock() in arch/ia64/include/asm/spinlock.h.
1159 */
1160
1161 #if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
1162
1163 GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4)
1164 .prologue
1165 .save ar.pfs, r0 // this code effectively has a zero frame size
1166 .save rp, r28
1167 .body
1168 nop 0
1169 tbit.nz p15,p0=r27,IA64_PSR_I_BIT
1170 .restore sp // pop existing prologue after next insn
1171 mov b6 = r28
1172 .prologue
1173 .save ar.pfs, r0
1174 .altrp b6
1175 .body
1176 ;;
1177 (p15) ssm psr.i // reenable interrupts if they were on
1178 // DavidM says that srlz.d is slow and is not required in this case
1179 .wait:
1180 // exponential backoff, kdb, lockmeter etc. go in here
1181 hint @pause
1182 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
1183 nop 0
1184 ;;
1185 cmp4.ne p14,p0=r30,r0
1186 (p14) br.cond.sptk.few .wait
1187 (p15) rsm psr.i // disable interrupts if we reenabled them
1188 br.cond.sptk.few b6 // lock is now free, try to acquire
1189 .global ia64_spinlock_contention_pre3_4_end // for kernprof
1190 ia64_spinlock_contention_pre3_4_end:
1191 END(ia64_spinlock_contention_pre3_4)
1192
1193 #else
1194
1195 GLOBAL_ENTRY(ia64_spinlock_contention)
1196 .prologue
1197 .altrp b6
1198 .body
1199 tbit.nz p15,p0=r27,IA64_PSR_I_BIT
1200 ;;
1201 .wait:
1202 (p15) ssm psr.i // reenable interrupts if they were on
1203 // DavidM says that srlz.d is slow and is not required in this case
1204 .wait2:
1205 // exponential backoff, kdb, lockmeter etc. go in here
1206 hint @pause
1207 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
1208 ;;
1209 cmp4.ne p14,p0=r30,r0
1210 mov r30 = 1
1211 (p14) br.cond.sptk.few .wait2
1212 (p15) rsm psr.i // disable interrupts if we reenabled them
1213 ;;
1214 cmpxchg4.acq r30=[r31], r30, ar.ccv
1215 ;;
1216 cmp4.ne p14,p0=r0,r30
1217 (p14) br.cond.sptk.few .wait
1218
1219 br.ret.sptk.many b6 // lock is now taken
1220 END(ia64_spinlock_contention)
1221
1222 #endif
1223
1224 #ifdef CONFIG_HOTPLUG_CPU
1225 GLOBAL_ENTRY(ia64_jump_to_sal)
1226 alloc r16=ar.pfs,1,0,0,0;;
1227 rsm psr.i | psr.ic
1228 {
1229 flushrs
1230 srlz.i
1231 }
1232 tpa r25=in0
1233 movl r18=tlb_purge_done;;
1234 DATA_VA_TO_PA(r18);;
1235 mov b1=r18 // Return location
1236 movl r18=ia64_do_tlb_purge;;
1237 DATA_VA_TO_PA(r18);;
1238 mov b2=r18 // doing tlb_flush work
1239 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1240 movl r17=1f;;
1241 DATA_VA_TO_PA(r17);;
1242 mov cr.iip=r17
1243 movl r16=SAL_PSR_BITS_TO_SET;;
1244 mov cr.ipsr=r16
1245 mov cr.ifs=r0;;
1246 rfi;;
1247 1:
1248 /*
1249 * Invalidate all TLB data/inst
1250 */
1251 br.sptk.many b2;; // jump to tlb purge code
1252
1253 tlb_purge_done:
1254 RESTORE_REGION_REGS(r25, r17,r18,r19);;
1255 RESTORE_REG(b0, r25, r17);;
1256 RESTORE_REG(b1, r25, r17);;
1257 RESTORE_REG(b2, r25, r17);;
1258 RESTORE_REG(b3, r25, r17);;
1259 RESTORE_REG(b4, r25, r17);;
1260 RESTORE_REG(b5, r25, r17);;
1261 ld8 r1=[r25],0x08;;
1262 ld8 r12=[r25],0x08;;
1263 ld8 r13=[r25],0x08;;
1264 RESTORE_REG(ar.fpsr, r25, r17);;
1265 RESTORE_REG(ar.pfs, r25, r17);;
1266 RESTORE_REG(ar.rnat, r25, r17);;
1267 RESTORE_REG(ar.unat, r25, r17);;
1268 RESTORE_REG(ar.bspstore, r25, r17);;
1269 RESTORE_REG(cr.dcr, r25, r17);;
1270 RESTORE_REG(cr.iva, r25, r17);;
1271 RESTORE_REG(cr.pta, r25, r17);;
1272 srlz.d;; // required not to violate RAW dependency
1273 RESTORE_REG(cr.itv, r25, r17);;
1274 RESTORE_REG(cr.pmv, r25, r17);;
1275 RESTORE_REG(cr.cmcv, r25, r17);;
1276 RESTORE_REG(cr.lrr0, r25, r17);;
1277 RESTORE_REG(cr.lrr1, r25, r17);;
1278 ld8 r4=[r25],0x08;;
1279 ld8 r5=[r25],0x08;;
1280 ld8 r6=[r25],0x08;;
1281 ld8 r7=[r25],0x08;;
1282 ld8 r17=[r25],0x08;;
1283 mov pr=r17,-1;;
1284 RESTORE_REG(ar.lc, r25, r17);;
1285 /*
1286 * Now Restore floating point regs
1287 */
1288 ldf.fill.nta f2=[r25],16;;
1289 ldf.fill.nta f3=[r25],16;;
1290 ldf.fill.nta f4=[r25],16;;
1291 ldf.fill.nta f5=[r25],16;;
1292 ldf.fill.nta f16=[r25],16;;
1293 ldf.fill.nta f17=[r25],16;;
1294 ldf.fill.nta f18=[r25],16;;
1295 ldf.fill.nta f19=[r25],16;;
1296 ldf.fill.nta f20=[r25],16;;
1297 ldf.fill.nta f21=[r25],16;;
1298 ldf.fill.nta f22=[r25],16;;
1299 ldf.fill.nta f23=[r25],16;;
1300 ldf.fill.nta f24=[r25],16;;
1301 ldf.fill.nta f25=[r25],16;;
1302 ldf.fill.nta f26=[r25],16;;
1303 ldf.fill.nta f27=[r25],16;;
1304 ldf.fill.nta f28=[r25],16;;
1305 ldf.fill.nta f29=[r25],16;;
1306 ldf.fill.nta f30=[r25],16;;
1307 ldf.fill.nta f31=[r25],16;;
1308
1309 /*
1310 * Now that we have done all the register restores
1311 * we are now ready for the big DIVE to SAL Land
1312 */
1313 ssm psr.ic;;
1314 srlz.d;;
1315 br.ret.sptk.many b0;;
1316 END(ia64_jump_to_sal)
1317 #endif /* CONFIG_HOTPLUG_CPU */
1318
1319 #endif /* CONFIG_SMP */
Linux kernel - Deliverables
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