arch/ia64/mm/tlb.c

   1 /*
   2  * TLB support routines.
   3  *
   4  * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
   5  *      David Mosberger-Tang <davidm@hpl.hp.com>
   6  *
   7  * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
   8  *              Modified RID allocation for SMP
   9  *          Goutham Rao <goutham.rao@intel.com>
  10  *              IPI based ptc implementation and A-step IPI implementation.
  11  * Rohit Seth <rohit.seth@intel.com>
  12  * Ken Chen <kenneth.w.chen@intel.com>
  13  */
  14 #include <linux/config.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/sched.h>
  19 #include <linux/smp.h>
  20 #include <linux/mm.h>
  21 #include <linux/bootmem.h>
  22
  23 #include <asm/delay.h>
  24 #include <asm/mmu_context.h>
  25 #include <asm/pgalloc.h>
  26 #include <asm/pal.h>
  27 #include <asm/tlbflush.h>
  28 #include <asm/dma.h>
  29
  30 static struct {
  31         unsigned long mask;     /* mask of supported purge page-sizes */
  32         unsigned long max_bits; /* log2() of largest supported purge page-size */
  33 } purge;
  34
  35 struct ia64_ctx ia64_ctx = {
  36         .lock =         SPIN_LOCK_UNLOCKED,
  37         .next =         1,
  38         .max_ctx =      ~0U
  39 };
  40
  41 DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
  42
  43 /*
  44  * Initializes the ia64_ctx.bitmap array based on max_ctx+1.
  45  * Called after cpu_init() has setup ia64_ctx.max_ctx based on
  46  * maximum RID that is supported by boot CPU.
  47  */
  48 void __init
  49 mmu_context_init (void)
  50 {
  51         ia64_ctx.bitmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
  52         ia64_ctx.flushmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
  53 }
  54
  55 /*
  56  * Acquire the ia64_ctx.lock before calling this function!
  57  */
  58 void
  59 wrap_mmu_context (struct mm_struct *mm)
  60 {
  61         int i;
  62         unsigned long flush_bit;
  63
  64         for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
  65                 flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
  66                 ia64_ctx.bitmap[i] ^= flush_bit;
  67         }
  68
  69         /* use offset at 300 to skip daemons */
  70         ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
  71                                 ia64_ctx.max_ctx, 300);
  72         ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
  73                                 ia64_ctx.max_ctx, ia64_ctx.next);
  74
  75         /* can't call flush_tlb_all() here because of race condition with O(1) scheduler [EF] */
  76         {
  77                 int cpu = get_cpu(); /* prevent preemption/migration */
  78                 for_each_online_cpu(i) {
  79                         if (i != cpu)
  80                                 per_cpu(ia64_need_tlb_flush, i) = 1;
  81                 }
  82                 put_cpu();
  83         }
  84         local_flush_tlb_all();
  85 }
  86
  87 void
  88 ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start, unsigned long end, unsigned long nbits)
  89 {
  90         static DEFINE_SPINLOCK(ptcg_lock);
  91
  92         if (mm != current->active_mm) {
  93                 flush_tlb_all();
  94                 return;
  95         }
  96
  97         /* HW requires global serialization of ptc.ga.  */
  98         spin_lock(&ptcg_lock);
  99         {
 100                 do {
 101                         /*
 102                          * Flush ALAT entries also.
 103                          */
 104                         ia64_ptcga(start, (nbits<<2));
 105                         ia64_srlz_i();
 106                         start += (1UL << nbits);
 107                 } while (start < end);
 108         }
 109         spin_unlock(&ptcg_lock);
 110 }
 111
 112 void
 113 local_flush_tlb_all (void)
 114 {
 115         unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
 116
 117         addr    = local_cpu_data->ptce_base;
 118         count0  = local_cpu_data->ptce_count[0];
 119         count1  = local_cpu_data->ptce_count[1];
 120         stride0 = local_cpu_data->ptce_stride[0];
 121         stride1 = local_cpu_data->ptce_stride[1];
 122
 123         local_irq_save(flags);
 124         for (i = 0; i < count0; ++i) {
 125                 for (j = 0; j < count1; ++j) {
 126                         ia64_ptce(addr);
 127                         addr += stride1;
 128                 }
 129                 addr += stride0;
 130         }
 131         local_irq_restore(flags);
 132         ia64_srlz_i();                  /* srlz.i implies srlz.d */
 133 }
 134
 135 void
 136 flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end)
 137 {
 138         struct mm_struct *mm = vma->vm_mm;
 139         unsigned long size = end - start;
 140         unsigned long nbits;
 141
 142 #ifndef CONFIG_SMP
 143         if (mm != current->active_mm) {
 144                 mm->context = 0;
 145                 return;
 146         }
 147 #endif
 148
 149         nbits = ia64_fls(size + 0xfff);
 150         while (unlikely (((1UL << nbits) & purge.mask) == 0) && (nbits < purge.max_bits))
 151                 ++nbits;
 152         if (nbits > purge.max_bits)
 153                 nbits = purge.max_bits;
 154         start &= ~((1UL << nbits) - 1);
 155
 156 # ifdef CONFIG_SMP
 157         platform_global_tlb_purge(mm, start, end, nbits);
 158 # else
 159         preempt_disable();
 160         do {
 161                 ia64_ptcl(start, (nbits<<2));
 162                 start += (1UL << nbits);
 163         } while (start < end);
 164         preempt_enable();
 165 # endif
 166
 167         ia64_srlz_i();                  /* srlz.i implies srlz.d */
 168 }
 169 EXPORT_SYMBOL(flush_tlb_range);
 170
 171 void __devinit
 172 ia64_tlb_init (void)
 173 {
 174         ia64_ptce_info_t ptce_info;
 175         unsigned long tr_pgbits;
 176         long status;
 177
 178         if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
 179                 printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld;"
 180                        "defaulting to architected purge page-sizes.\n", status);
 181                 purge.mask = 0x115557000UL;
 182         }
 183         purge.max_bits = ia64_fls(purge.mask);
 184
 185         ia64_get_ptce(&ptce_info);
 186         local_cpu_data->ptce_base = ptce_info.base;
 187         local_cpu_data->ptce_count[0] = ptce_info.count[0];
 188         local_cpu_data->ptce_count[1] = ptce_info.count[1];
 189         local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
 190         local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
 191
 192         local_flush_tlb_all();          /* nuke left overs from bootstrapping... */
 193 }