arch/ia64/pci/fixup.c

   1 /*
   2  * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
   3  * Derived from fixup.c of i386 tree.
   4  */
   5
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/vgaarb.h>
   9 #include <linux/screen_info.h>
  10
  11 #include <asm/machvec.h>
  12
  13 /*
  14  * Fixup to mark boot BIOS video selected by BIOS before it changes
  15  *
  16  * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
  17  *
  18  * The standard boot ROM sequence for an x86 machine uses the BIOS
  19  * to select an initial video card for boot display. This boot video
  20  * card will have its BIOS copied to 0xC0000 in system RAM.
  21  * IORESOURCE_ROM_SHADOW is used to associate the boot video
  22  * card with this copy. On laptops this copy has to be used since
  23  * the main ROM may be compressed or combined with another image.
  24  * See pci_map_rom() for use of this flag. Before marking the device
  25  * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set
  26  * by either arch code or vga-arbitration; if so only apply the fixup to this
  27  * already-determined primary video card.
  28  */
  29
  30 static void pci_fixup_video(struct pci_dev *pdev)
  31 {
  32         struct pci_dev *bridge;
  33         struct pci_bus *bus;
  34         u16 config;
  35         struct resource *res;
  36
  37         if ((strcmp(ia64_platform_name, "dig") != 0)
  38             && (strcmp(ia64_platform_name, "hpzx1")  != 0))
  39                 return;
  40         /* Maybe, this machine supports legacy memory map. */
  41
  42         /* Is VGA routed to us? */
  43         bus = pdev->bus;
  44         while (bus) {
  45                 bridge = bus->self;
  46
  47                 /*
  48                  * From information provided by
  49                  * "David Miller" <davem@davemloft.net>
  50                  * The bridge control register is valid for PCI header
  51                  * type BRIDGE, or CARDBUS. Host to PCI controllers use
  52                  * PCI header type NORMAL.
  53                  */
  54                 if (bridge && (pci_is_bridge(bridge))) {
  55                         pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
  56                                                 &config);
  57                         if (!(config & PCI_BRIDGE_CTL_VGA))
  58                                 return;
  59                 }
  60                 bus = bus->parent;
  61         }
  62         if (!vga_default_device() || pdev == vga_default_device()) {
  63                 pci_read_config_word(pdev, PCI_COMMAND, &config);
  64                 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
  65                         res = &pdev->resource[PCI_ROM_RESOURCE];
  66
  67                         pci_disable_rom(pdev);
  68                         if (res->parent)
  69                                 release_resource(res);
  70
  71                         res->start = 0xC0000;
  72                         res->end = res->start + 0x20000 - 1;
  73                         res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
  74                                      IORESOURCE_PCI_FIXED;
  75                         dev_info(&pdev->dev, "Video device with shadowed ROM at %pR\n",
  76                                  res);
  77                 }
  78         }
  79 }
  80 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
  81                                 PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);