arch/ia64/pci/pci.c

   1 /*
   2  * pci.c - Low-Level PCI Access in IA-64
   3  *
   4  * Derived from bios32.c of i386 tree.
   5  *
   6  * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *      Bjorn Helgaas <bjorn.helgaas@hp.com>
   9  * Copyright (C) 2004 Silicon Graphics, Inc.
  10  *
  11  * Note: Above list of copyright holders is incomplete...
  12  */
  13 #include <linux/config.h>
  14
  15 #include <linux/acpi.h>
  16 #include <linux/types.h>
  17 #include <linux/kernel.h>
  18 #include <linux/pci.h>
  19 #include <linux/init.h>
  20 #include <linux/ioport.h>
  21 #include <linux/slab.h>
  22 #include <linux/smp_lock.h>
  23 #include <linux/spinlock.h>
  24
  25 #include <asm/machvec.h>
  26 #include <asm/page.h>
  27 #include <asm/segment.h>
  28 #include <asm/system.h>
  29 #include <asm/io.h>
  30 #include <asm/sal.h>
  31 #include <asm/smp.h>
  32 #include <asm/irq.h>
  33 #include <asm/hw_irq.h>
  34
  35
  36 /*
  37  * Low-level SAL-based PCI configuration access functions. Note that SAL
  38  * calls are already serialized (via sal_lock), so we don't need another
  39  * synchronization mechanism here.
  40  */
  41
  42 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg)           \
  43         (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
  44
  45 /* SAL 3.2 adds support for extended config space. */
  46
  47 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg)       \
  48         (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
  49
  50 static int
  51 pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
  52               int reg, int len, u32 *value)
  53 {
  54         u64 addr, data = 0;
  55         int mode, result;
  56
  57         if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  58                 return -EINVAL;
  59
  60         if ((seg | reg) <= 255) {
  61                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  62                 mode = 0;
  63         } else {
  64                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  65                 mode = 1;
  66         }
  67         result = ia64_sal_pci_config_read(addr, mode, len, &data);
  68         if (result != 0)
  69                 return -EINVAL;
  70
  71         *value = (u32) data;
  72         return 0;
  73 }
  74
  75 static int
  76 pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
  77                int reg, int len, u32 value)
  78 {
  79         u64 addr;
  80         int mode, result;
  81
  82         if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  83                 return -EINVAL;
  84
  85         if ((seg | reg) <= 255) {
  86                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  87                 mode = 0;
  88         } else {
  89                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  90                 mode = 1;
  91         }
  92         result = ia64_sal_pci_config_write(addr, mode, len, value);
  93         if (result != 0)
  94                 return -EINVAL;
  95         return 0;
  96 }
  97
  98 static struct pci_raw_ops pci_sal_ops = {
  99         .read =         pci_sal_read,
 100         .write =        pci_sal_write
 101 };
 102
 103 struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
 104
 105 static int
 106 pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
 107 {
 108         return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
 109                                  devfn, where, size, value);
 110 }
 111
 112 static int
 113 pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
 114 {
 115         return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
 116                                   devfn, where, size, value);
 117 }
 118
 119 struct pci_ops pci_root_ops = {
 120         .read = pci_read,
 121         .write = pci_write,
 122 };
 123
 124 #ifdef CONFIG_NUMA
 125 extern acpi_status acpi_map_iosapic(acpi_handle, u32, void *, void **);
 126 static void acpi_map_iosapics(void)
 127 {
 128         acpi_get_devices(NULL, acpi_map_iosapic, NULL, NULL);
 129 }
 130 #else
 131 static void acpi_map_iosapics(void)
 132 {
 133         return;
 134 }
 135 #endif /* CONFIG_NUMA */
 136
 137 static int __init
 138 pci_acpi_init (void)
 139 {
 140         acpi_map_iosapics();
 141
 142         return 0;
 143 }
 144
 145 subsys_initcall(pci_acpi_init);
 146
 147 /* Called by ACPI when it finds a new root bus.  */
 148
 149 static struct pci_controller * __devinit
 150 alloc_pci_controller (int seg)
 151 {
 152         struct pci_controller *controller;
 153
 154         controller = kmalloc(sizeof(*controller), GFP_KERNEL);
 155         if (!controller)
 156                 return NULL;
 157
 158         memset(controller, 0, sizeof(*controller));
 159         controller->segment = seg;
 160         controller->node = -1;
 161         return controller;
 162 }
 163
 164 static u64 __devinit
 165 add_io_space (struct acpi_resource_address64 *addr)
 166 {
 167         u64 offset;
 168         int sparse = 0;
 169         int i;
 170
 171         if (addr->address_translation_offset == 0)
 172                 return IO_SPACE_BASE(0);        /* part of legacy IO space */
 173
 174         if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION)
 175                 sparse = 1;
 176
 177         offset = (u64) ioremap(addr->address_translation_offset, 0);
 178         for (i = 0; i < num_io_spaces; i++)
 179                 if (io_space[i].mmio_base == offset &&
 180                     io_space[i].sparse == sparse)
 181                         return IO_SPACE_BASE(i);
 182
 183         if (num_io_spaces == MAX_IO_SPACES) {
 184                 printk("Too many IO port spaces\n");
 185                 return ~0;
 186         }
 187
 188         i = num_io_spaces++;
 189         io_space[i].mmio_base = offset;
 190         io_space[i].sparse = sparse;
 191
 192         return IO_SPACE_BASE(i);
 193 }
 194
 195 static acpi_status __devinit
 196 count_window (struct acpi_resource *resource, void *data)
 197 {
 198         unsigned int *windows = (unsigned int *) data;
 199         struct acpi_resource_address64 addr;
 200         acpi_status status;
 201
 202         status = acpi_resource_to_address64(resource, &addr);
 203         if (ACPI_SUCCESS(status))
 204                 if (addr.resource_type == ACPI_MEMORY_RANGE ||
 205                     addr.resource_type == ACPI_IO_RANGE)
 206                         (*windows)++;
 207
 208         return AE_OK;
 209 }
 210
 211 struct pci_root_info {
 212         struct pci_controller *controller;
 213         char *name;
 214 };
 215
 216 static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
 217 {
 218         struct pci_root_info *info = data;
 219         struct pci_window *window;
 220         struct acpi_resource_address64 addr;
 221         acpi_status status;
 222         unsigned long flags, offset = 0;
 223         struct resource *root;
 224
 225         status = acpi_resource_to_address64(res, &addr);
 226         if (!ACPI_SUCCESS(status))
 227                 return AE_OK;
 228
 229         if (!addr.address_length)
 230                 return AE_OK;
 231
 232         if (addr.resource_type == ACPI_MEMORY_RANGE) {
 233                 flags = IORESOURCE_MEM;
 234                 root = &iomem_resource;
 235                 offset = addr.address_translation_offset;
 236         } else if (addr.resource_type == ACPI_IO_RANGE) {
 237                 flags = IORESOURCE_IO;
 238                 root = &ioport_resource;
 239                 offset = add_io_space(&addr);
 240                 if (offset == ~0)
 241                         return AE_OK;
 242         } else
 243                 return AE_OK;
 244
 245         window = &info->controller->window[info->controller->windows++];
 246         window->resource.name = info->name;
 247         window->resource.flags = flags;
 248         window->resource.start = addr.min_address_range + offset;
 249         window->resource.end = addr.max_address_range + offset;
 250         window->resource.child = NULL;
 251         window->offset = offset;
 252
 253         if (insert_resource(root, &window->resource)) {
 254                 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
 255                         window->resource.start, window->resource.end,
 256                         root->name, info->name);
 257         }
 258
 259         return AE_OK;
 260 }
 261
 262 static void __devinit
 263 pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
 264 {
 265         int i, j;
 266
 267         j = 0;
 268         for (i = 0; i < ctrl->windows; i++) {
 269                 struct resource *res = &ctrl->window[i].resource;
 270                 /* HP's firmware has a hack to work around a Windows bug.
 271                  * Ignore these tiny memory ranges */
 272                 if ((res->flags & IORESOURCE_MEM) &&
 273                     (res->end - res->start < 16))
 274                         continue;
 275                 if (j >= PCI_BUS_NUM_RESOURCES) {
 276                         printk("Ignoring range [%lx-%lx] (%lx)\n", res->start,
 277                                         res->end, res->flags);
 278                         continue;
 279                 }
 280                 bus->resource[j++] = res;
 281         }
 282 }
 283
 284 struct pci_bus * __devinit
 285 pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
 286 {
 287         struct pci_root_info info;
 288         struct pci_controller *controller;
 289         unsigned int windows = 0;
 290         struct pci_bus *pbus;
 291         char *name;
 292         int pxm;
 293
 294         controller = alloc_pci_controller(domain);
 295         if (!controller)
 296                 goto out1;
 297
 298         controller->acpi_handle = device->handle;
 299
 300         pxm = acpi_get_pxm(controller->acpi_handle);
 301 #ifdef CONFIG_NUMA
 302         if (pxm >= 0)
 303                 controller->node = pxm_to_nid_map[pxm];
 304 #endif
 305
 306         acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
 307                         &windows);
 308         controller->window = kmalloc_node(sizeof(*controller->window) * windows,
 309                         GFP_KERNEL, controller->node);
 310         if (!controller->window)
 311                 goto out2;
 312
 313         name = kmalloc(16, GFP_KERNEL);
 314         if (!name)
 315                 goto out3;
 316
 317         sprintf(name, "PCI Bus %04x:%02x", domain, bus);
 318         info.controller = controller;
 319         info.name = name;
 320         acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window,
 321                         &info);
 322
 323         pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
 324         if (pbus)
 325                 pcibios_setup_root_windows(pbus, controller);
 326
 327         return pbus;
 328
 329 out3:
 330         kfree(controller->window);
 331 out2:
 332         kfree(controller);
 333 out1:
 334         return NULL;
 335 }
 336
 337 void pcibios_resource_to_bus(struct pci_dev *dev,
 338                 struct pci_bus_region *region, struct resource *res)
 339 {
 340         struct pci_controller *controller = PCI_CONTROLLER(dev);
 341         unsigned long offset = 0;
 342         int i;
 343
 344         for (i = 0; i < controller->windows; i++) {
 345                 struct pci_window *window = &controller->window[i];
 346                 if (!(window->resource.flags & res->flags))
 347                         continue;
 348                 if (window->resource.start > res->start)
 349                         continue;
 350                 if (window->resource.end < res->end)
 351                         continue;
 352                 offset = window->offset;
 353                 break;
 354         }
 355
 356         region->start = res->start - offset;
 357         region->end = res->end - offset;
 358 }
 359 EXPORT_SYMBOL(pcibios_resource_to_bus);
 360
 361 void pcibios_bus_to_resource(struct pci_dev *dev,
 362                 struct resource *res, struct pci_bus_region *region)
 363 {
 364         struct pci_controller *controller = PCI_CONTROLLER(dev);
 365         unsigned long offset = 0;
 366         int i;
 367
 368         for (i = 0; i < controller->windows; i++) {
 369                 struct pci_window *window = &controller->window[i];
 370                 if (!(window->resource.flags & res->flags))
 371                         continue;
 372                 if (window->resource.start - window->offset > region->start)
 373                         continue;
 374                 if (window->resource.end - window->offset < region->end)
 375                         continue;
 376                 offset = window->offset;
 377                 break;
 378         }
 379
 380         res->start = region->start + offset;
 381         res->end = region->end + offset;
 382 }
 383
 384 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 385 {
 386         unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
 387         struct resource *devr = &dev->resource[idx];
 388
 389         if (!dev->bus)
 390                 return 0;
 391         for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) {
 392                 struct resource *busr = dev->bus->resource[i];
 393
 394                 if (!busr || ((busr->flags ^ devr->flags) & type_mask))
 395                         continue;
 396                 if ((devr->start) && (devr->start >= busr->start) &&
 397                                 (devr->end <= busr->end))
 398                         return 1;
 399         }
 400         return 0;
 401 }
 402
 403 static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
 404 {
 405         struct pci_bus_region region;
 406         int i;
 407         int limit = (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) ? \
 408                 PCI_BRIDGE_RESOURCES : PCI_NUM_RESOURCES;
 409
 410         for (i = 0; i < limit; i++) {
 411                 if (!dev->resource[i].flags)
 412                         continue;
 413                 region.start = dev->resource[i].start;
 414                 region.end = dev->resource[i].end;
 415                 pcibios_bus_to_resource(dev, &dev->resource[i], &region);
 416                 if ((is_valid_resource(dev, i)))
 417                         pci_claim_resource(dev, i);
 418         }
 419 }
 420
 421 /*
 422  *  Called after each bus is probed, but before its children are examined.
 423  */
 424 void __devinit
 425 pcibios_fixup_bus (struct pci_bus *b)
 426 {
 427         struct pci_dev *dev;
 428
 429         if (b->self) {
 430                 pci_read_bridge_bases(b);
 431                 pcibios_fixup_device_resources(b->self);
 432         }
 433         list_for_each_entry(dev, &b->devices, bus_list)
 434                 pcibios_fixup_device_resources(dev);
 435
 436         return;
 437 }
 438
 439 void __devinit
 440 pcibios_update_irq (struct pci_dev *dev, int irq)
 441 {
 442         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 443
 444         /* ??? FIXME -- record old value for shutdown.  */
 445 }
 446
 447 static inline int
 448 pcibios_enable_resources (struct pci_dev *dev, int mask)
 449 {
 450         u16 cmd, old_cmd;
 451         int idx;
 452         struct resource *r;
 453         unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
 454
 455         if (!dev)
 456                 return -EINVAL;
 457
 458         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 459         old_cmd = cmd;
 460         for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
 461                 /* Only set up the desired resources.  */
 462                 if (!(mask & (1 << idx)))
 463                         continue;
 464
 465                 r = &dev->resource[idx];
 466                 if (!(r->flags & type_mask))
 467                         continue;
 468                 if ((idx == PCI_ROM_RESOURCE) &&
 469                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 470                         continue;
 471                 if (!r->start && r->end) {
 472                         printk(KERN_ERR
 473                                "PCI: Device %s not available because of resource collisions\n",
 474                                pci_name(dev));
 475                         return -EINVAL;
 476                 }
 477                 if (r->flags & IORESOURCE_IO)
 478                         cmd |= PCI_COMMAND_IO;
 479                 if (r->flags & IORESOURCE_MEM)
 480                         cmd |= PCI_COMMAND_MEMORY;
 481         }
 482         if (cmd != old_cmd) {
 483                 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
 484                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 485         }
 486         return 0;
 487 }
 488
 489 int
 490 pcibios_enable_device (struct pci_dev *dev, int mask)
 491 {
 492         int ret;
 493
 494         ret = pcibios_enable_resources(dev, mask);
 495         if (ret < 0)
 496                 return ret;
 497
 498         return acpi_pci_irq_enable(dev);
 499 }
 500
 501 #ifdef CONFIG_ACPI_DEALLOCATE_IRQ
 502 void
 503 pcibios_disable_device (struct pci_dev *dev)
 504 {
 505         acpi_pci_irq_disable(dev);
 506 }
 507 #endif /* CONFIG_ACPI_DEALLOCATE_IRQ */
 508
 509 void
 510 pcibios_align_resource (void *data, struct resource *res,
 511                         unsigned long size, unsigned long align)
 512 {
 513 }
 514
 515 /*
 516  * PCI BIOS setup, always defaults to SAL interface
 517  */
 518 char * __init
 519 pcibios_setup (char *str)
 520 {
 521         return NULL;
 522 }
 523
 524 int
 525 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
 526                      enum pci_mmap_state mmap_state, int write_combine)
 527 {
 528         /*
 529          * I/O space cannot be accessed via normal processor loads and
 530          * stores on this platform.
 531          */
 532         if (mmap_state == pci_mmap_io)
 533                 /*
 534                  * XXX we could relax this for I/O spaces for which ACPI
 535                  * indicates that the space is 1-to-1 mapped.  But at the
 536                  * moment, we don't support multiple PCI address spaces and
 537                  * the legacy I/O space is not 1-to-1 mapped, so this is moot.
 538                  */
 539                 return -EINVAL;
 540
 541         /*
 542          * Leave vm_pgoff as-is, the PCI space address is the physical
 543          * address on this platform.
 544          */
 545         vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO);
 546
 547         if (write_combine && efi_range_is_wc(vma->vm_start,
 548                                              vma->vm_end - vma->vm_start))
 549                 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 550         else
 551                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 552
 553         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 554                              vma->vm_end - vma->vm_start, vma->vm_page_prot))
 555                 return -EAGAIN;
 556
 557         return 0;
 558 }
 559
 560 /**
 561  * ia64_pci_get_legacy_mem - generic legacy mem routine
 562  * @bus: bus to get legacy memory base address for
 563  *
 564  * Find the base of legacy memory for @bus.  This is typically the first
 565  * megabyte of bus address space for @bus or is simply 0 on platforms whose
 566  * chipsets support legacy I/O and memory routing.  Returns the base address
 567  * or an error pointer if an error occurred.
 568  *
 569  * This is the ia64 generic version of this routine.  Other platforms
 570  * are free to override it with a machine vector.
 571  */
 572 char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
 573 {
 574         return (char *)__IA64_UNCACHED_OFFSET;
 575 }
 576
 577 /**
 578  * pci_mmap_legacy_page_range - map legacy memory space to userland
 579  * @bus: bus whose legacy space we're mapping
 580  * @vma: vma passed in by mmap
 581  *
 582  * Map legacy memory space for this device back to userspace using a machine
 583  * vector to get the base address.
 584  */
 585 int
 586 pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma)
 587 {
 588         char *addr;
 589
 590         addr = pci_get_legacy_mem(bus);
 591         if (IS_ERR(addr))
 592                 return PTR_ERR(addr);
 593
 594         vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
 595         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 596         vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO);
 597
 598         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 599                             vma->vm_end - vma->vm_start, vma->vm_page_prot))
 600                 return -EAGAIN;
 601
 602         return 0;
 603 }
 604
 605 /**
 606  * ia64_pci_legacy_read - read from legacy I/O space
 607  * @bus: bus to read
 608  * @port: legacy port value
 609  * @val: caller allocated storage for returned value
 610  * @size: number of bytes to read
 611  *
 612  * Simply reads @size bytes from @port and puts the result in @val.
 613  *
 614  * Again, this (and the write routine) are generic versions that can be
 615  * overridden by the platform.  This is necessary on platforms that don't
 616  * support legacy I/O routing or that hard fail on legacy I/O timeouts.
 617  */
 618 int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 619 {
 620         int ret = size;
 621
 622         switch (size) {
 623         case 1:
 624                 *val = inb(port);
 625                 break;
 626         case 2:
 627                 *val = inw(port);
 628                 break;
 629         case 4:
 630                 *val = inl(port);
 631                 break;
 632         default:
 633                 ret = -EINVAL;
 634                 break;
 635         }
 636
 637         return ret;
 638 }
 639
 640 /**
 641  * ia64_pci_legacy_write - perform a legacy I/O write
 642  * @bus: bus pointer
 643  * @port: port to write
 644  * @val: value to write
 645  * @size: number of bytes to write from @val
 646  *
 647  * Simply writes @size bytes of @val to @port.
 648  */
 649 int ia64_pci_legacy_write(struct pci_dev *bus, u16 port, u32 val, u8 size)
 650 {
 651         int ret = 0;
 652
 653         switch (size) {
 654         case 1:
 655                 outb(val, port);
 656                 break;
 657         case 2:
 658                 outw(val, port);
 659                 break;
 660         case 4:
 661                 outl(val, port);
 662                 break;
 663         default:
 664                 ret = -EINVAL;
 665                 break;
 666         }
 667
 668         return ret;
 669 }
 670
 671 /**
 672  * pci_cacheline_size - determine cacheline size for PCI devices
 673  * @dev: void
 674  *
 675  * We want to use the line-size of the outer-most cache.  We assume
 676  * that this line-size is the same for all CPUs.
 677  *
 678  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
 679  *
 680  * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
 681  */
 682 static unsigned long
 683 pci_cacheline_size (void)
 684 {
 685         u64 levels, unique_caches;
 686         s64 status;
 687         pal_cache_config_info_t cci;
 688         static u8 cacheline_size;
 689
 690         if (cacheline_size)
 691                 return cacheline_size;
 692
 693         status = ia64_pal_cache_summary(&levels, &unique_caches);
 694         if (status != 0) {
 695                 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
 696                        __FUNCTION__, status);
 697                 return SMP_CACHE_BYTES;
 698         }
 699
 700         status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
 701                                             &cci);
 702         if (status != 0) {
 703                 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
 704                        __FUNCTION__, status);
 705                 return SMP_CACHE_BYTES;
 706         }
 707         cacheline_size = 1 << cci.pcci_line_size;
 708         return cacheline_size;
 709 }
 710
 711 /**
 712  * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
 713  * @dev: the PCI device for which MWI is enabled
 714  *
 715  * For ia64, we can get the cacheline sizes from PAL.
 716  *
 717  * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
 718  */
 719 int
 720 pcibios_prep_mwi (struct pci_dev *dev)
 721 {
 722         unsigned long desired_linesize, current_linesize;
 723         int rc = 0;
 724         u8 pci_linesize;
 725
 726         desired_linesize = pci_cacheline_size();
 727
 728         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
 729         current_linesize = 4 * pci_linesize;
 730         if (desired_linesize != current_linesize) {
 731                 printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
 732                        pci_name(dev), current_linesize);
 733                 if (current_linesize > desired_linesize) {
 734                         printk(" expected %lu bytes instead\n", desired_linesize);
 735                         rc = -EINVAL;
 736                 } else {
 737                         printk(" correcting to %lu\n", desired_linesize);
 738                         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
 739                 }
 740         }
 741         return rc;
 742 }
 743
 744 int pci_vector_resources(int last, int nr_released)
 745 {
 746         int count = nr_released;
 747
 748         count += (IA64_LAST_DEVICE_VECTOR - last);
 749
 750         return count;
 751 }