2 * pci.c - Low-Level PCI Access in IA-64
4 * Derived from bios32.c of i386 tree.
6 * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn.helgaas@hp.com>
9 * Copyright (C) 2004 Silicon Graphics, Inc.
11 * Note: Above list of copyright holders is incomplete...
13 #include <linux/config.h>
15 #include <linux/acpi.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/ioport.h>
21 #include <linux/slab.h>
22 #include <linux/smp_lock.h>
23 #include <linux/spinlock.h>
25 #include <asm/machvec.h>
27 #include <asm/system.h>
32 #include <asm/hw_irq.h>
36 * Low-level SAL-based PCI configuration access functions. Note that SAL
37 * calls are already serialized (via sal_lock), so we don't need another
38 * synchronization mechanism here.
41 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
42 (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
44 /* SAL 3.2 adds support for extended config space. */
46 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
47 (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
50 pci_sal_read (unsigned int seg
, unsigned int bus
, unsigned int devfn
,
51 int reg
, int len
, u32
*value
)
56 if (!value
|| (seg
> 65535) || (bus
> 255) || (devfn
> 255) || (reg
> 4095))
59 if ((seg
| reg
) <= 255) {
60 addr
= PCI_SAL_ADDRESS(seg
, bus
, devfn
, reg
);
63 addr
= PCI_SAL_EXT_ADDRESS(seg
, bus
, devfn
, reg
);
66 result
= ia64_sal_pci_config_read(addr
, mode
, len
, &data
);
75 pci_sal_write (unsigned int seg
, unsigned int bus
, unsigned int devfn
,
76 int reg
, int len
, u32 value
)
81 if ((seg
> 65535) || (bus
> 255) || (devfn
> 255) || (reg
> 4095))
84 if ((seg
| reg
) <= 255) {
85 addr
= PCI_SAL_ADDRESS(seg
, bus
, devfn
, reg
);
88 addr
= PCI_SAL_EXT_ADDRESS(seg
, bus
, devfn
, reg
);
91 result
= ia64_sal_pci_config_write(addr
, mode
, len
, value
);
97 static struct pci_raw_ops pci_sal_ops
= {
99 .write
= pci_sal_write
102 struct pci_raw_ops
*raw_pci_ops
= &pci_sal_ops
;
105 pci_read (struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*value
)
107 return raw_pci_ops
->read(pci_domain_nr(bus
), bus
->number
,
108 devfn
, where
, size
, value
);
112 pci_write (struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 value
)
114 return raw_pci_ops
->write(pci_domain_nr(bus
), bus
->number
,
115 devfn
, where
, size
, value
);
118 struct pci_ops pci_root_ops
= {
123 /* Called by ACPI when it finds a new root bus. */
125 static struct pci_controller
* __devinit
126 alloc_pci_controller (int seg
)
128 struct pci_controller
*controller
;
130 controller
= kmalloc(sizeof(*controller
), GFP_KERNEL
);
134 memset(controller
, 0, sizeof(*controller
));
135 controller
->segment
= seg
;
136 controller
->node
= -1;
141 add_io_space (struct acpi_resource_address64
*addr
)
147 if (addr
->address_translation_offset
== 0)
148 return IO_SPACE_BASE(0); /* part of legacy IO space */
150 if (addr
->attribute
.io
.translation_attribute
== ACPI_SPARSE_TRANSLATION
)
153 offset
= (u64
) ioremap(addr
->address_translation_offset
, 0);
154 for (i
= 0; i
< num_io_spaces
; i
++)
155 if (io_space
[i
].mmio_base
== offset
&&
156 io_space
[i
].sparse
== sparse
)
157 return IO_SPACE_BASE(i
);
159 if (num_io_spaces
== MAX_IO_SPACES
) {
160 printk("Too many IO port spaces\n");
165 io_space
[i
].mmio_base
= offset
;
166 io_space
[i
].sparse
= sparse
;
168 return IO_SPACE_BASE(i
);
171 static acpi_status __devinit
resource_to_window(struct acpi_resource
*resource
,
172 struct acpi_resource_address64
*addr
)
177 * We're only interested in _CRS descriptors that are
178 * - address space descriptors for memory or I/O space
180 * - producers, i.e., the address space is routed downstream,
181 * not consumed by the bridge itself
183 status
= acpi_resource_to_address64(resource
, addr
);
184 if (ACPI_SUCCESS(status
) &&
185 (addr
->resource_type
== ACPI_MEMORY_RANGE
||
186 addr
->resource_type
== ACPI_IO_RANGE
) &&
187 addr
->address_length
&&
188 addr
->producer_consumer
== ACPI_PRODUCER
)
194 static acpi_status __devinit
195 count_window (struct acpi_resource
*resource
, void *data
)
197 unsigned int *windows
= (unsigned int *) data
;
198 struct acpi_resource_address64 addr
;
201 status
= resource_to_window(resource
, &addr
);
202 if (ACPI_SUCCESS(status
))
208 struct pci_root_info
{
209 struct pci_controller
*controller
;
213 static __devinit acpi_status
add_window(struct acpi_resource
*res
, void *data
)
215 struct pci_root_info
*info
= data
;
216 struct pci_window
*window
;
217 struct acpi_resource_address64 addr
;
219 unsigned long flags
, offset
= 0;
220 struct resource
*root
;
222 /* Return AE_OK for non-window resources to keep scanning for more */
223 status
= resource_to_window(res
, &addr
);
224 if (!ACPI_SUCCESS(status
))
227 if (addr
.resource_type
== ACPI_MEMORY_RANGE
) {
228 flags
= IORESOURCE_MEM
;
229 root
= &iomem_resource
;
230 offset
= addr
.address_translation_offset
;
231 } else if (addr
.resource_type
== ACPI_IO_RANGE
) {
232 flags
= IORESOURCE_IO
;
233 root
= &ioport_resource
;
234 offset
= add_io_space(&addr
);
240 window
= &info
->controller
->window
[info
->controller
->windows
++];
241 window
->resource
.name
= info
->name
;
242 window
->resource
.flags
= flags
;
243 window
->resource
.start
= addr
.min_address_range
+ offset
;
244 window
->resource
.end
= addr
.max_address_range
+ offset
;
245 window
->resource
.child
= NULL
;
246 window
->offset
= offset
;
248 if (insert_resource(root
, &window
->resource
)) {
249 printk(KERN_ERR
"alloc 0x%lx-0x%lx from %s for %s failed\n",
250 window
->resource
.start
, window
->resource
.end
,
251 root
->name
, info
->name
);
257 static void __devinit
258 pcibios_setup_root_windows(struct pci_bus
*bus
, struct pci_controller
*ctrl
)
263 for (i
= 0; i
< ctrl
->windows
; i
++) {
264 struct resource
*res
= &ctrl
->window
[i
].resource
;
265 /* HP's firmware has a hack to work around a Windows bug.
266 * Ignore these tiny memory ranges */
267 if ((res
->flags
& IORESOURCE_MEM
) &&
268 (res
->end
- res
->start
< 16))
270 if (j
>= PCI_BUS_NUM_RESOURCES
) {
271 printk("Ignoring range [%lx-%lx] (%lx)\n", res
->start
,
272 res
->end
, res
->flags
);
275 bus
->resource
[j
++] = res
;
279 struct pci_bus
* __devinit
280 pci_acpi_scan_root(struct acpi_device
*device
, int domain
, int bus
)
282 struct pci_root_info info
;
283 struct pci_controller
*controller
;
284 unsigned int windows
= 0;
285 struct pci_bus
*pbus
;
289 controller
= alloc_pci_controller(domain
);
293 controller
->acpi_handle
= device
->handle
;
295 pxm
= acpi_get_pxm(controller
->acpi_handle
);
298 controller
->node
= pxm_to_nid_map
[pxm
];
301 acpi_walk_resources(device
->handle
, METHOD_NAME__CRS
, count_window
,
303 controller
->window
= kmalloc_node(sizeof(*controller
->window
) * windows
,
304 GFP_KERNEL
, controller
->node
);
305 if (!controller
->window
)
308 name
= kmalloc(16, GFP_KERNEL
);
312 sprintf(name
, "PCI Bus %04x:%02x", domain
, bus
);
313 info
.controller
= controller
;
315 acpi_walk_resources(device
->handle
, METHOD_NAME__CRS
, add_window
,
318 pbus
= pci_scan_bus_parented(NULL
, bus
, &pci_root_ops
, controller
);
320 pcibios_setup_root_windows(pbus
, controller
);
325 kfree(controller
->window
);
332 void pcibios_resource_to_bus(struct pci_dev
*dev
,
333 struct pci_bus_region
*region
, struct resource
*res
)
335 struct pci_controller
*controller
= PCI_CONTROLLER(dev
);
336 unsigned long offset
= 0;
339 for (i
= 0; i
< controller
->windows
; i
++) {
340 struct pci_window
*window
= &controller
->window
[i
];
341 if (!(window
->resource
.flags
& res
->flags
))
343 if (window
->resource
.start
> res
->start
)
345 if (window
->resource
.end
< res
->end
)
347 offset
= window
->offset
;
351 region
->start
= res
->start
- offset
;
352 region
->end
= res
->end
- offset
;
354 EXPORT_SYMBOL(pcibios_resource_to_bus
);
356 void pcibios_bus_to_resource(struct pci_dev
*dev
,
357 struct resource
*res
, struct pci_bus_region
*region
)
359 struct pci_controller
*controller
= PCI_CONTROLLER(dev
);
360 unsigned long offset
= 0;
363 for (i
= 0; i
< controller
->windows
; i
++) {
364 struct pci_window
*window
= &controller
->window
[i
];
365 if (!(window
->resource
.flags
& res
->flags
))
367 if (window
->resource
.start
- window
->offset
> region
->start
)
369 if (window
->resource
.end
- window
->offset
< region
->end
)
371 offset
= window
->offset
;
375 res
->start
= region
->start
+ offset
;
376 res
->end
= region
->end
+ offset
;
378 EXPORT_SYMBOL(pcibios_bus_to_resource
);
380 static int __devinit
is_valid_resource(struct pci_dev
*dev
, int idx
)
382 unsigned int i
, type_mask
= IORESOURCE_IO
| IORESOURCE_MEM
;
383 struct resource
*devr
= &dev
->resource
[idx
];
387 for (i
=0; i
<PCI_BUS_NUM_RESOURCES
; i
++) {
388 struct resource
*busr
= dev
->bus
->resource
[i
];
390 if (!busr
|| ((busr
->flags
^ devr
->flags
) & type_mask
))
392 if ((devr
->start
) && (devr
->start
>= busr
->start
) &&
393 (devr
->end
<= busr
->end
))
399 static void __devinit
pcibios_fixup_device_resources(struct pci_dev
*dev
)
401 struct pci_bus_region region
;
403 int limit
= (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) ? \
404 PCI_BRIDGE_RESOURCES
: PCI_NUM_RESOURCES
;
406 for (i
= 0; i
< limit
; i
++) {
407 if (!dev
->resource
[i
].flags
)
409 region
.start
= dev
->resource
[i
].start
;
410 region
.end
= dev
->resource
[i
].end
;
411 pcibios_bus_to_resource(dev
, &dev
->resource
[i
], ®ion
);
412 if ((is_valid_resource(dev
, i
)))
413 pci_claim_resource(dev
, i
);
418 * Called after each bus is probed, but before its children are examined.
421 pcibios_fixup_bus (struct pci_bus
*b
)
426 pci_read_bridge_bases(b
);
427 pcibios_fixup_device_resources(b
->self
);
429 list_for_each_entry(dev
, &b
->devices
, bus_list
)
430 pcibios_fixup_device_resources(dev
);
436 pcibios_update_irq (struct pci_dev
*dev
, int irq
)
438 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
440 /* ??? FIXME -- record old value for shutdown. */
444 pcibios_enable_resources (struct pci_dev
*dev
, int mask
)
449 unsigned long type_mask
= IORESOURCE_IO
| IORESOURCE_MEM
;
454 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
456 for (idx
=0; idx
<PCI_NUM_RESOURCES
; idx
++) {
457 /* Only set up the desired resources. */
458 if (!(mask
& (1 << idx
)))
461 r
= &dev
->resource
[idx
];
462 if (!(r
->flags
& type_mask
))
464 if ((idx
== PCI_ROM_RESOURCE
) &&
465 (!(r
->flags
& IORESOURCE_ROM_ENABLE
)))
467 if (!r
->start
&& r
->end
) {
469 "PCI: Device %s not available because of resource collisions\n",
473 if (r
->flags
& IORESOURCE_IO
)
474 cmd
|= PCI_COMMAND_IO
;
475 if (r
->flags
& IORESOURCE_MEM
)
476 cmd
|= PCI_COMMAND_MEMORY
;
478 if (cmd
!= old_cmd
) {
479 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev
), old_cmd
, cmd
);
480 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
486 pcibios_enable_device (struct pci_dev
*dev
, int mask
)
490 ret
= pcibios_enable_resources(dev
, mask
);
494 return acpi_pci_irq_enable(dev
);
498 pcibios_disable_device (struct pci_dev
*dev
)
500 acpi_pci_irq_disable(dev
);
504 pcibios_align_resource (void *data
, struct resource
*res
,
505 unsigned long size
, unsigned long align
)
510 * PCI BIOS setup, always defaults to SAL interface
513 pcibios_setup (char *str
)
519 pci_mmap_page_range (struct pci_dev
*dev
, struct vm_area_struct
*vma
,
520 enum pci_mmap_state mmap_state
, int write_combine
)
523 * I/O space cannot be accessed via normal processor loads and
524 * stores on this platform.
526 if (mmap_state
== pci_mmap_io
)
528 * XXX we could relax this for I/O spaces for which ACPI
529 * indicates that the space is 1-to-1 mapped. But at the
530 * moment, we don't support multiple PCI address spaces and
531 * the legacy I/O space is not 1-to-1 mapped, so this is moot.
536 * Leave vm_pgoff as-is, the PCI space address is the physical
537 * address on this platform.
539 vma
->vm_flags
|= (VM_SHM
| VM_RESERVED
| VM_IO
);
541 if (write_combine
&& efi_range_is_wc(vma
->vm_start
,
542 vma
->vm_end
- vma
->vm_start
))
543 vma
->vm_page_prot
= pgprot_writecombine(vma
->vm_page_prot
);
545 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
547 if (remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
548 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
))
555 * ia64_pci_get_legacy_mem - generic legacy mem routine
556 * @bus: bus to get legacy memory base address for
558 * Find the base of legacy memory for @bus. This is typically the first
559 * megabyte of bus address space for @bus or is simply 0 on platforms whose
560 * chipsets support legacy I/O and memory routing. Returns the base address
561 * or an error pointer if an error occurred.
563 * This is the ia64 generic version of this routine. Other platforms
564 * are free to override it with a machine vector.
566 char *ia64_pci_get_legacy_mem(struct pci_bus
*bus
)
568 return (char *)__IA64_UNCACHED_OFFSET
;
572 * pci_mmap_legacy_page_range - map legacy memory space to userland
573 * @bus: bus whose legacy space we're mapping
574 * @vma: vma passed in by mmap
576 * Map legacy memory space for this device back to userspace using a machine
577 * vector to get the base address.
580 pci_mmap_legacy_page_range(struct pci_bus
*bus
, struct vm_area_struct
*vma
)
584 addr
= pci_get_legacy_mem(bus
);
586 return PTR_ERR(addr
);
588 vma
->vm_pgoff
+= (unsigned long)addr
>> PAGE_SHIFT
;
589 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
590 vma
->vm_flags
|= (VM_SHM
| VM_RESERVED
| VM_IO
);
592 if (remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
593 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
))
600 * ia64_pci_legacy_read - read from legacy I/O space
602 * @port: legacy port value
603 * @val: caller allocated storage for returned value
604 * @size: number of bytes to read
606 * Simply reads @size bytes from @port and puts the result in @val.
608 * Again, this (and the write routine) are generic versions that can be
609 * overridden by the platform. This is necessary on platforms that don't
610 * support legacy I/O routing or that hard fail on legacy I/O timeouts.
612 int ia64_pci_legacy_read(struct pci_bus
*bus
, u16 port
, u32
*val
, u8 size
)
635 * ia64_pci_legacy_write - perform a legacy I/O write
637 * @port: port to write
638 * @val: value to write
639 * @size: number of bytes to write from @val
641 * Simply writes @size bytes of @val to @port.
643 int ia64_pci_legacy_write(struct pci_dev
*bus
, u16 port
, u32 val
, u8 size
)
666 * pci_cacheline_size - determine cacheline size for PCI devices
669 * We want to use the line-size of the outer-most cache. We assume
670 * that this line-size is the same for all CPUs.
672 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
674 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
677 pci_cacheline_size (void)
679 u64 levels
, unique_caches
;
681 pal_cache_config_info_t cci
;
682 static u8 cacheline_size
;
685 return cacheline_size
;
687 status
= ia64_pal_cache_summary(&levels
, &unique_caches
);
689 printk(KERN_ERR
"%s: ia64_pal_cache_summary() failed (status=%ld)\n",
690 __FUNCTION__
, status
);
691 return SMP_CACHE_BYTES
;
694 status
= ia64_pal_cache_config_info(levels
- 1, /* cache_type (data_or_unified)= */ 2,
697 printk(KERN_ERR
"%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
698 __FUNCTION__
, status
);
699 return SMP_CACHE_BYTES
;
701 cacheline_size
= 1 << cci
.pcci_line_size
;
702 return cacheline_size
;
706 * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
707 * @dev: the PCI device for which MWI is enabled
709 * For ia64, we can get the cacheline sizes from PAL.
711 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
714 pcibios_prep_mwi (struct pci_dev
*dev
)
716 unsigned long desired_linesize
, current_linesize
;
720 desired_linesize
= pci_cacheline_size();
722 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &pci_linesize
);
723 current_linesize
= 4 * pci_linesize
;
724 if (desired_linesize
!= current_linesize
) {
725 printk(KERN_WARNING
"PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
726 pci_name(dev
), current_linesize
);
727 if (current_linesize
> desired_linesize
) {
728 printk(" expected %lu bytes instead\n", desired_linesize
);
731 printk(" correcting to %lu\n", desired_linesize
);
732 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, desired_linesize
/ 4);
738 int pci_vector_resources(int last
, int nr_released
)
740 int count
= nr_released
;
742 count
+= (IA64_LAST_DEVICE_VECTOR
- last
);