arch/ia64/sn/pci/pci_dma.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved.
   7  *
   8  * Routines for PCI DMA mapping.  See Documentation/DMA-API.txt for
   9  * a description of how these routines should be used.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <asm/dma.h>
  14 #include <asm/sn/pcibr_provider.h>
  15 #include <asm/sn/pcibus_provider_defs.h>
  16 #include <asm/sn/pcidev.h>
  17 #include <asm/sn/sn_sal.h>
  18
  19 #define SG_ENT_VIRT_ADDRESS(sg) (page_address((sg)->page) + (sg)->offset)
  20 #define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
  21
  22 /**
  23  * sn_dma_supported - test a DMA mask
  24  * @dev: device to test
  25  * @mask: DMA mask to test
  26  *
  27  * Return whether the given PCI device DMA address mask can be supported
  28  * properly.  For example, if your device can only drive the low 24-bits
  29  * during PCI bus mastering, then you would pass 0x00ffffff as the mask to
  30  * this function.  Of course, SN only supports devices that have 32 or more
  31  * address bits when using the PMU.
  32  */
  33 int sn_dma_supported(struct device *dev, u64 mask)
  34 {
  35         BUG_ON(dev->bus != &pci_bus_type);
  36
  37         if (mask < 0x7fffffff)
  38                 return 0;
  39         return 1;
  40 }
  41 EXPORT_SYMBOL(sn_dma_supported);
  42
  43 /**
  44  * sn_dma_set_mask - set the DMA mask
  45  * @dev: device to set
  46  * @dma_mask: new mask
  47  *
  48  * Set @dev's DMA mask if the hw supports it.
  49  */
  50 int sn_dma_set_mask(struct device *dev, u64 dma_mask)
  51 {
  52         BUG_ON(dev->bus != &pci_bus_type);
  53
  54         if (!sn_dma_supported(dev, dma_mask))
  55                 return 0;
  56
  57         *dev->dma_mask = dma_mask;
  58         return 1;
  59 }
  60 EXPORT_SYMBOL(sn_dma_set_mask);
  61
  62 /**
  63  * sn_dma_alloc_coherent - allocate memory for coherent DMA
  64  * @dev: device to allocate for
  65  * @size: size of the region
  66  * @dma_handle: DMA (bus) address
  67  * @flags: memory allocation flags
  68  *
  69  * dma_alloc_coherent() returns a pointer to a memory region suitable for
  70  * coherent DMA traffic to/from a PCI device.  On SN platforms, this means
  71  * that @dma_handle will have the %PCIIO_DMA_CMD flag set.
  72  *
  73  * This interface is usually used for "command" streams (e.g. the command
  74  * queue for a SCSI controller).  See Documentation/DMA-API.txt for
  75  * more information.
  76  */
  77 void *sn_dma_alloc_coherent(struct device *dev, size_t size,
  78                             dma_addr_t * dma_handle, int flags)
  79 {
  80         void *cpuaddr;
  81         unsigned long phys_addr;
  82         struct pci_dev *pdev = to_pci_dev(dev);
  83         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
  84
  85         BUG_ON(dev->bus != &pci_bus_type);
  86
  87         /*
  88          * Allocate the memory.
  89          * FIXME: We should be doing alloc_pages_node for the node closest
  90          *        to the PCI device.
  91          */
  92         if (!(cpuaddr = (void *)__get_free_pages(GFP_ATOMIC, get_order(size))))
  93                 return NULL;
  94
  95         memset(cpuaddr, 0x0, size);
  96
  97         /* physical addr. of the memory we just got */
  98         phys_addr = __pa(cpuaddr);
  99
 100         /*
 101          * 64 bit address translations should never fail.
 102          * 32 bit translations can fail if there are insufficient mapping
 103          * resources.
 104          */
 105
 106         *dma_handle = provider->dma_map_consistent(pdev, phys_addr, size);
 107         if (!*dma_handle) {
 108                 printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
 109                 free_pages((unsigned long)cpuaddr, get_order(size));
 110                 return NULL;
 111         }
 112
 113         return cpuaddr;
 114 }
 115 EXPORT_SYMBOL(sn_dma_alloc_coherent);
 116
 117 /**
 118  * sn_pci_free_coherent - free memory associated with coherent DMAable region
 119  * @dev: device to free for
 120  * @size: size to free
 121  * @cpu_addr: kernel virtual address to free
 122  * @dma_handle: DMA address associated with this region
 123  *
 124  * Frees the memory allocated by dma_alloc_coherent(), potentially unmapping
 125  * any associated IOMMU mappings.
 126  */
 127 void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
 128                           dma_addr_t dma_handle)
 129 {
 130         struct pci_dev *pdev = to_pci_dev(dev);
 131         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 132
 133         BUG_ON(dev->bus != &pci_bus_type);
 134
 135         provider->dma_unmap(pdev, dma_handle, 0);
 136         free_pages((unsigned long)cpu_addr, get_order(size));
 137 }
 138 EXPORT_SYMBOL(sn_dma_free_coherent);
 139
 140 /**
 141  * sn_dma_map_single - map a single page for DMA
 142  * @dev: device to map for
 143  * @cpu_addr: kernel virtual address of the region to map
 144  * @size: size of the region
 145  * @direction: DMA direction
 146  *
 147  * Map the region pointed to by @cpu_addr for DMA and return the
 148  * DMA address.
 149  *
 150  * We map this to the one step pcibr_dmamap_trans interface rather than
 151  * the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have
 152  * no way of saving the dmamap handle from the alloc to later free
 153  * (which is pretty much unacceptable).
 154  *
 155  * TODO: simplify our interface;
 156  *       figure out how to save dmamap handle so can use two step.
 157  */
 158 dma_addr_t sn_dma_map_single(struct device *dev, void *cpu_addr, size_t size,
 159                              int direction)
 160 {
 161         dma_addr_t dma_addr;
 162         unsigned long phys_addr;
 163         struct pci_dev *pdev = to_pci_dev(dev);
 164         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 165
 166         BUG_ON(dev->bus != &pci_bus_type);
 167
 168         phys_addr = __pa(cpu_addr);
 169         dma_addr = provider->dma_map(pdev, phys_addr, size);
 170         if (!dma_addr) {
 171                 printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
 172                 return 0;
 173         }
 174         return dma_addr;
 175 }
 176 EXPORT_SYMBOL(sn_dma_map_single);
 177
 178 /**
 179  * sn_dma_unmap_single - unamp a DMA mapped page
 180  * @dev: device to sync
 181  * @dma_addr: DMA address to sync
 182  * @size: size of region
 183  * @direction: DMA direction
 184  *
 185  * This routine is supposed to sync the DMA region specified
 186  * by @dma_handle into the coherence domain.  On SN, we're always cache
 187  * coherent, so we just need to free any ATEs associated with this mapping.
 188  */
 189 void sn_dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 190                          int direction)
 191 {
 192         struct pci_dev *pdev = to_pci_dev(dev);
 193         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 194
 195         BUG_ON(dev->bus != &pci_bus_type);
 196
 197         provider->dma_unmap(pdev, dma_addr, direction);
 198 }
 199 EXPORT_SYMBOL(sn_dma_unmap_single);
 200
 201 /**
 202  * sn_dma_unmap_sg - unmap a DMA scatterlist
 203  * @dev: device to unmap
 204  * @sg: scatterlist to unmap
 205  * @nhwentries: number of scatterlist entries
 206  * @direction: DMA direction
 207  *
 208  * Unmap a set of streaming mode DMA translations.
 209  */
 210 void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
 211                      int nhwentries, int direction)
 212 {
 213         int i;
 214         struct pci_dev *pdev = to_pci_dev(dev);
 215         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 216
 217         BUG_ON(dev->bus != &pci_bus_type);
 218
 219         for (i = 0; i < nhwentries; i++, sg++) {
 220                 provider->dma_unmap(pdev, sg->dma_address, direction);
 221                 sg->dma_address = (dma_addr_t) NULL;
 222                 sg->dma_length = 0;
 223         }
 224 }
 225 EXPORT_SYMBOL(sn_dma_unmap_sg);
 226
 227 /**
 228  * sn_dma_map_sg - map a scatterlist for DMA
 229  * @dev: device to map for
 230  * @sg: scatterlist to map
 231  * @nhwentries: number of entries
 232  * @direction: direction of the DMA transaction
 233  *
 234  * Maps each entry of @sg for DMA.
 235  */
 236 int sn_dma_map_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
 237                   int direction)
 238 {
 239         unsigned long phys_addr;
 240         struct scatterlist *saved_sg = sg;
 241         struct pci_dev *pdev = to_pci_dev(dev);
 242         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 243         int i;
 244
 245         BUG_ON(dev->bus != &pci_bus_type);
 246
 247         /*
 248          * Setup a DMA address for each entry in the scatterlist.
 249          */
 250         for (i = 0; i < nhwentries; i++, sg++) {
 251                 phys_addr = SG_ENT_PHYS_ADDRESS(sg);
 252                 sg->dma_address = provider->dma_map(pdev,
 253                                                     phys_addr, sg->length);
 254
 255                 if (!sg->dma_address) {
 256                         printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
 257
 258                         /*
 259                          * Free any successfully allocated entries.
 260                          */
 261                         if (i > 0)
 262                                 sn_dma_unmap_sg(dev, saved_sg, i, direction);
 263                         return 0;
 264                 }
 265
 266                 sg->dma_length = sg->length;
 267         }
 268
 269         return nhwentries;
 270 }
 271 EXPORT_SYMBOL(sn_dma_map_sg);
 272
 273 void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
 274                                 size_t size, int direction)
 275 {
 276         BUG_ON(dev->bus != &pci_bus_type);
 277 }
 278 EXPORT_SYMBOL(sn_dma_sync_single_for_cpu);
 279
 280 void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
 281                                    size_t size, int direction)
 282 {
 283         BUG_ON(dev->bus != &pci_bus_type);
 284 }
 285 EXPORT_SYMBOL(sn_dma_sync_single_for_device);
 286
 287 void sn_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
 288                             int nelems, int direction)
 289 {
 290         BUG_ON(dev->bus != &pci_bus_type);
 291 }
 292 EXPORT_SYMBOL(sn_dma_sync_sg_for_cpu);
 293
 294 void sn_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 295                                int nelems, int direction)
 296 {
 297         BUG_ON(dev->bus != &pci_bus_type);
 298 }
 299 EXPORT_SYMBOL(sn_dma_sync_sg_for_device);
 300
 301 int sn_dma_mapping_error(dma_addr_t dma_addr)
 302 {
 303         return 0;
 304 }
 305 EXPORT_SYMBOL(sn_dma_mapping_error);
 306
 307 char *sn_pci_get_legacy_mem(struct pci_bus *bus)
 308 {
 309         if (!SN_PCIBUS_BUSSOFT(bus))
 310                 return ERR_PTR(-ENODEV);
 311
 312         return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem | __IA64_UNCACHED_OFFSET);
 313 }
 314
 315 int sn_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 316 {
 317         unsigned long addr;
 318         int ret;
 319
 320         if (!SN_PCIBUS_BUSSOFT(bus))
 321                 return -ENODEV;
 322
 323         addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
 324         addr += port;
 325
 326         ret = ia64_sn_probe_mem(addr, (long)size, (void *)val);
 327
 328         if (ret == 2)
 329                 return -EINVAL;
 330
 331         if (ret == 1)
 332                 *val = -1;
 333
 334         return size;
 335 }
 336
 337 int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
 338 {
 339         int ret = size;
 340         unsigned long paddr;
 341         unsigned long *addr;
 342
 343         if (!SN_PCIBUS_BUSSOFT(bus)) {
 344                 ret = -ENODEV;
 345                 goto out;
 346         }
 347
 348         /* Put the phys addr in uncached space */
 349         paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
 350         paddr += port;
 351         addr = (unsigned long *)paddr;
 352
 353         switch (size) {
 354         case 1:
 355                 *(volatile u8 *)(addr) = (u8)(val);
 356                 break;
 357         case 2:
 358                 *(volatile u16 *)(addr) = (u16)(val);
 359                 break;
 360         case 4:
 361                 *(volatile u32 *)(addr) = (u32)(val);
 362                 break;
 363         default:
 364                 ret = -EINVAL;
 365                 break;
 366         }
 367  out:
 368         return ret;
 369 }