arch/ia64/sn/pci/pci_dma.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved.
   7  *
   8  * Routines for PCI DMA mapping.  See Documentation/DMA-API.txt for
   9  * a description of how these routines should be used.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/dma-mapping.h>
  14 #include <asm/dma.h>
  15 #include <asm/sn/intr.h>
  16 #include <asm/sn/pcibus_provider_defs.h>
  17 #include <asm/sn/pcidev.h>
  18 #include <asm/sn/sn_sal.h>
  19
  20 #define SG_ENT_VIRT_ADDRESS(sg) (sg_virt((sg)))
  21 #define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
  22
  23 /**
  24  * sn_dma_supported - test a DMA mask
  25  * @dev: device to test
  26  * @mask: DMA mask to test
  27  *
  28  * Return whether the given PCI device DMA address mask can be supported
  29  * properly.  For example, if your device can only drive the low 24-bits
  30  * during PCI bus mastering, then you would pass 0x00ffffff as the mask to
  31  * this function.  Of course, SN only supports devices that have 32 or more
  32  * address bits when using the PMU.
  33  */
  34 static int sn_dma_supported(struct device *dev, u64 mask)
  35 {
  36         BUG_ON(dev->bus != &pci_bus_type);
  37
  38         if (mask < 0x7fffffff)
  39                 return 0;
  40         return 1;
  41 }
  42
  43 /**
  44  * sn_dma_set_mask - set the DMA mask
  45  * @dev: device to set
  46  * @dma_mask: new mask
  47  *
  48  * Set @dev's DMA mask if the hw supports it.
  49  */
  50 int sn_dma_set_mask(struct device *dev, u64 dma_mask)
  51 {
  52         BUG_ON(dev->bus != &pci_bus_type);
  53
  54         if (!sn_dma_supported(dev, dma_mask))
  55                 return 0;
  56
  57         *dev->dma_mask = dma_mask;
  58         return 1;
  59 }
  60 EXPORT_SYMBOL(sn_dma_set_mask);
  61
  62 /**
  63  * sn_dma_alloc_coherent - allocate memory for coherent DMA
  64  * @dev: device to allocate for
  65  * @size: size of the region
  66  * @dma_handle: DMA (bus) address
  67  * @flags: memory allocation flags
  68  *
  69  * dma_alloc_coherent() returns a pointer to a memory region suitable for
  70  * coherent DMA traffic to/from a PCI device.  On SN platforms, this means
  71  * that @dma_handle will have the %PCIIO_DMA_CMD flag set.
  72  *
  73  * This interface is usually used for "command" streams (e.g. the command
  74  * queue for a SCSI controller).  See Documentation/DMA-API.txt for
  75  * more information.
  76  */
  77 static void *sn_dma_alloc_coherent(struct device *dev, size_t size,
  78                                    dma_addr_t * dma_handle, gfp_t flags)
  79 {
  80         void *cpuaddr;
  81         unsigned long phys_addr;
  82         int node;
  83         struct pci_dev *pdev = to_pci_dev(dev);
  84         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
  85
  86         BUG_ON(dev->bus != &pci_bus_type);
  87
  88         /*
  89          * Allocate the memory.
  90          */
  91         node = pcibus_to_node(pdev->bus);
  92         if (likely(node >=0)) {
  93                 struct page *p = alloc_pages_node(node, flags, get_order(size));
  94
  95                 if (likely(p))
  96                         cpuaddr = page_address(p);
  97                 else
  98                         return NULL;
  99         } else
 100                 cpuaddr = (void *)__get_free_pages(flags, get_order(size));
 101
 102         if (unlikely(!cpuaddr))
 103                 return NULL;
 104
 105         memset(cpuaddr, 0x0, size);
 106
 107         /* physical addr. of the memory we just got */
 108         phys_addr = __pa(cpuaddr);
 109
 110         /*
 111          * 64 bit address translations should never fail.
 112          * 32 bit translations can fail if there are insufficient mapping
 113          * resources.
 114          */
 115
 116         *dma_handle = provider->dma_map_consistent(pdev, phys_addr, size,
 117                                                    SN_DMA_ADDR_PHYS);
 118         if (!*dma_handle) {
 119                 printk(KERN_ERR "%s: out of ATEs\n", __func__);
 120                 free_pages((unsigned long)cpuaddr, get_order(size));
 121                 return NULL;
 122         }
 123
 124         return cpuaddr;
 125 }
 126
 127 /**
 128  * sn_pci_free_coherent - free memory associated with coherent DMAable region
 129  * @dev: device to free for
 130  * @size: size to free
 131  * @cpu_addr: kernel virtual address to free
 132  * @dma_handle: DMA address associated with this region
 133  *
 134  * Frees the memory allocated by dma_alloc_coherent(), potentially unmapping
 135  * any associated IOMMU mappings.
 136  */
 137 static void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
 138                                  dma_addr_t dma_handle)
 139 {
 140         struct pci_dev *pdev = to_pci_dev(dev);
 141         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 142
 143         BUG_ON(dev->bus != &pci_bus_type);
 144
 145         provider->dma_unmap(pdev, dma_handle, 0);
 146         free_pages((unsigned long)cpu_addr, get_order(size));
 147 }
 148
 149 /**
 150  * sn_dma_map_single_attrs - map a single page for DMA
 151  * @dev: device to map for
 152  * @cpu_addr: kernel virtual address of the region to map
 153  * @size: size of the region
 154  * @direction: DMA direction
 155  * @attrs: optional dma attributes
 156  *
 157  * Map the region pointed to by @cpu_addr for DMA and return the
 158  * DMA address.
 159  *
 160  * We map this to the one step pcibr_dmamap_trans interface rather than
 161  * the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have
 162  * no way of saving the dmamap handle from the alloc to later free
 163  * (which is pretty much unacceptable).
 164  *
 165  * mappings with the DMA_ATTR_WRITE_BARRIER get mapped with
 166  * dma_map_consistent() so that writes force a flush of pending DMA.
 167  * (See "SGI Altix Architecture Considerations for Linux Device Drivers",
 168  * Document Number: 007-4763-001)
 169  *
 170  * TODO: simplify our interface;
 171  *       figure out how to save dmamap handle so can use two step.
 172  */
 173 static dma_addr_t sn_dma_map_page(struct device *dev, struct page *page,
 174                                   unsigned long offset, size_t size,
 175                                   enum dma_data_direction dir,
 176                                   struct dma_attrs *attrs)
 177 {
 178         void *cpu_addr = page_address(page) + offset;
 179         dma_addr_t dma_addr;
 180         unsigned long phys_addr;
 181         struct pci_dev *pdev = to_pci_dev(dev);
 182         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 183         int dmabarr;
 184
 185         dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs);
 186
 187         BUG_ON(dev->bus != &pci_bus_type);
 188
 189         phys_addr = __pa(cpu_addr);
 190         if (dmabarr)
 191                 dma_addr = provider->dma_map_consistent(pdev, phys_addr,
 192                                                         size, SN_DMA_ADDR_PHYS);
 193         else
 194                 dma_addr = provider->dma_map(pdev, phys_addr, size,
 195                                              SN_DMA_ADDR_PHYS);
 196
 197         if (!dma_addr) {
 198                 printk(KERN_ERR "%s: out of ATEs\n", __func__);
 199                 return 0;
 200         }
 201         return dma_addr;
 202 }
 203
 204 /**
 205  * sn_dma_unmap_single_attrs - unamp a DMA mapped page
 206  * @dev: device to sync
 207  * @dma_addr: DMA address to sync
 208  * @size: size of region
 209  * @direction: DMA direction
 210  * @attrs: optional dma attributes
 211  *
 212  * This routine is supposed to sync the DMA region specified
 213  * by @dma_handle into the coherence domain.  On SN, we're always cache
 214  * coherent, so we just need to free any ATEs associated with this mapping.
 215  */
 216 static void sn_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
 217                               size_t size, enum dma_data_direction dir,
 218                               struct dma_attrs *attrs)
 219 {
 220         struct pci_dev *pdev = to_pci_dev(dev);
 221         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 222
 223         BUG_ON(dev->bus != &pci_bus_type);
 224
 225         provider->dma_unmap(pdev, dma_addr, dir);
 226 }
 227
 228 /**
 229  * sn_dma_unmap_sg - unmap a DMA scatterlist
 230  * @dev: device to unmap
 231  * @sg: scatterlist to unmap
 232  * @nhwentries: number of scatterlist entries
 233  * @direction: DMA direction
 234  * @attrs: optional dma attributes
 235  *
 236  * Unmap a set of streaming mode DMA translations.
 237  */
 238 static void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
 239                             int nhwentries, enum dma_data_direction dir,
 240                             struct dma_attrs *attrs)
 241 {
 242         int i;
 243         struct pci_dev *pdev = to_pci_dev(dev);
 244         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 245         struct scatterlist *sg;
 246
 247         BUG_ON(dev->bus != &pci_bus_type);
 248
 249         for_each_sg(sgl, sg, nhwentries, i) {
 250                 provider->dma_unmap(pdev, sg->dma_address, dir);
 251                 sg->dma_address = (dma_addr_t) NULL;
 252                 sg->dma_length = 0;
 253         }
 254 }
 255
 256 /**
 257  * sn_dma_map_sg - map a scatterlist for DMA
 258  * @dev: device to map for
 259  * @sg: scatterlist to map
 260  * @nhwentries: number of entries
 261  * @direction: direction of the DMA transaction
 262  * @attrs: optional dma attributes
 263  *
 264  * mappings with the DMA_ATTR_WRITE_BARRIER get mapped with
 265  * dma_map_consistent() so that writes force a flush of pending DMA.
 266  * (See "SGI Altix Architecture Considerations for Linux Device Drivers",
 267  * Document Number: 007-4763-001)
 268  *
 269  * Maps each entry of @sg for DMA.
 270  */
 271 static int sn_dma_map_sg(struct device *dev, struct scatterlist *sgl,
 272                          int nhwentries, enum dma_data_direction dir,
 273                          struct dma_attrs *attrs)
 274 {
 275         unsigned long phys_addr;
 276         struct scatterlist *saved_sg = sgl, *sg;
 277         struct pci_dev *pdev = to_pci_dev(dev);
 278         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 279         int i;
 280         int dmabarr;
 281
 282         dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs);
 283
 284         BUG_ON(dev->bus != &pci_bus_type);
 285
 286         /*
 287          * Setup a DMA address for each entry in the scatterlist.
 288          */
 289         for_each_sg(sgl, sg, nhwentries, i) {
 290                 dma_addr_t dma_addr;
 291                 phys_addr = SG_ENT_PHYS_ADDRESS(sg);
 292                 if (dmabarr)
 293                         dma_addr = provider->dma_map_consistent(pdev,
 294                                                                 phys_addr,
 295                                                                 sg->length,
 296                                                                 SN_DMA_ADDR_PHYS);
 297                 else
 298                         dma_addr = provider->dma_map(pdev, phys_addr,
 299                                                      sg->length,
 300                                                      SN_DMA_ADDR_PHYS);
 301
 302                 sg->dma_address = dma_addr;
 303                 if (!sg->dma_address) {
 304                         printk(KERN_ERR "%s: out of ATEs\n", __func__);
 305
 306                         /*
 307                          * Free any successfully allocated entries.
 308                          */
 309                         if (i > 0)
 310                                 sn_dma_unmap_sg(dev, saved_sg, i, dir, attrs);
 311                         return 0;
 312                 }
 313
 314                 sg->dma_length = sg->length;
 315         }
 316
 317         return nhwentries;
 318 }
 319
 320 static void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
 321                                        size_t size, enum dma_data_direction dir)
 322 {
 323         BUG_ON(dev->bus != &pci_bus_type);
 324 }
 325
 326 static void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
 327                                           size_t size,
 328                                           enum dma_data_direction dir)
 329 {
 330         BUG_ON(dev->bus != &pci_bus_type);
 331 }
 332
 333 static void sn_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
 334                                    int nelems, enum dma_data_direction dir)
 335 {
 336         BUG_ON(dev->bus != &pci_bus_type);
 337 }
 338
 339 static void sn_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 340                                       int nelems, enum dma_data_direction dir)
 341 {
 342         BUG_ON(dev->bus != &pci_bus_type);
 343 }
 344
 345 static int sn_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 346 {
 347         return 0;
 348 }
 349
 350 u64 sn_dma_get_required_mask(struct device *dev)
 351 {
 352         return DMA_64BIT_MASK;
 353 }
 354 EXPORT_SYMBOL_GPL(sn_dma_get_required_mask);
 355
 356 char *sn_pci_get_legacy_mem(struct pci_bus *bus)
 357 {
 358         if (!SN_PCIBUS_BUSSOFT(bus))
 359                 return ERR_PTR(-ENODEV);
 360
 361         return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem | __IA64_UNCACHED_OFFSET);
 362 }
 363
 364 int sn_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 365 {
 366         unsigned long addr;
 367         int ret;
 368         struct ia64_sal_retval isrv;
 369
 370         /*
 371          * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
 372          * around hw issues at the pci bus level.  SGI proms older than
 373          * 4.10 don't implement this.
 374          */
 375
 376         SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
 377                  pci_domain_nr(bus), bus->number,
 378                  0, /* io */
 379                  0, /* read */
 380                  port, size, __pa(val));
 381
 382         if (isrv.status == 0)
 383                 return size;
 384
 385         /*
 386          * If the above failed, retry using the SAL_PROBE call which should
 387          * be present in all proms (but which cannot work round PCI chipset
 388          * bugs).  This code is retained for compatibility with old
 389          * pre-4.10 proms, and should be removed at some point in the future.
 390          */
 391
 392         if (!SN_PCIBUS_BUSSOFT(bus))
 393                 return -ENODEV;
 394
 395         addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
 396         addr += port;
 397
 398         ret = ia64_sn_probe_mem(addr, (long)size, (void *)val);
 399
 400         if (ret == 2)
 401                 return -EINVAL;
 402
 403         if (ret == 1)
 404                 *val = -1;
 405
 406         return size;
 407 }
 408
 409 int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
 410 {
 411         int ret = size;
 412         unsigned long paddr;
 413         unsigned long *addr;
 414         struct ia64_sal_retval isrv;
 415
 416         /*
 417          * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
 418          * around hw issues at the pci bus level.  SGI proms older than
 419          * 4.10 don't implement this.
 420          */
 421
 422         SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
 423                  pci_domain_nr(bus), bus->number,
 424                  0, /* io */
 425                  1, /* write */
 426                  port, size, __pa(&val));
 427
 428         if (isrv.status == 0)
 429                 return size;
 430
 431         /*
 432          * If the above failed, retry using the SAL_PROBE call which should
 433          * be present in all proms (but which cannot work round PCI chipset
 434          * bugs).  This code is retained for compatibility with old
 435          * pre-4.10 proms, and should be removed at some point in the future.
 436          */
 437
 438         if (!SN_PCIBUS_BUSSOFT(bus)) {
 439                 ret = -ENODEV;
 440                 goto out;
 441         }
 442
 443         /* Put the phys addr in uncached space */
 444         paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
 445         paddr += port;
 446         addr = (unsigned long *)paddr;
 447
 448         switch (size) {
 449         case 1:
 450                 *(volatile u8 *)(addr) = (u8)(val);
 451                 break;
 452         case 2:
 453                 *(volatile u16 *)(addr) = (u16)(val);
 454                 break;
 455         case 4:
 456                 *(volatile u32 *)(addr) = (u32)(val);
 457                 break;
 458         default:
 459                 ret = -EINVAL;
 460                 break;
 461         }
 462  out:
 463         return ret;
 464 }
 465
 466 static struct dma_map_ops sn_dma_ops = {
 467         .alloc_coherent         = sn_dma_alloc_coherent,
 468         .free_coherent          = sn_dma_free_coherent,
 469         .map_page               = sn_dma_map_page,
 470         .unmap_page             = sn_dma_unmap_page,
 471         .map_sg                 = sn_dma_map_sg,
 472         .unmap_sg               = sn_dma_unmap_sg,
 473         .sync_single_for_cpu    = sn_dma_sync_single_for_cpu,
 474         .sync_sg_for_cpu        = sn_dma_sync_sg_for_cpu,
 475         .sync_single_for_device = sn_dma_sync_single_for_device,
 476         .sync_sg_for_device     = sn_dma_sync_sg_for_device,
 477         .mapping_error          = sn_dma_mapping_error,
 478         .dma_supported          = sn_dma_supported,
 479 };
 480
 481 void sn_dma_init(void)
 482 {
 483         dma_ops = &sn_dma_ops;
 484 }