1 /***************************************************************************/
4 * linux/arch/m68knommu/platform/527x/config.c
6 * Sub-architcture dependent initialization code for the Freescale
9 * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
13 /***************************************************************************/
15 #include <linux/kernel.h>
16 #include <linux/param.h>
17 #include <linux/init.h>
19 #include <asm/machdep.h>
20 #include <asm/coldfire.h>
21 #include <asm/mcfsim.h>
22 #include <asm/mcfuart.h>
24 /***************************************************************************/
26 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
28 static void __init
m527x_qspi_init(void)
30 #if defined(CONFIG_M5271)
33 /* setup QSPS pins for QSPI with gpio CS control */
34 writeb(0x1f, MCFGPIO_PAR_QSPI
);
35 /* and CS2 & CS3 as gpio */
36 par
= readw(MCFGPIO_PAR_TIMER
);
38 writew(par
, MCFGPIO_PAR_TIMER
);
39 #elif defined(CONFIG_M5275)
40 /* setup QSPS pins for QSPI with gpio CS control */
41 writew(0x003e, MCFGPIO_PAR_QSPI
);
45 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
47 /***************************************************************************/
49 static void __init
m527x_uarts_init(void)
54 * External Pin Mask Setting & Enable External Pin for Interface
56 sepmask
= readw(MCFGPIO_PAR_UART
);
57 sepmask
|= UART0_ENABLE_MASK
| UART1_ENABLE_MASK
| UART2_ENABLE_MASK
;
58 writew(sepmask
, MCFGPIO_PAR_UART
);
61 /***************************************************************************/
63 static void __init
m527x_fec_init(void)
68 /* Set multi-function pins to ethernet mode for fec0 */
69 #if defined(CONFIG_M5271)
70 v
= readb(MCFGPIO_PAR_FECI2C
);
71 writeb(v
| 0xf0, MCFGPIO_PAR_FECI2C
);
73 par
= readw(MCFGPIO_PAR_FECI2C
);
74 writew(par
| 0xf00, MCFGPIO_PAR_FECI2C
);
75 v
= readb(MCFGPIO_PAR_FEC0HL
);
76 writeb(v
| 0xc0, MCFGPIO_PAR_FEC0HL
);
78 /* Set multi-function pins to ethernet mode for fec1 */
79 par
= readw(MCFGPIO_PAR_FECI2C
);
80 writew(par
| 0xa0, MCFGPIO_PAR_FECI2C
);
81 v
= readb(MCFGPIO_PAR_FEC1HL
);
82 writeb(v
| 0xc0, MCFGPIO_PAR_FEC1HL
);
86 /***************************************************************************/
88 void __init
config_BSP(char *commandp
, int size
)
90 mach_sched_init
= hw_timer_init
;
93 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
98 /***************************************************************************/
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