arch/metag/Kconfig.soc

   1 choice
   2         prompt "SoC Type"
   3         default META21_FPGA
   4
   5 config META12_FPGA
   6         bool "Meta 1.2 FPGA"
   7         select METAG_META12
   8         help
   9           This is a Meta 1.2 FPGA bitstream, just a bare CPU.
  10
  11 config META21_FPGA
  12         bool "Meta 2.1 FPGA"
  13         select METAG_META21
  14         help
  15           This is a Meta 2.1 FPGA bitstream, just a bare CPU.
  16
  17 config SOC_TZ1090
  18         bool "Toumaz Xenif TZ1090 SoC (Comet)"
  19         select METAG_LNKGET_AROUND_CACHE
  20         select METAG_META21
  21         select METAG_SMP_WRITE_REORDERING
  22         select PINCTRL
  23         select PINCTRL_TZ1090
  24         select PINCTRL_TZ1090_PDC
  25         help
  26           This is a Toumaz Technology Xenif TZ1090 (A.K.A. Comet) SoC containing
  27           a 2-threaded HTP.
  28
  29 endchoice
  30
  31 menu "SoC configuration"
  32
  33 if METAG_META21
  34
  35 # Meta 2.x specific options
  36
  37 config METAG_META21_MMU
  38         bool "Meta 2.x MMU mode"
  39         default y
  40         help
  41           Use the Meta 2.x MMU in extended mode.
  42
  43 config METAG_UNALIGNED
  44         bool "Meta 2.x unaligned access checking"
  45         default y
  46         help
  47           All memory accesses will be checked for alignment and an exception
  48           raised on unaligned accesses. This feature does cost performance
  49           but without it there will be no notification of this type of error.
  50
  51 config METAG_USER_TCM
  52         bool "Meta on-chip memory support for userland"
  53         select GENERIC_ALLOCATOR
  54         default y
  55         help
  56           Allow the on-chip memories of Meta SoCs to be used by user
  57           applications.
  58
  59 endif
  60
  61 config METAG_HALT_ON_PANIC
  62         bool "Halt the core on panic"
  63         help
  64           Halt the core when a panic occurs. This is useful when running
  65           pre-production silicon or in an FPGA environment.
  66
  67 endmenu