arch/metag/include/asm/pgtable.h

   1 /*
   2  * Macros and functions to manipulate Meta page tables.
   3  */
   4
   5 #ifndef _METAG_PGTABLE_H
   6 #define _METAG_PGTABLE_H
   7
   8 #include <asm-generic/pgtable-nopmd.h>
   9
  10 /* Invalid regions on Meta: 0x00000000-0x001FFFFF and 0xFFFF0000-0xFFFFFFFF */
  11 #if PAGE_OFFSET >= LINGLOBAL_BASE
  12 #define CONSISTENT_START        0xF7000000
  13 #define CONSISTENT_END          0xF73FFFFF
  14 #define VMALLOC_START           0xF8000000
  15 #define VMALLOC_END             0xFFFEFFFF
  16 #else
  17 #define CONSISTENT_START        0x77000000
  18 #define CONSISTENT_END          0x773FFFFF
  19 #define VMALLOC_START           0x78000000
  20 #define VMALLOC_END             0x7FFFFFFF
  21 #endif
  22
  23 /*
  24  * Definitions for MMU descriptors
  25  *
  26  * These are the hardware bits in the MMCU pte entries.
  27  * Derived from the Meta toolkit headers.
  28  */
  29 #define _PAGE_PRESENT           MMCU_ENTRY_VAL_BIT
  30 #define _PAGE_WRITE             MMCU_ENTRY_WR_BIT
  31 #define _PAGE_PRIV              MMCU_ENTRY_PRIV_BIT
  32 /* Write combine bit - this can cause writes to occur out of order */
  33 #define _PAGE_WR_COMBINE        MMCU_ENTRY_WRC_BIT
  34 /* Sys coherent bit - this bit is never used by Linux */
  35 #define _PAGE_SYS_COHERENT      MMCU_ENTRY_SYS_BIT
  36 #define _PAGE_ALWAYS_ZERO_1     0x020
  37 #define _PAGE_CACHE_CTRL0       0x040
  38 #define _PAGE_CACHE_CTRL1       0x080
  39 #define _PAGE_ALWAYS_ZERO_2     0x100
  40 #define _PAGE_ALWAYS_ZERO_3     0x200
  41 #define _PAGE_ALWAYS_ZERO_4     0x400
  42 #define _PAGE_ALWAYS_ZERO_5     0x800
  43
  44 /* These are software bits that we stuff into the gaps in the hardware
  45  * pte entries that are not used.  Note, these DO get stored in the actual
  46  * hardware, but the hardware just does not use them.
  47  */
  48 #define _PAGE_ACCESSED          _PAGE_ALWAYS_ZERO_1
  49 #define _PAGE_DIRTY             _PAGE_ALWAYS_ZERO_2
  50
  51 /* Pages owned, and protected by, the kernel. */
  52 #define _PAGE_KERNEL            _PAGE_PRIV
  53
  54 /* No cacheing of this page */
  55 #define _PAGE_CACHE_WIN0        (MMCU_CWIN_UNCACHED << MMCU_ENTRY_CWIN_S)
  56 /* burst cacheing - good for data streaming */
  57 #define _PAGE_CACHE_WIN1        (MMCU_CWIN_BURST << MMCU_ENTRY_CWIN_S)
  58 /* One cache way per thread */
  59 #define _PAGE_CACHE_WIN2        (MMCU_CWIN_C1SET << MMCU_ENTRY_CWIN_S)
  60 /* Full on cacheing */
  61 #define _PAGE_CACHE_WIN3        (MMCU_CWIN_CACHED << MMCU_ENTRY_CWIN_S)
  62
  63 #define _PAGE_CACHEABLE         (_PAGE_CACHE_WIN3 | _PAGE_WR_COMBINE)
  64
  65 /* which bits are used for cache control ... */
  66 #define _PAGE_CACHE_MASK        (_PAGE_CACHE_CTRL0 | _PAGE_CACHE_CTRL1 | \
  67                                  _PAGE_WR_COMBINE)
  68
  69 /* This is a mask of the bits that pte_modify is allowed to change. */
  70 #define _PAGE_CHG_MASK          (PAGE_MASK)
  71
  72 #define _PAGE_SZ_SHIFT          1
  73 #define _PAGE_SZ_4K             (0x0)
  74 #define _PAGE_SZ_8K             (0x1 << _PAGE_SZ_SHIFT)
  75 #define _PAGE_SZ_16K            (0x2 << _PAGE_SZ_SHIFT)
  76 #define _PAGE_SZ_32K            (0x3 << _PAGE_SZ_SHIFT)
  77 #define _PAGE_SZ_64K            (0x4 << _PAGE_SZ_SHIFT)
  78 #define _PAGE_SZ_128K           (0x5 << _PAGE_SZ_SHIFT)
  79 #define _PAGE_SZ_256K           (0x6 << _PAGE_SZ_SHIFT)
  80 #define _PAGE_SZ_512K           (0x7 << _PAGE_SZ_SHIFT)
  81 #define _PAGE_SZ_1M             (0x8 << _PAGE_SZ_SHIFT)
  82 #define _PAGE_SZ_2M             (0x9 << _PAGE_SZ_SHIFT)
  83 #define _PAGE_SZ_4M             (0xa << _PAGE_SZ_SHIFT)
  84 #define _PAGE_SZ_MASK           (0xf << _PAGE_SZ_SHIFT)
  85
  86 #if defined(CONFIG_PAGE_SIZE_4K)
  87 #define _PAGE_SZ                (_PAGE_SZ_4K)
  88 #elif defined(CONFIG_PAGE_SIZE_8K)
  89 #define _PAGE_SZ                (_PAGE_SZ_8K)
  90 #elif defined(CONFIG_PAGE_SIZE_16K)
  91 #define _PAGE_SZ                (_PAGE_SZ_16K)
  92 #endif
  93 #define _PAGE_TABLE             (_PAGE_SZ | _PAGE_PRESENT)
  94
  95 #if defined(CONFIG_HUGETLB_PAGE_SIZE_8K)
  96 # define _PAGE_SZHUGE           (_PAGE_SZ_8K)
  97 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_16K)
  98 # define _PAGE_SZHUGE           (_PAGE_SZ_16K)
  99 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_32K)
 100 # define _PAGE_SZHUGE           (_PAGE_SZ_32K)
 101 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
 102 # define _PAGE_SZHUGE           (_PAGE_SZ_64K)
 103 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_128K)
 104 # define _PAGE_SZHUGE           (_PAGE_SZ_128K)
 105 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
 106 # define _PAGE_SZHUGE           (_PAGE_SZ_256K)
 107 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
 108 # define _PAGE_SZHUGE           (_PAGE_SZ_512K)
 109 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_1M)
 110 # define _PAGE_SZHUGE           (_PAGE_SZ_1M)
 111 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_2M)
 112 # define _PAGE_SZHUGE           (_PAGE_SZ_2M)
 113 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_4M)
 114 # define _PAGE_SZHUGE           (_PAGE_SZ_4M)
 115 #endif
 116
 117 /*
 118  * The Linux memory management assumes a three-level page table setup. On
 119  * Meta, we use that, but "fold" the mid level into the top-level page
 120  * table.
 121  */
 122
 123 /* PGDIR_SHIFT determines the size of the area a second-level page table can
 124  * map. This is always 4MB.
 125  */
 126
 127 #define PGDIR_SHIFT     22
 128 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 129 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 130
 131 /*
 132  * Entries per page directory level: we use a two-level, so
 133  * we don't really have any PMD directory physically. First level tables
 134  * always map 2Gb (local or global) at a granularity of 4MB, second-level
 135  * tables map 4MB with a granularity between 4MB and 4kB (between 1 and
 136  * 1024 entries).
 137  */
 138 #define PTRS_PER_PTE    (PGDIR_SIZE/PAGE_SIZE)
 139 #define HPTRS_PER_PTE   (PGDIR_SIZE/HPAGE_SIZE)
 140 #define PTRS_PER_PGD    512
 141
 142 #define USER_PTRS_PER_PGD       256
 143 #define FIRST_USER_ADDRESS      META_MEMORY_BASE
 144 #define FIRST_USER_PGD_NR       pgd_index(FIRST_USER_ADDRESS)
 145
 146 #define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
 147                                  _PAGE_CACHEABLE)
 148
 149 #define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \
 150                                  _PAGE_ACCESSED | _PAGE_CACHEABLE)
 151 #define PAGE_SHARED_C   PAGE_SHARED
 152 #define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
 153                                  _PAGE_CACHEABLE)
 154 #define PAGE_COPY_C     PAGE_COPY
 155
 156 #define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
 157                                  _PAGE_CACHEABLE)
 158 #define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
 159                                  _PAGE_ACCESSED | _PAGE_WRITE | \
 160                                  _PAGE_CACHEABLE | _PAGE_KERNEL)
 161
 162 #define __P000  PAGE_NONE
 163 #define __P001  PAGE_READONLY
 164 #define __P010  PAGE_COPY
 165 #define __P011  PAGE_COPY
 166 #define __P100  PAGE_READONLY
 167 #define __P101  PAGE_READONLY
 168 #define __P110  PAGE_COPY_C
 169 #define __P111  PAGE_COPY_C
 170
 171 #define __S000  PAGE_NONE
 172 #define __S001  PAGE_READONLY
 173 #define __S010  PAGE_SHARED
 174 #define __S011  PAGE_SHARED
 175 #define __S100  PAGE_READONLY
 176 #define __S101  PAGE_READONLY
 177 #define __S110  PAGE_SHARED_C
 178 #define __S111  PAGE_SHARED_C
 179
 180 #ifndef __ASSEMBLY__
 181
 182 #include <asm/page.h>
 183
 184 /* zero page used for uninitialized stuff */
 185 extern unsigned long empty_zero_page;
 186 #define ZERO_PAGE(vaddr)        (virt_to_page(empty_zero_page))
 187
 188 /* Certain architectures need to do special things when pte's
 189  * within a page table are directly modified.  Thus, the following
 190  * hook is made available.
 191  */
 192 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
 193 #define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
 194
 195 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
 196
 197 #define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
 198
 199 #define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 200
 201 #define pte_none(x)             (!pte_val(x))
 202 #define pte_present(x)          (pte_val(x) & _PAGE_PRESENT)
 203 #define pte_clear(mm, addr, xp) do { pte_val(*(xp)) = 0; } while (0)
 204
 205 #define pmd_none(x)             (!pmd_val(x))
 206 #define pmd_bad(x)              ((pmd_val(x) & ~(PAGE_MASK | _PAGE_SZ_MASK)) \
 207                                         != (_PAGE_TABLE & ~_PAGE_SZ_MASK))
 208 #define pmd_present(x)          (pmd_val(x) & _PAGE_PRESENT)
 209 #define pmd_clear(xp)           do { pmd_val(*(xp)) = 0; } while (0)
 210
 211 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 212
 213 /*
 214  * The following only work if pte_present() is true.
 215  * Undefined behaviour if not..
 216  */
 217
 218 static inline int pte_write(pte_t pte)   { return pte_val(pte) & _PAGE_WRITE; }
 219 static inline int pte_dirty(pte_t pte)   { return pte_val(pte) & _PAGE_DIRTY; }
 220 static inline int pte_young(pte_t pte)   { return pte_val(pte) & _PAGE_ACCESSED; }
 221 static inline int pte_special(pte_t pte) { return 0; }
 222
 223 static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= (~_PAGE_WRITE); return pte; }
 224 static inline pte_t pte_mkclean(pte_t pte)   { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
 225 static inline pte_t pte_mkold(pte_t pte)     { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 226 static inline pte_t pte_mkwrite(pte_t pte)   { pte_val(pte) |= _PAGE_WRITE; return pte; }
 227 static inline pte_t pte_mkdirty(pte_t pte)   { pte_val(pte) |= _PAGE_DIRTY; return pte; }
 228 static inline pte_t pte_mkyoung(pte_t pte)   { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 229 static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 230 static inline pte_t pte_mkhuge(pte_t pte)    { return pte; }
 231
 232 /*
 233  * Macro and implementation to make a page protection as uncacheable.
 234  */
 235 #define pgprot_writecombine(prot)                                       \
 236         __pgprot(pgprot_val(prot) & ~(_PAGE_CACHE_CTRL1 | _PAGE_CACHE_CTRL0))
 237
 238 #define pgprot_noncached(prot)                                          \
 239         __pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE)
 240
 241
 242 /*
 243  * Conversion functions: convert a page and protection to a page entry,
 244  * and a page entry and page directory to the page they refer to.
 245  */
 246
 247 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 248
 249 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 250 {
 251         pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
 252         return pte;
 253 }
 254
 255 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
 256 {
 257         unsigned long paddr = pmd_val(pmd) & PAGE_MASK;
 258         if (!paddr)
 259                 return 0;
 260         return (unsigned long)__va(paddr);
 261 }
 262
 263 #define pmd_page(pmd)           (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
 264 #define pmd_page_shift(pmd)     (12 + ((pmd_val(pmd) & _PAGE_SZ_MASK) \
 265                                         >> _PAGE_SZ_SHIFT))
 266 #define pmd_num_ptrs(pmd)       (PGDIR_SIZE >> pmd_page_shift(pmd))
 267
 268 /*
 269  * Each pgd is only 2k, mapping 2Gb (local or global). If we're in global
 270  * space drop the top bit before indexing the pgd.
 271  */
 272 #if PAGE_OFFSET >= LINGLOBAL_BASE
 273 #define pgd_index(address)      ((((address) & ~0x80000000) >> PGDIR_SHIFT) \
 274                                                         & (PTRS_PER_PGD-1))
 275 #else
 276 #define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 277 #endif
 278
 279 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
 280
 281 #define pgd_offset_k(address)   pgd_offset(&init_mm, address)
 282
 283 #define pmd_index(address)      (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 284
 285 /* Find an entry in the second-level page table.. */
 286 #if !defined(CONFIG_HUGETLB_PAGE)
 287   /* all pages are of size (1 << PAGE_SHIFT), so no need to read 1st level pt */
 288 # define pte_index(pmd, address) \
 289         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 290 #else
 291   /* some pages are huge, so read 1st level pt to find out */
 292 # define pte_index(pmd, address) \
 293         (((address) >> pmd_page_shift(pmd)) & (pmd_num_ptrs(pmd) - 1))
 294 #endif
 295 #define pte_offset_kernel(dir, address) \
 296         ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(*(dir), address))
 297 #define pte_offset_map(dir, address)            pte_offset_kernel(dir, address)
 298 #define pte_offset_map_nested(dir, address)     pte_offset_kernel(dir, address)
 299
 300 #define pte_unmap(pte)          do { } while (0)
 301 #define pte_unmap_nested(pte)   do { } while (0)
 302
 303 #define pte_ERROR(e) \
 304         pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 305 #define pgd_ERROR(e) \
 306         pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 307
 308 /*
 309  * Meta doesn't have any external MMU info: the kernel page
 310  * tables contain all the necessary information.
 311  */
 312 static inline void update_mmu_cache(struct vm_area_struct *vma,
 313                                     unsigned long address, pte_t *pte)
 314 {
 315 }
 316
 317 /*
 318  * Encode and decode a swap entry (must be !pte_none(e) && !pte_present(e))
 319  * Since PAGE_PRESENT is bit 1, we can use the bits above that.
 320  */
 321 #define __swp_type(x)                   (((x).val >> 1) & 0xff)
 322 #define __swp_offset(x)                 ((x).val >> 10)
 323 #define __swp_entry(type, offset)       ((swp_entry_t) { ((type) << 1) | \
 324                                          ((offset) << 10) })
 325 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
 326 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
 327
 328 #define kern_addr_valid(addr)   (1)
 329
 330 /*
 331  * No page table caches to initialise
 332  */
 333 #define pgtable_cache_init()    do { } while (0)
 334
 335 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 336 void paging_init(unsigned long mem_end);
 337
 338 #ifdef CONFIG_METAG_META12
 339 /* This is a workaround for an issue in Meta 1 cores. These cores cache
 340  * invalid entries in the TLB so we always need to flush whenever we add
 341  * a new pte. Unfortunately we can only flush the whole TLB not shoot down
 342  * single entries so this is sub-optimal. This implementation ensures that
 343  * we will get a flush at the second attempt, so we may still get repeated
 344  * faults, we just don't overflow the kernel stack handling them.
 345  */
 346 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 347 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
 348 ({                                                                        \
 349         int __changed = !pte_same(*(__ptep), __entry);                    \
 350         if (__changed) {                                                  \
 351                 set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
 352         }                                                                 \
 353         flush_tlb_page(__vma, __address);                                 \
 354         __changed;                                                        \
 355 })
 356 #endif
 357
 358 #include <asm-generic/pgtable.h>
 359
 360 #endif /* __ASSEMBLY__ */
 361 #endif /* _METAG_PGTABLE_H */