arch/metag/kernel/cachepart.c

   1 /*
   2  * Meta cache partition manipulation.
   3  *
   4  * Copyright 2010 Imagination Technologies Ltd.
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/io.h>
   9 #include <linux/errno.h>
  10 #include <asm/processor.h>
  11 #include <asm/cachepart.h>
  12 #include <asm/metag_isa.h>
  13 #include <asm/metag_mem.h>
  14
  15 #define SYSC_DCPART(n)  (SYSC_DCPART0 + SYSC_xCPARTn_STRIDE * (n))
  16 #define SYSC_ICPART(n)  (SYSC_ICPART0 + SYSC_xCPARTn_STRIDE * (n))
  17
  18 #define CACHE_ASSOCIATIVITY 4 /* 4 way set-assosiative */
  19 #define ICACHE 0
  20 #define DCACHE 1
  21
  22 /* The CORE_CONFIG2 register is not available on Meta 1 */
  23 #ifdef CONFIG_METAG_META21
  24 unsigned int get_dcache_size(void)
  25 {
  26         unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
  27         return 0x1000 << ((config2 & METAC_CORECFG2_DCSZ_BITS)
  28                                 >> METAC_CORECFG2_DCSZ_S);
  29 }
  30
  31 unsigned int get_icache_size(void)
  32 {
  33         unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
  34         return 0x1000 << ((config2 & METAC_CORE_C2ICSZ_BITS)
  35                                 >> METAC_CORE_C2ICSZ_S);
  36 }
  37
  38 unsigned int get_global_dcache_size(void)
  39 {
  40         unsigned int cpart = metag_in32(SYSC_DCPART(hard_processor_id()));
  41         unsigned int temp = cpart & SYSC_xCPARTG_AND_BITS;
  42         return (get_dcache_size() * ((temp >> SYSC_xCPARTG_AND_S) + 1)) >> 4;
  43 }
  44
  45 unsigned int get_global_icache_size(void)
  46 {
  47         unsigned int cpart = metag_in32(SYSC_ICPART(hard_processor_id()));
  48         unsigned int temp = cpart & SYSC_xCPARTG_AND_BITS;
  49         return (get_icache_size() * ((temp >> SYSC_xCPARTG_AND_S) + 1)) >> 4;
  50 }
  51
  52 static unsigned int get_thread_cache_size(unsigned int cache, int thread_id)
  53 {
  54         unsigned int cache_size;
  55         unsigned int t_cache_part;
  56         unsigned int isEnabled;
  57         unsigned int offset = 0;
  58         isEnabled = (cache == DCACHE ? metag_in32(MMCU_DCACHE_CTRL_ADDR) & 0x1 :
  59                 metag_in32(MMCU_ICACHE_CTRL_ADDR) & 0x1);
  60         if (!isEnabled)
  61                 return 0;
  62 #if PAGE_OFFSET >= LINGLOBAL_BASE
  63         /* Checking for global cache */
  64         cache_size = (cache == DCACHE ? get_global_dache_size() :
  65                 get_global_icache_size());
  66         offset = 8;
  67 #else
  68         cache_size = (cache == DCACHE ? get_dcache_size() :
  69                 get_icache_size());
  70 #endif
  71         t_cache_part = (cache == DCACHE ?
  72                 (metag_in32(SYSC_DCPART(thread_id)) >> offset) & 0xF :
  73                 (metag_in32(SYSC_ICPART(thread_id)) >> offset) & 0xF);
  74         switch (t_cache_part) {
  75         case 0xF:
  76                 return cache_size;
  77         case 0x7:
  78                 return cache_size / 2;
  79         case 0x3:
  80                 return cache_size / 4;
  81         case 0x1:
  82                 return cache_size / 8;
  83         case 0:
  84                 return cache_size / 16;
  85         }
  86         return -1;
  87 }
  88
  89 void check_for_cache_aliasing(int thread_id)
  90 {
  91         unsigned int thread_cache_size;
  92         unsigned int cache_type;
  93         for (cache_type = ICACHE; cache_type <= DCACHE; cache_type++) {
  94                 thread_cache_size =
  95                                 get_thread_cache_size(cache_type, thread_id);
  96                 if (thread_cache_size < 0)
  97                         pr_emerg("Can't read %s cache size", \
  98                                  cache_type ? "DCACHE" : "ICACHE");
  99                 else if (thread_cache_size == 0)
 100                         /* Cache is off. No need to check for aliasing */
 101                         continue;
 102                 if (thread_cache_size / CACHE_ASSOCIATIVITY > PAGE_SIZE) {
 103                         pr_emerg("Cache aliasing detected in %s on Thread %d",
 104                                  cache_type ? "DCACHE" : "ICACHE", thread_id);
 105                         pr_warn("Total %s size: %u bytes",
 106                                 cache_type ? "DCACHE" : "ICACHE ",
 107                                 cache_type ? get_dcache_size()
 108                                 : get_icache_size());
 109                         pr_warn("Thread %s size: %d bytes",
 110                                 cache_type ? "CACHE" : "ICACHE",
 111                                 thread_cache_size);
 112                         pr_warn("Page Size: %lu bytes", PAGE_SIZE);
 113                 }
 114         }
 115 }
 116
 117 #else
 118
 119 void check_for_cache_aliasing(int thread_id)
 120 {
 121         return;
 122 }
 123
 124 #endif