arch/microblaze/include/asm/pci-bridge.h

   1 #ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H
   2 #define _ASM_MICROBLAZE_PCI_BRIDGE_H
   3 #ifdef __KERNEL__
   4 /*
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10 #include <linux/pci.h>
  11 #include <linux/list.h>
  12 #include <linux/ioport.h>
  13
  14 struct device_node;
  15
  16 enum {
  17         /* Force re-assigning all resources (ignore firmware
  18          * setup completely)
  19          */
  20         PCI_REASSIGN_ALL_RSRC   = 0x00000001,
  21
  22         /* Re-assign all bus numbers */
  23         PCI_REASSIGN_ALL_BUS    = 0x00000002,
  24
  25         /* Do not try to assign, just use existing setup */
  26         PCI_PROBE_ONLY          = 0x00000004,
  27
  28         /* Don't bother with ISA alignment unless the bridge has
  29          * ISA forwarding enabled
  30          */
  31         PCI_CAN_SKIP_ISA_ALIGN  = 0x00000008,
  32
  33         /* Enable domain numbers in /proc */
  34         PCI_ENABLE_PROC_DOMAINS = 0x00000010,
  35         /* ... except for domain 0 */
  36         PCI_COMPAT_DOMAIN_0             = 0x00000020,
  37 };
  38
  39 /*
  40  * Structure of a PCI controller (host bridge)
  41  */
  42 struct pci_controller {
  43         struct pci_bus *bus;
  44         char is_dynamic;
  45         struct device_node *dn;
  46         struct list_head list_node;
  47         struct device *parent;
  48
  49         int first_busno;
  50         int last_busno;
  51
  52         int self_busno;
  53
  54         void __iomem *io_base_virt;
  55         resource_size_t io_base_phys;
  56
  57         resource_size_t pci_io_size;
  58
  59         /* Some machines (PReP) have a non 1:1 mapping of
  60          * the PCI memory space in the CPU bus space
  61          */
  62         resource_size_t pci_mem_offset;
  63
  64         /* Some machines have a special region to forward the ISA
  65          * "memory" cycles such as VGA memory regions. Left to 0
  66          * if unsupported
  67          */
  68         resource_size_t isa_mem_phys;
  69         resource_size_t isa_mem_size;
  70
  71         struct pci_ops *ops;
  72         unsigned int __iomem *cfg_addr;
  73         void __iomem *cfg_data;
  74
  75         /*
  76          * Used for variants of PCI indirect handling and possible quirks:
  77          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  78          *  EXT_REG - provides access to PCI-e extended registers
  79          *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
  80          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  81          *   to determine which bus number to match on when generating type0
  82          *   config cycles
  83          *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  84          *   hanging if we don't have link and try to do config cycles to
  85          *   anything but the PHB.  Only allow talking to the PHB if this is
  86          *   set.
  87          *  BIG_ENDIAN - cfg_addr is a big endian register
  88          *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs
  89          *   on the PLB4.  Effectively disable MRM commands by setting this.
  90          */
  91 #define INDIRECT_TYPE_SET_CFG_TYPE              0x00000001
  92 #define INDIRECT_TYPE_EXT_REG           0x00000002
  93 #define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS      0x00000004
  94 #define INDIRECT_TYPE_NO_PCIE_LINK              0x00000008
  95 #define INDIRECT_TYPE_BIG_ENDIAN                0x00000010
  96 #define INDIRECT_TYPE_BROKEN_MRM                0x00000020
  97         u32 indirect_type;
  98
  99         /* Currently, we limit ourselves to 1 IO range and 3 mem
 100          * ranges since the common pci_bus structure can't handle more
 101          */
 102         struct resource io_resource;
 103         struct resource mem_resources[3];
 104         int global_number;      /* PCI domain number */
 105 };
 106
 107 #ifdef CONFIG_PCI
 108 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
 109 {
 110         return dev->dev.of_node;
 111 }
 112
 113 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
 114 {
 115         return bus->dev.of_node;
 116 }
 117
 118 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 119 {
 120         return bus->sysdata;
 121 }
 122
 123 static inline int isa_vaddr_is_ioport(void __iomem *address)
 124 {
 125         /* No specific ISA handling on ppc32 at this stage, it
 126          * all goes through PCI
 127          */
 128         return 0;
 129 }
 130 #endif /* CONFIG_PCI */
 131
 132 /* These are used for config access before all the PCI probing
 133    has been done. */
 134 extern int early_read_config_byte(struct pci_controller *hose, int bus,
 135                         int dev_fn, int where, u8 *val);
 136 extern int early_read_config_word(struct pci_controller *hose, int bus,
 137                         int dev_fn, int where, u16 *val);
 138 extern int early_read_config_dword(struct pci_controller *hose, int bus,
 139                         int dev_fn, int where, u32 *val);
 140 extern int early_write_config_byte(struct pci_controller *hose, int bus,
 141                         int dev_fn, int where, u8 val);
 142 extern int early_write_config_word(struct pci_controller *hose, int bus,
 143                         int dev_fn, int where, u16 val);
 144 extern int early_write_config_dword(struct pci_controller *hose, int bus,
 145                         int dev_fn, int where, u32 val);
 146
 147 extern int early_find_capability(struct pci_controller *hose, int bus,
 148                                  int dev_fn, int cap);
 149
 150 extern void setup_indirect_pci(struct pci_controller *hose,
 151                                resource_size_t cfg_addr,
 152                                resource_size_t cfg_data, u32 flags);
 153
 154 /* Get the PCI host controller for an OF device */
 155 extern struct pci_controller *pci_find_hose_for_OF_device(
 156                         struct device_node *node);
 157
 158 /* Fill up host controller resources from the OF node */
 159 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 160                         struct device_node *dev, int primary);
 161
 162 /* Allocate & free a PCI host bridge structure */
 163 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
 164 extern void pcibios_free_controller(struct pci_controller *phb);
 165 extern void pcibios_setup_phb_resources(struct pci_controller *hose);
 166
 167 #ifdef CONFIG_PCI
 168 extern unsigned int pci_flags;
 169
 170 static inline void pci_set_flags(int flags)
 171 {
 172         pci_flags = flags;
 173 }
 174
 175 static inline void pci_add_flags(int flags)
 176 {
 177         pci_flags |= flags;
 178 }
 179
 180 static inline int pci_has_flag(int flag)
 181 {
 182         return pci_flags & flag;
 183 }
 184
 185 extern struct list_head hose_list;
 186
 187 extern int pcibios_vaddr_is_ioport(void __iomem *address);
 188 #else
 189 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 190 {
 191         return 0;
 192 }
 193
 194 static inline void pci_set_flags(int flags) { }
 195 static inline void pci_add_flags(int flags) { }
 196 static inline int pci_has_flag(int flag)
 197 {
 198         return 0;
 199 }
 200 #endif  /* CONFIG_PCI */
 201
 202 #endif  /* __KERNEL__ */
 203 #endif  /* _ASM_MICROBLAZE_PCI_BRIDGE_H */