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microblaze: Support 4k/16k/64k pages
[deliverable/linux.git] / arch / microblaze / kernel / hw_exception_handler.S
1 /*
2 * Exception handling for Microblaze
3 *
4 * Rewriten interrupt handling
5 *
6 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
7 * Copyright (C) 2008-2009 PetaLogix
8 *
9 * uClinux customisation (C) 2005 John Williams
10 *
11 * MMU code derived from arch/ppc/kernel/head_4xx.S:
12 * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
13 * Initial PowerPC version.
14 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
15 * Rewritten for PReP
16 * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
17 * Low-level exception handers, MMU support, and rewrite.
18 * Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
19 * PowerPC 8xx modifications.
20 * Copyright (C) 1998-1999 TiVo, Inc.
21 * PowerPC 403GCX modifications.
22 * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
23 * PowerPC 403GCX/405GP modifications.
24 * Copyright 2000 MontaVista Software Inc.
25 * PPC405 modifications
26 * PowerPC 403GCX/405GP modifications.
27 * Author: MontaVista Software, Inc.
28 * frank_rowand@mvista.com or source@mvista.com
29 * debbie_chu@mvista.com
30 *
31 * Original code
32 * Copyright (C) 2004 Xilinx, Inc.
33 *
34 * This program is free software; you can redistribute it and/or modify it
35 * under the terms of the GNU General Public License version 2 as published
36 * by the Free Software Foundation.
37 */
38
39 /*
40 * Here are the handlers which don't require enabling translation
41 * and calling other kernel code thus we can keep their design very simple
42 * and do all processing in real mode. All what they need is a valid current
43 * (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
44 * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
45 * these registers are saved/restored
46 * The handlers which require translation are in entry.S --KAA
47 *
48 * Microblaze HW Exception Handler
49 * - Non self-modifying exception handler for the following exception conditions
50 * - Unalignment
51 * - Instruction bus error
52 * - Data bus error
53 * - Illegal instruction opcode
54 * - Divide-by-zero
55 *
56 * - Privileged instruction exception (MMU)
57 * - Data storage exception (MMU)
58 * - Instruction storage exception (MMU)
59 * - Data TLB miss exception (MMU)
60 * - Instruction TLB miss exception (MMU)
61 *
62 * Note we disable interrupts during exception handling, otherwise we will
63 * possibly get multiple re-entrancy if interrupt handles themselves cause
64 * exceptions. JW
65 */
66
67 #include <asm/exceptions.h>
68 #include <asm/unistd.h>
69 #include <asm/page.h>
70
71 #include <asm/entry.h>
72 #include <asm/current.h>
73 #include <linux/linkage.h>
74
75 #include <asm/mmu.h>
76 #include <asm/pgtable.h>
77 #include <asm/signal.h>
78 #include <asm/asm-offsets.h>
79
80 #undef DEBUG
81
82 /* Helpful Macros */
83 #define NUM_TO_REG(num) r ## num
84
85 #ifdef CONFIG_MMU
86 #define RESTORE_STATE \
87 lwi r5, r1, 0; \
88 mts rmsr, r5; \
89 nop; \
90 lwi r3, r1, PT_R3; \
91 lwi r4, r1, PT_R4; \
92 lwi r5, r1, PT_R5; \
93 lwi r6, r1, PT_R6; \
94 lwi r11, r1, PT_R11; \
95 lwi r31, r1, PT_R31; \
96 lwi r1, r1, PT_R1;
97 #endif /* CONFIG_MMU */
98
99 #define LWREG_NOP \
100 bri ex_handler_unhandled; \
101 nop;
102
103 #define SWREG_NOP \
104 bri ex_handler_unhandled; \
105 nop;
106
107 /* FIXME this is weird - for noMMU kernel is not possible to use brid
108 * instruction which can shorten executed time
109 */
110
111 /* r3 is the source */
112 #define R3_TO_LWREG_V(regnum) \
113 swi r3, r1, 4 * regnum; \
114 bri ex_handler_done;
115
116 /* r3 is the source */
117 #define R3_TO_LWREG(regnum) \
118 or NUM_TO_REG (regnum), r0, r3; \
119 bri ex_handler_done;
120
121 /* r3 is the target */
122 #define SWREG_TO_R3_V(regnum) \
123 lwi r3, r1, 4 * regnum; \
124 bri ex_sw_tail;
125
126 /* r3 is the target */
127 #define SWREG_TO_R3(regnum) \
128 or r3, r0, NUM_TO_REG (regnum); \
129 bri ex_sw_tail;
130
131 #ifdef CONFIG_MMU
132 #define R3_TO_LWREG_VM_V(regnum) \
133 brid ex_lw_end_vm; \
134 swi r3, r7, 4 * regnum;
135
136 #define R3_TO_LWREG_VM(regnum) \
137 brid ex_lw_end_vm; \
138 or NUM_TO_REG (regnum), r0, r3;
139
140 #define SWREG_TO_R3_VM_V(regnum) \
141 brid ex_sw_tail_vm; \
142 lwi r3, r7, 4 * regnum;
143
144 #define SWREG_TO_R3_VM(regnum) \
145 brid ex_sw_tail_vm; \
146 or r3, r0, NUM_TO_REG (regnum);
147
148 /* Shift right instruction depending on available configuration */
149 #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
150 #define BSRLI(rD, rA, imm) \
151 bsrli rD, rA, imm
152 #else
153 #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
154 /* Only the used shift constants defined here - add more if needed */
155 #define BSRLI2(rD, rA) \
156 srl rD, rA; /* << 1 */ \
157 srl rD, rD; /* << 2 */
158 #define BSRLI10(rD, rA) \
159 srl rD, rA; /* << 1 */ \
160 srl rD, rD; /* << 2 */ \
161 srl rD, rD; /* << 3 */ \
162 srl rD, rD; /* << 4 */ \
163 srl rD, rD; /* << 5 */ \
164 srl rD, rD; /* << 6 */ \
165 srl rD, rD; /* << 7 */ \
166 srl rD, rD; /* << 8 */ \
167 srl rD, rD; /* << 9 */ \
168 srl rD, rD /* << 10 */
169 #define BSRLI20(rD, rA) \
170 BSRLI10(rD, rA); \
171 BSRLI10(rD, rD)
172 #endif
173 #endif /* CONFIG_MMU */
174
175 .extern other_exception_handler /* Defined in exception.c */
176
177 /*
178 * hw_exception_handler - Handler for exceptions
179 *
180 * Exception handler notes:
181 * - Handles all exceptions
182 * - Does not handle unaligned exceptions during load into r17, r1, r0.
183 * - Does not handle unaligned exceptions during store from r17 (cannot be
184 * done) and r1 (slows down common case)
185 *
186 * Relevant register structures
187 *
188 * EAR - |----|----|----|----|----|----|----|----|
189 * - < ## 32 bit faulting address ## >
190 *
191 * ESR - |----|----|----|----|----| - | - |-----|-----|
192 * - W S REG EXC
193 *
194 *
195 * STACK FRAME STRUCTURE (for NO_MMU)
196 * ---------------------------------
197 *
198 * +-------------+ + 0
199 * | MSR |
200 * +-------------+ + 4
201 * | r1 |
202 * | . |
203 * | . |
204 * | . |
205 * | . |
206 * | r18 |
207 * +-------------+ + 76
208 * | . |
209 * | . |
210 *
211 * MMU kernel uses the same 'pt_pool_space' pointed space
212 * which is used for storing register values - noMMu style was, that values were
213 * stored in stack but in case of failure you lost information about register.
214 * Currently you can see register value in memory in specific place.
215 * In compare to with previous solution the speed should be the same.
216 *
217 * MMU exception handler has different handling compare to no MMU kernel.
218 * Exception handler use jump table for directing of what happen. For MMU kernel
219 * is this approach better because MMU relate exception are handled by asm code
220 * in this file. In compare to with MMU expect of unaligned exception
221 * is everything handled by C code.
222 */
223
224 /*
225 * every of these handlers is entered having R3/4/5/6/11/current saved on stack
226 * and clobbered so care should be taken to restore them if someone is going to
227 * return from exception
228 */
229
230 /* wrappers to restore state before coming to entry.S */
231 #ifdef CONFIG_MMU
232 .section .data
233 .align 4
234 pt_pool_space:
235 .space PT_SIZE
236
237 #ifdef DEBUG
238 /* Create space for exception counting. */
239 .section .data
240 .global exception_debug_table
241 .align 4
242 exception_debug_table:
243 /* Look at exception vector table. There is 32 exceptions * word size */
244 .space (32 * 4)
245 #endif /* DEBUG */
246
247 .section .rodata
248 .align 4
249 _MB_HW_ExceptionVectorTable:
250 /* 0 - Undefined */
251 .long TOPHYS(ex_handler_unhandled)
252 /* 1 - Unaligned data access exception */
253 .long TOPHYS(handle_unaligned_ex)
254 /* 2 - Illegal op-code exception */
255 .long TOPHYS(full_exception_trapw)
256 /* 3 - Instruction bus error exception */
257 .long TOPHYS(full_exception_trapw)
258 /* 4 - Data bus error exception */
259 .long TOPHYS(full_exception_trapw)
260 /* 5 - Divide by zero exception */
261 .long TOPHYS(full_exception_trapw)
262 /* 6 - Floating point unit exception */
263 .long TOPHYS(full_exception_trapw)
264 /* 7 - Privileged instruction exception */
265 .long TOPHYS(full_exception_trapw)
266 /* 8 - 15 - Undefined */
267 .long TOPHYS(ex_handler_unhandled)
268 .long TOPHYS(ex_handler_unhandled)
269 .long TOPHYS(ex_handler_unhandled)
270 .long TOPHYS(ex_handler_unhandled)
271 .long TOPHYS(ex_handler_unhandled)
272 .long TOPHYS(ex_handler_unhandled)
273 .long TOPHYS(ex_handler_unhandled)
274 .long TOPHYS(ex_handler_unhandled)
275 /* 16 - Data storage exception */
276 .long TOPHYS(handle_data_storage_exception)
277 /* 17 - Instruction storage exception */
278 .long TOPHYS(handle_instruction_storage_exception)
279 /* 18 - Data TLB miss exception */
280 .long TOPHYS(handle_data_tlb_miss_exception)
281 /* 19 - Instruction TLB miss exception */
282 .long TOPHYS(handle_instruction_tlb_miss_exception)
283 /* 20 - 31 - Undefined */
284 .long TOPHYS(ex_handler_unhandled)
285 .long TOPHYS(ex_handler_unhandled)
286 .long TOPHYS(ex_handler_unhandled)
287 .long TOPHYS(ex_handler_unhandled)
288 .long TOPHYS(ex_handler_unhandled)
289 .long TOPHYS(ex_handler_unhandled)
290 .long TOPHYS(ex_handler_unhandled)
291 .long TOPHYS(ex_handler_unhandled)
292 .long TOPHYS(ex_handler_unhandled)
293 .long TOPHYS(ex_handler_unhandled)
294 .long TOPHYS(ex_handler_unhandled)
295 .long TOPHYS(ex_handler_unhandled)
296 #endif
297
298 .global _hw_exception_handler
299 .section .text
300 .align 4
301 .ent _hw_exception_handler
302 _hw_exception_handler:
303 #ifndef CONFIG_MMU
304 addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
305 #else
306 swi r1, r0, TOPHYS(pt_pool_space + PT_R1); /* GET_SP */
307 /* Save date to kernel memory. Here is the problem
308 * when you came from user space */
309 ori r1, r0, TOPHYS(pt_pool_space);
310 #endif
311 swi r3, r1, PT_R3
312 swi r4, r1, PT_R4
313 swi r5, r1, PT_R5
314 swi r6, r1, PT_R6
315
316 #ifdef CONFIG_MMU
317 swi r11, r1, PT_R11
318 swi r31, r1, PT_R31
319 lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */
320 #endif
321
322 mfs r5, rmsr;
323 nop
324 swi r5, r1, 0;
325 mfs r4, resr
326 nop
327 mfs r3, rear;
328 nop
329
330 #ifndef CONFIG_MMU
331 andi r5, r4, 0x1000; /* Check ESR[DS] */
332 beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
333 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
334 nop
335 not_in_delay_slot:
336 swi r17, r1, PT_R17
337 #endif
338
339 andi r5, r4, 0x1F; /* Extract ESR[EXC] */
340
341 #ifdef CONFIG_MMU
342 /* Calculate exception vector offset = r5 << 2 */
343 addk r6, r5, r5; /* << 1 */
344 addk r6, r6, r6; /* << 2 */
345
346 #ifdef DEBUG
347 /* counting which exception happen */
348 lwi r5, r0, TOPHYS(exception_debug_table)
349 addi r5, r5, 1
350 swi r5, r0, TOPHYS(exception_debug_table)
351 lwi r5, r6, TOPHYS(exception_debug_table)
352 addi r5, r5, 1
353 swi r5, r6, TOPHYS(exception_debug_table)
354 #endif
355 /* end */
356 /* Load the HW Exception vector */
357 lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
358 bra r6
359
360 full_exception_trapw:
361 RESTORE_STATE
362 bri full_exception_trap
363 #else
364 /* Exceptions enabled here. This will allow nested exceptions */
365 mfs r6, rmsr;
366 nop
367 swi r6, r1, 0; /* RMSR_OFFSET */
368 ori r6, r6, 0x100; /* Turn ON the EE bit */
369 andi r6, r6, ~2; /* Disable interrupts */
370 mts rmsr, r6;
371 nop
372
373 xori r6, r5, 1; /* 00001 = Unaligned Exception */
374 /* Jump to unalignment exception handler */
375 beqi r6, handle_unaligned_ex;
376
377 handle_other_ex: /* Handle Other exceptions here */
378 /* Save other volatiles before we make procedure calls below */
379 swi r7, r1, PT_R7
380 swi r8, r1, PT_R8
381 swi r9, r1, PT_R9
382 swi r10, r1, PT_R10
383 swi r11, r1, PT_R11
384 swi r12, r1, PT_R12
385 swi r14, r1, PT_R14
386 swi r15, r1, PT_R15
387 swi r18, r1, PT_R18
388
389 or r5, r1, r0
390 andi r6, r4, 0x1F; /* Load ESR[EC] */
391 lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
392 swi r7, r1, PT_MODE
393 mfs r7, rfsr
394 nop
395 addk r8, r17, r0; /* Load exception address */
396 bralid r15, full_exception; /* Branch to the handler */
397 nop;
398 mts rfsr, r0; /* Clear sticky fsr */
399 nop
400
401 /*
402 * Trigger execution of the signal handler by enabling
403 * interrupts and calling an invalid syscall.
404 */
405 mfs r5, rmsr;
406 nop
407 ori r5, r5, 2;
408 mts rmsr, r5; /* enable interrupt */
409 nop
410 addi r12, r0, __NR_syscalls;
411 brki r14, 0x08;
412 mfs r5, rmsr; /* disable interrupt */
413 nop
414 andi r5, r5, ~2;
415 mts rmsr, r5;
416 nop
417
418 lwi r7, r1, PT_R7
419 lwi r8, r1, PT_R8
420 lwi r9, r1, PT_R9
421 lwi r10, r1, PT_R10
422 lwi r11, r1, PT_R11
423 lwi r12, r1, PT_R12
424 lwi r14, r1, PT_R14
425 lwi r15, r1, PT_R15
426 lwi r18, r1, PT_R18
427
428 bri ex_handler_done; /* Complete exception handling */
429 #endif
430
431 /* 0x01 - Unaligned data access exception
432 * This occurs when a word access is not aligned on a word boundary,
433 * or when a 16-bit access is not aligned on a 16-bit boundary.
434 * This handler perform the access, and returns, except for MMU when
435 * the unaligned address is last on a 4k page or the physical address is
436 * not found in the page table, in which case unaligned_data_trap is called.
437 */
438 handle_unaligned_ex:
439 /* Working registers already saved: R3, R4, R5, R6
440 * R4 = ESR
441 * R3 = EAR
442 */
443 #ifdef CONFIG_MMU
444 andi r6, r4, 0x1000 /* Check ESR[DS] */
445 beqi r6, _no_delayslot /* Branch if ESR[DS] not set */
446 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
447 nop
448 _no_delayslot:
449 /* jump to high level unaligned handler */
450 RESTORE_STATE;
451 bri unaligned_data_trap
452 #endif
453 andi r6, r4, 0x3E0; /* Mask and extract the register operand */
454 srl r6, r6; /* r6 >> 5 */
455 srl r6, r6;
456 srl r6, r6;
457 srl r6, r6;
458 srl r6, r6;
459 /* Store the register operand in a temporary location */
460 sbi r6, r0, TOPHYS(ex_reg_op);
461
462 andi r6, r4, 0x400; /* Extract ESR[S] */
463 bnei r6, ex_sw;
464 ex_lw:
465 andi r6, r4, 0x800; /* Extract ESR[W] */
466 beqi r6, ex_lhw;
467 lbui r5, r3, 0; /* Exception address in r3 */
468 /* Load a word, byte-by-byte from destination address
469 and save it in tmp space */
470 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
471 lbui r5, r3, 1;
472 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
473 lbui r5, r3, 2;
474 sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
475 lbui r5, r3, 3;
476 sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
477 /* Get the destination register value into r4 */
478 lwi r4, r0, TOPHYS(ex_tmp_data_loc_0);
479 bri ex_lw_tail;
480 ex_lhw:
481 lbui r5, r3, 0; /* Exception address in r3 */
482 /* Load a half-word, byte-by-byte from destination
483 address and save it in tmp space */
484 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
485 lbui r5, r3, 1;
486 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
487 /* Get the destination register value into r4 */
488 lhui r4, r0, TOPHYS(ex_tmp_data_loc_0);
489 ex_lw_tail:
490 /* Get the destination register number into r5 */
491 lbui r5, r0, TOPHYS(ex_reg_op);
492 /* Form load_word jump table offset (lw_table + (8 * regnum)) */
493 addik r6, r0, TOPHYS(lw_table);
494 addk r5, r5, r5;
495 addk r5, r5, r5;
496 addk r5, r5, r5;
497 addk r5, r5, r6;
498 bra r5;
499 ex_lw_end: /* Exception handling of load word, ends */
500 ex_sw:
501 /* Get the destination register number into r5 */
502 lbui r5, r0, TOPHYS(ex_reg_op);
503 /* Form store_word jump table offset (sw_table + (8 * regnum)) */
504 addik r6, r0, TOPHYS(sw_table);
505 add r5, r5, r5;
506 add r5, r5, r5;
507 add r5, r5, r5;
508 add r5, r5, r6;
509 bra r5;
510 ex_sw_tail:
511 mfs r6, resr;
512 nop
513 andi r6, r6, 0x800; /* Extract ESR[W] */
514 beqi r6, ex_shw;
515 /* Get the word - delay slot */
516 swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
517 /* Store the word, byte-by-byte into destination address */
518 lbui r4, r0, TOPHYS(ex_tmp_data_loc_0);
519 sbi r4, r3, 0;
520 lbui r4, r0, TOPHYS(ex_tmp_data_loc_1);
521 sbi r4, r3, 1;
522 lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
523 sbi r4, r3, 2;
524 lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
525 sbi r4, r3, 3;
526 bri ex_handler_done;
527
528 ex_shw:
529 /* Store the lower half-word, byte-by-byte into destination address */
530 swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
531 lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
532 sbi r4, r3, 0;
533 lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
534 sbi r4, r3, 1;
535 ex_sw_end: /* Exception handling of store word, ends. */
536
537 ex_handler_done:
538 #ifndef CONFIG_MMU
539 lwi r5, r1, 0 /* RMSR */
540 mts rmsr, r5
541 nop
542 lwi r3, r1, PT_R3
543 lwi r4, r1, PT_R4
544 lwi r5, r1, PT_R5
545 lwi r6, r1, PT_R6
546 lwi r17, r1, PT_R17
547
548 rted r17, 0
549 addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
550 #else
551 RESTORE_STATE;
552 rted r17, 0
553 nop
554 #endif
555
556 #ifdef CONFIG_MMU
557 /* Exception vector entry code. This code runs with address translation
558 * turned off (i.e. using physical addresses). */
559
560 /* Exception vectors. */
561
562 /* 0x10 - Data Storage Exception
563 * This happens for just a few reasons. U0 set (but we don't do that),
564 * or zone protection fault (user violation, write to protected page).
565 * If this is just an update of modified status, we do that quickly
566 * and exit. Otherwise, we call heavyweight functions to do the work.
567 */
568 handle_data_storage_exception:
569 /* Working registers already saved: R3, R4, R5, R6
570 * R3 = ESR
571 */
572 mfs r11, rpid
573 nop
574 /* If we are faulting a kernel address, we have to use the
575 * kernel page tables.
576 */
577 ori r5, r0, CONFIG_KERNEL_START
578 cmpu r5, r3, r5
579 bgti r5, ex3
580 /* First, check if it was a zone fault (which means a user
581 * tried to access a kernel or read-protected page - always
582 * a SEGV). All other faults here must be stores, so no
583 * need to check ESR_S as well. */
584 andi r4, r4, 0x800 /* ESR_Z - zone protection */
585 bnei r4, ex2
586
587 ori r4, r0, swapper_pg_dir
588 mts rpid, r0 /* TLB will have 0 TID */
589 nop
590 bri ex4
591
592 /* Get the PGD for the current thread. */
593 ex3:
594 /* First, check if it was a zone fault (which means a user
595 * tried to access a kernel or read-protected page - always
596 * a SEGV). All other faults here must be stores, so no
597 * need to check ESR_S as well. */
598 andi r4, r4, 0x800 /* ESR_Z */
599 bnei r4, ex2
600 /* get current task address */
601 addi r4 ,CURRENT_TASK, TOPHYS(0);
602 lwi r4, r4, TASK_THREAD+PGDIR
603 ex4:
604 tophys(r4,r4)
605 /* Create L1 (pgdir/pmd) address */
606 BSRLI(r5,r3, PGDIR_SHIFT - 2)
607 andi r5, r5, PAGE_SIZE - 4
608 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
609 or r4, r4, r5
610 lwi r4, r4, 0 /* Get L1 entry */
611 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
612 beqi r5, ex2 /* Bail if no table */
613
614 tophys(r5,r5)
615 BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
616 andi r6, r6, PAGE_SIZE - 4
617 andi r5, r5, PAGE_MASK + 0x3
618 or r5, r5, r6
619 lwi r4, r5, 0 /* Get Linux PTE */
620
621 andi r6, r4, _PAGE_RW /* Is it writeable? */
622 beqi r6, ex2 /* Bail if not */
623
624 /* Update 'changed' */
625 ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
626 swi r4, r5, 0 /* Update Linux page table */
627
628 /* Most of the Linux PTE is ready to load into the TLB LO.
629 * We set ZSEL, where only the LS-bit determines user access.
630 * We set execute, because we don't have the granularity to
631 * properly set this at the page level (Linux problem).
632 * If shared is set, we cause a zero PID->TID load.
633 * Many of these bits are software only. Bits we don't set
634 * here we (properly should) assume have the appropriate value.
635 */
636 /* Ignore memory coherent, just LSB on ZSEL is used + EX/WR */
637 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
638 TLB_ZSEL(1) | TLB_ATTR_MASK
639 ori r4, r4, _PAGE_HWEXEC /* make it executable */
640
641 /* find the TLB index that caused the fault. It has to be here*/
642 mts rtlbsx, r3
643 nop
644 mfs r5, rtlbx /* DEBUG: TBD */
645 nop
646 mts rtlblo, r4 /* Load TLB LO */
647 nop
648 /* Will sync shadow TLBs */
649
650 /* Done...restore registers and get out of here. */
651 mts rpid, r11
652 nop
653 bri 4
654
655 RESTORE_STATE;
656 rted r17, 0
657 nop
658 ex2:
659 /* The bailout. Restore registers to pre-exception conditions
660 * and call the heavyweights to help us out. */
661 mts rpid, r11
662 nop
663 bri 4
664 RESTORE_STATE;
665 bri page_fault_data_trap
666
667
668 /* 0x11 - Instruction Storage Exception
669 * This is caused by a fetch from non-execute or guarded pages. */
670 handle_instruction_storage_exception:
671 /* Working registers already saved: R3, R4, R5, R6
672 * R3 = ESR
673 */
674
675 RESTORE_STATE;
676 bri page_fault_instr_trap
677
678 /* 0x12 - Data TLB Miss Exception
679 * As the name implies, translation is not in the MMU, so search the
680 * page tables and fix it. The only purpose of this function is to
681 * load TLB entries from the page table if they exist.
682 */
683 handle_data_tlb_miss_exception:
684 /* Working registers already saved: R3, R4, R5, R6
685 * R3 = EAR, R4 = ESR
686 */
687 mfs r11, rpid
688 nop
689
690 /* If we are faulting a kernel address, we have to use the
691 * kernel page tables. */
692 ori r6, r0, CONFIG_KERNEL_START
693 cmpu r4, r3, r6
694 bgti r4, ex5
695 ori r4, r0, swapper_pg_dir
696 mts rpid, r0 /* TLB will have 0 TID */
697 nop
698 bri ex6
699
700 /* Get the PGD for the current thread. */
701 ex5:
702 /* get current task address */
703 addi r4 ,CURRENT_TASK, TOPHYS(0);
704 lwi r4, r4, TASK_THREAD+PGDIR
705 ex6:
706 tophys(r4,r4)
707 /* Create L1 (pgdir/pmd) address */
708 BSRLI(r5,r3, PGDIR_SHIFT - 2)
709 andi r5, r5, PAGE_SIZE - 4
710 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
711 or r4, r4, r5
712 lwi r4, r4, 0 /* Get L1 entry */
713 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
714 beqi r5, ex7 /* Bail if no table */
715
716 tophys(r5,r5)
717 BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
718 andi r6, r6, PAGE_SIZE - 4
719 andi r5, r5, PAGE_MASK + 0x3
720 or r5, r5, r6
721 lwi r4, r5, 0 /* Get Linux PTE */
722
723 andi r6, r4, _PAGE_PRESENT
724 beqi r6, ex7
725
726 ori r4, r4, _PAGE_ACCESSED
727 swi r4, r5, 0
728
729 /* Most of the Linux PTE is ready to load into the TLB LO.
730 * We set ZSEL, where only the LS-bit determines user access.
731 * We set execute, because we don't have the granularity to
732 * properly set this at the page level (Linux problem).
733 * If shared is set, we cause a zero PID->TID load.
734 * Many of these bits are software only. Bits we don't set
735 * here we (properly should) assume have the appropriate value.
736 */
737 brid finish_tlb_load
738 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
739 TLB_ZSEL(1) | TLB_ATTR_MASK
740 ex7:
741 /* The bailout. Restore registers to pre-exception conditions
742 * and call the heavyweights to help us out.
743 */
744 mts rpid, r11
745 nop
746 bri 4
747 RESTORE_STATE;
748 bri page_fault_data_trap
749
750 /* 0x13 - Instruction TLB Miss Exception
751 * Nearly the same as above, except we get our information from
752 * different registers and bailout to a different point.
753 */
754 handle_instruction_tlb_miss_exception:
755 /* Working registers already saved: R3, R4, R5, R6
756 * R3 = ESR
757 */
758 mfs r11, rpid
759 nop
760
761 /* If we are faulting a kernel address, we have to use the
762 * kernel page tables.
763 */
764 ori r4, r0, CONFIG_KERNEL_START
765 cmpu r4, r3, r4
766 bgti r4, ex8
767 ori r4, r0, swapper_pg_dir
768 mts rpid, r0 /* TLB will have 0 TID */
769 nop
770 bri ex9
771
772 /* Get the PGD for the current thread. */
773 ex8:
774 /* get current task address */
775 addi r4 ,CURRENT_TASK, TOPHYS(0);
776 lwi r4, r4, TASK_THREAD+PGDIR
777 ex9:
778 tophys(r4,r4)
779 /* Create L1 (pgdir/pmd) address */
780 BSRLI(r5,r3, PGDIR_SHIFT - 2)
781 andi r5, r5, PAGE_SIZE - 4
782 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
783 or r4, r4, r5
784 lwi r4, r4, 0 /* Get L1 entry */
785 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
786 beqi r5, ex10 /* Bail if no table */
787
788 tophys(r5,r5)
789 BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
790 andi r6, r6, PAGE_SIZE - 4
791 andi r5, r5, PAGE_MASK + 0x3
792 or r5, r5, r6
793 lwi r4, r5, 0 /* Get Linux PTE */
794
795 andi r6, r4, _PAGE_PRESENT
796 beqi r6, ex10
797
798 ori r4, r4, _PAGE_ACCESSED
799 swi r4, r5, 0
800
801 /* Most of the Linux PTE is ready to load into the TLB LO.
802 * We set ZSEL, where only the LS-bit determines user access.
803 * We set execute, because we don't have the granularity to
804 * properly set this at the page level (Linux problem).
805 * If shared is set, we cause a zero PID->TID load.
806 * Many of these bits are software only. Bits we don't set
807 * here we (properly should) assume have the appropriate value.
808 */
809 brid finish_tlb_load
810 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
811 TLB_ZSEL(1) | TLB_ATTR_MASK
812 ex10:
813 /* The bailout. Restore registers to pre-exception conditions
814 * and call the heavyweights to help us out.
815 */
816 mts rpid, r11
817 nop
818 bri 4
819 RESTORE_STATE;
820 bri page_fault_instr_trap
821
822 /* Both the instruction and data TLB miss get to this point to load the TLB.
823 * r3 - EA of fault
824 * r4 - TLB LO (info from Linux PTE)
825 * r5, r6 - available to use
826 * PID - loaded with proper value when we get here
827 * Upon exit, we reload everything and RFI.
828 * A common place to load the TLB.
829 */
830 .section .data
831 .align 4
832 .global tlb_skip
833 tlb_skip:
834 .long MICROBLAZE_TLB_SKIP
835 tlb_index:
836 /* MS: storing last used tlb index */
837 .long MICROBLAZE_TLB_SIZE/2
838 .previous
839 finish_tlb_load:
840 /* MS: load the last used TLB index. */
841 lwi r5, r0, TOPHYS(tlb_index)
842 addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
843
844 /* MS: FIXME this is potential fault, because this is mask not count */
845 andi r5, r5, MICROBLAZE_TLB_SIZE - 1
846 ori r6, r0, 1
847 cmp r31, r5, r6
848 blti r31, ex12
849 lwi r5, r0, TOPHYS(tlb_skip)
850 ex12:
851 /* MS: save back current TLB index */
852 swi r5, r0, TOPHYS(tlb_index)
853
854 ori r4, r4, _PAGE_HWEXEC /* make it executable */
855 mts rtlbx, r5 /* MS: save current TLB */
856 nop
857 mts rtlblo, r4 /* MS: save to TLB LO */
858 nop
859
860 /* Create EPN. This is the faulting address plus a static
861 * set of bits. These are size, valid, E, U0, and ensure
862 * bits 20 and 21 are zero.
863 */
864 andi r3, r3, PAGE_MASK
865 #ifdef CONFIG_MICROBLAZE_64K_PAGES
866 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_64K)
867 #elif CONFIG_MICROBLAZE_16K_PAGES
868 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_16K)
869 #else
870 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_4K)
871 #endif
872 mts rtlbhi, r3 /* Load TLB HI */
873 nop
874
875 /* Done...restore registers and get out of here. */
876 mts rpid, r11
877 nop
878 bri 4
879 RESTORE_STATE;
880 rted r17, 0
881 nop
882
883 /* extern void giveup_fpu(struct task_struct *prev)
884 *
885 * The MicroBlaze processor may have an FPU, so this should not just
886 * return: TBD.
887 */
888 .globl giveup_fpu;
889 .align 4;
890 giveup_fpu:
891 bralid r15,0 /* TBD */
892 nop
893
894 /* At present, this routine just hangs. - extern void abort(void) */
895 .globl abort;
896 .align 4;
897 abort:
898 br r0
899
900 .globl set_context;
901 .align 4;
902 set_context:
903 mts rpid, r5 /* Shadow TLBs are automatically */
904 nop
905 bri 4 /* flushed by changing PID */
906 rtsd r15,8
907 nop
908
909 #endif
910 .end _hw_exception_handler
911
912 #ifdef CONFIG_MMU
913 /* Unaligned data access exception last on a 4k page for MMU.
914 * When this is called, we are in virtual mode with exceptions enabled
915 * and registers 1-13,15,17,18 saved.
916 *
917 * R3 = ESR
918 * R4 = EAR
919 * R7 = pointer to saved registers (struct pt_regs *regs)
920 *
921 * This handler perform the access, and returns via ret_from_exc.
922 */
923 .global _unaligned_data_exception
924 .ent _unaligned_data_exception
925 _unaligned_data_exception:
926 andi r8, r3, 0x3E0; /* Mask and extract the register operand */
927 BSRLI(r8,r8,2); /* r8 >> 2 = register operand * 8 */
928 andi r6, r3, 0x400; /* Extract ESR[S] */
929 bneid r6, ex_sw_vm;
930 andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
931 ex_lw_vm:
932 beqid r6, ex_lhw_vm;
933 load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
934 /* Load a word, byte-by-byte from destination address and save it in tmp space*/
935 addik r6, r0, ex_tmp_data_loc_0;
936 sbi r5, r6, 0;
937 load2: lbui r5, r4, 1;
938 sbi r5, r6, 1;
939 load3: lbui r5, r4, 2;
940 sbi r5, r6, 2;
941 load4: lbui r5, r4, 3;
942 sbi r5, r6, 3;
943 brid ex_lw_tail_vm;
944 /* Get the destination register value into r3 - delay slot */
945 lwi r3, r6, 0;
946 ex_lhw_vm:
947 /* Load a half-word, byte-by-byte from destination address and
948 * save it in tmp space */
949 addik r6, r0, ex_tmp_data_loc_0;
950 sbi r5, r6, 0;
951 load5: lbui r5, r4, 1;
952 sbi r5, r6, 1;
953 lhui r3, r6, 0; /* Get the destination register value into r3 */
954 ex_lw_tail_vm:
955 /* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */
956 addik r5, r8, lw_table_vm;
957 bra r5;
958 ex_lw_end_vm: /* Exception handling of load word, ends */
959 brai ret_from_exc;
960 ex_sw_vm:
961 /* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */
962 addik r5, r8, sw_table_vm;
963 bra r5;
964 ex_sw_tail_vm:
965 addik r5, r0, ex_tmp_data_loc_0;
966 beqid r6, ex_shw_vm;
967 swi r3, r5, 0; /* Get the word - delay slot */
968 /* Store the word, byte-by-byte into destination address */
969 lbui r3, r5, 0;
970 store1: sbi r3, r4, 0;
971 lbui r3, r5, 1;
972 store2: sbi r3, r4, 1;
973 lbui r3, r5, 2;
974 store3: sbi r3, r4, 2;
975 lbui r3, r5, 3;
976 brid ret_from_exc;
977 store4: sbi r3, r4, 3; /* Delay slot */
978 ex_shw_vm:
979 /* Store the lower half-word, byte-by-byte into destination address */
980 #ifdef __MICROBLAZEEL__
981 lbui r3, r5, 0;
982 store5: sbi r3, r4, 0;
983 lbui r3, r5, 1;
984 brid ret_from_exc;
985 store6: sbi r3, r4, 1; /* Delay slot */
986 #else
987 lbui r3, r5, 2;
988 store5: sbi r3, r4, 0;
989 lbui r3, r5, 3;
990 brid ret_from_exc;
991 store6: sbi r3, r4, 1; /* Delay slot */
992 #endif
993
994 ex_sw_end_vm: /* Exception handling of store word, ends. */
995
996 /* We have to prevent cases that get/put_user macros get unaligned pointer
997 * to bad page area. We have to find out which origin instruction caused it
998 * and called fixup for that origin instruction not instruction in unaligned
999 * handler */
1000 ex_unaligned_fixup:
1001 ori r5, r7, 0 /* setup pointer to pt_regs */
1002 lwi r6, r7, PT_PC; /* faulting address is one instruction above */
1003 addik r6, r6, -4 /* for finding proper fixup */
1004 swi r6, r7, PT_PC; /* a save back it to PT_PC */
1005 addik r7, r0, SIGSEGV
1006 /* call bad_page_fault for finding aligned fixup, fixup address is saved
1007 * in PT_PC which is used as return address from exception */
1008 addik r15, r0, ret_from_exc-8 /* setup return address */
1009 brid bad_page_fault
1010 nop
1011
1012 /* We prevent all load/store because it could failed any attempt to access */
1013 .section __ex_table,"a";
1014 .word load1,ex_unaligned_fixup;
1015 .word load2,ex_unaligned_fixup;
1016 .word load3,ex_unaligned_fixup;
1017 .word load4,ex_unaligned_fixup;
1018 .word load5,ex_unaligned_fixup;
1019 .word store1,ex_unaligned_fixup;
1020 .word store2,ex_unaligned_fixup;
1021 .word store3,ex_unaligned_fixup;
1022 .word store4,ex_unaligned_fixup;
1023 .word store5,ex_unaligned_fixup;
1024 .word store6,ex_unaligned_fixup;
1025 .previous;
1026 .end _unaligned_data_exception
1027 #endif /* CONFIG_MMU */
1028
1029 .global ex_handler_unhandled
1030 ex_handler_unhandled:
1031 /* FIXME add handle function for unhandled exception - dump register */
1032 bri 0
1033
1034 /*
1035 * hw_exception_handler Jump Table
1036 * - Contains code snippets for each register that caused the unalign exception
1037 * - Hence exception handler is NOT self-modifying
1038 * - Separate table for load exceptions and store exceptions.
1039 * - Each table is of size: (8 * 32) = 256 bytes
1040 */
1041
1042 .section .text
1043 .align 4
1044 lw_table:
1045 lw_r0: R3_TO_LWREG (0);
1046 lw_r1: LWREG_NOP;
1047 lw_r2: R3_TO_LWREG (2);
1048 lw_r3: R3_TO_LWREG_V (3);
1049 lw_r4: R3_TO_LWREG_V (4);
1050 lw_r5: R3_TO_LWREG_V (5);
1051 lw_r6: R3_TO_LWREG_V (6);
1052 lw_r7: R3_TO_LWREG (7);
1053 lw_r8: R3_TO_LWREG (8);
1054 lw_r9: R3_TO_LWREG (9);
1055 lw_r10: R3_TO_LWREG (10);
1056 lw_r11: R3_TO_LWREG (11);
1057 lw_r12: R3_TO_LWREG (12);
1058 lw_r13: R3_TO_LWREG (13);
1059 lw_r14: R3_TO_LWREG (14);
1060 lw_r15: R3_TO_LWREG (15);
1061 lw_r16: R3_TO_LWREG (16);
1062 lw_r17: LWREG_NOP;
1063 lw_r18: R3_TO_LWREG (18);
1064 lw_r19: R3_TO_LWREG (19);
1065 lw_r20: R3_TO_LWREG (20);
1066 lw_r21: R3_TO_LWREG (21);
1067 lw_r22: R3_TO_LWREG (22);
1068 lw_r23: R3_TO_LWREG (23);
1069 lw_r24: R3_TO_LWREG (24);
1070 lw_r25: R3_TO_LWREG (25);
1071 lw_r26: R3_TO_LWREG (26);
1072 lw_r27: R3_TO_LWREG (27);
1073 lw_r28: R3_TO_LWREG (28);
1074 lw_r29: R3_TO_LWREG (29);
1075 lw_r30: R3_TO_LWREG (30);
1076 #ifdef CONFIG_MMU
1077 lw_r31: R3_TO_LWREG_V (31);
1078 #else
1079 lw_r31: R3_TO_LWREG (31);
1080 #endif
1081
1082 sw_table:
1083 sw_r0: SWREG_TO_R3 (0);
1084 sw_r1: SWREG_NOP;
1085 sw_r2: SWREG_TO_R3 (2);
1086 sw_r3: SWREG_TO_R3_V (3);
1087 sw_r4: SWREG_TO_R3_V (4);
1088 sw_r5: SWREG_TO_R3_V (5);
1089 sw_r6: SWREG_TO_R3_V (6);
1090 sw_r7: SWREG_TO_R3 (7);
1091 sw_r8: SWREG_TO_R3 (8);
1092 sw_r9: SWREG_TO_R3 (9);
1093 sw_r10: SWREG_TO_R3 (10);
1094 sw_r11: SWREG_TO_R3 (11);
1095 sw_r12: SWREG_TO_R3 (12);
1096 sw_r13: SWREG_TO_R3 (13);
1097 sw_r14: SWREG_TO_R3 (14);
1098 sw_r15: SWREG_TO_R3 (15);
1099 sw_r16: SWREG_TO_R3 (16);
1100 sw_r17: SWREG_NOP;
1101 sw_r18: SWREG_TO_R3 (18);
1102 sw_r19: SWREG_TO_R3 (19);
1103 sw_r20: SWREG_TO_R3 (20);
1104 sw_r21: SWREG_TO_R3 (21);
1105 sw_r22: SWREG_TO_R3 (22);
1106 sw_r23: SWREG_TO_R3 (23);
1107 sw_r24: SWREG_TO_R3 (24);
1108 sw_r25: SWREG_TO_R3 (25);
1109 sw_r26: SWREG_TO_R3 (26);
1110 sw_r27: SWREG_TO_R3 (27);
1111 sw_r28: SWREG_TO_R3 (28);
1112 sw_r29: SWREG_TO_R3 (29);
1113 sw_r30: SWREG_TO_R3 (30);
1114 #ifdef CONFIG_MMU
1115 sw_r31: SWREG_TO_R3_V (31);
1116 #else
1117 sw_r31: SWREG_TO_R3 (31);
1118 #endif
1119
1120 #ifdef CONFIG_MMU
1121 lw_table_vm:
1122 lw_r0_vm: R3_TO_LWREG_VM (0);
1123 lw_r1_vm: R3_TO_LWREG_VM_V (1);
1124 lw_r2_vm: R3_TO_LWREG_VM_V (2);
1125 lw_r3_vm: R3_TO_LWREG_VM_V (3);
1126 lw_r4_vm: R3_TO_LWREG_VM_V (4);
1127 lw_r5_vm: R3_TO_LWREG_VM_V (5);
1128 lw_r6_vm: R3_TO_LWREG_VM_V (6);
1129 lw_r7_vm: R3_TO_LWREG_VM_V (7);
1130 lw_r8_vm: R3_TO_LWREG_VM_V (8);
1131 lw_r9_vm: R3_TO_LWREG_VM_V (9);
1132 lw_r10_vm: R3_TO_LWREG_VM_V (10);
1133 lw_r11_vm: R3_TO_LWREG_VM_V (11);
1134 lw_r12_vm: R3_TO_LWREG_VM_V (12);
1135 lw_r13_vm: R3_TO_LWREG_VM_V (13);
1136 lw_r14_vm: R3_TO_LWREG_VM_V (14);
1137 lw_r15_vm: R3_TO_LWREG_VM_V (15);
1138 lw_r16_vm: R3_TO_LWREG_VM_V (16);
1139 lw_r17_vm: R3_TO_LWREG_VM_V (17);
1140 lw_r18_vm: R3_TO_LWREG_VM_V (18);
1141 lw_r19_vm: R3_TO_LWREG_VM_V (19);
1142 lw_r20_vm: R3_TO_LWREG_VM_V (20);
1143 lw_r21_vm: R3_TO_LWREG_VM_V (21);
1144 lw_r22_vm: R3_TO_LWREG_VM_V (22);
1145 lw_r23_vm: R3_TO_LWREG_VM_V (23);
1146 lw_r24_vm: R3_TO_LWREG_VM_V (24);
1147 lw_r25_vm: R3_TO_LWREG_VM_V (25);
1148 lw_r26_vm: R3_TO_LWREG_VM_V (26);
1149 lw_r27_vm: R3_TO_LWREG_VM_V (27);
1150 lw_r28_vm: R3_TO_LWREG_VM_V (28);
1151 lw_r29_vm: R3_TO_LWREG_VM_V (29);
1152 lw_r30_vm: R3_TO_LWREG_VM_V (30);
1153 lw_r31_vm: R3_TO_LWREG_VM_V (31);
1154
1155 sw_table_vm:
1156 sw_r0_vm: SWREG_TO_R3_VM (0);
1157 sw_r1_vm: SWREG_TO_R3_VM_V (1);
1158 sw_r2_vm: SWREG_TO_R3_VM_V (2);
1159 sw_r3_vm: SWREG_TO_R3_VM_V (3);
1160 sw_r4_vm: SWREG_TO_R3_VM_V (4);
1161 sw_r5_vm: SWREG_TO_R3_VM_V (5);
1162 sw_r6_vm: SWREG_TO_R3_VM_V (6);
1163 sw_r7_vm: SWREG_TO_R3_VM_V (7);
1164 sw_r8_vm: SWREG_TO_R3_VM_V (8);
1165 sw_r9_vm: SWREG_TO_R3_VM_V (9);
1166 sw_r10_vm: SWREG_TO_R3_VM_V (10);
1167 sw_r11_vm: SWREG_TO_R3_VM_V (11);
1168 sw_r12_vm: SWREG_TO_R3_VM_V (12);
1169 sw_r13_vm: SWREG_TO_R3_VM_V (13);
1170 sw_r14_vm: SWREG_TO_R3_VM_V (14);
1171 sw_r15_vm: SWREG_TO_R3_VM_V (15);
1172 sw_r16_vm: SWREG_TO_R3_VM_V (16);
1173 sw_r17_vm: SWREG_TO_R3_VM_V (17);
1174 sw_r18_vm: SWREG_TO_R3_VM_V (18);
1175 sw_r19_vm: SWREG_TO_R3_VM_V (19);
1176 sw_r20_vm: SWREG_TO_R3_VM_V (20);
1177 sw_r21_vm: SWREG_TO_R3_VM_V (21);
1178 sw_r22_vm: SWREG_TO_R3_VM_V (22);
1179 sw_r23_vm: SWREG_TO_R3_VM_V (23);
1180 sw_r24_vm: SWREG_TO_R3_VM_V (24);
1181 sw_r25_vm: SWREG_TO_R3_VM_V (25);
1182 sw_r26_vm: SWREG_TO_R3_VM_V (26);
1183 sw_r27_vm: SWREG_TO_R3_VM_V (27);
1184 sw_r28_vm: SWREG_TO_R3_VM_V (28);
1185 sw_r29_vm: SWREG_TO_R3_VM_V (29);
1186 sw_r30_vm: SWREG_TO_R3_VM_V (30);
1187 sw_r31_vm: SWREG_TO_R3_VM_V (31);
1188 #endif /* CONFIG_MMU */
1189
1190 /* Temporary data structures used in the handler */
1191 .section .data
1192 .align 4
1193 ex_tmp_data_loc_0:
1194 .byte 0
1195 ex_tmp_data_loc_1:
1196 .byte 0
1197 ex_tmp_data_loc_2:
1198 .byte 0
1199 ex_tmp_data_loc_3:
1200 .byte 0
1201 ex_reg_op:
1202 .byte 0
Linux kernel - Deliverables
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