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microblaze: Fix unaligned issue on MMU system with BS=0 DIV=1
[deliverable/linux.git] / arch / microblaze / kernel / hw_exception_handler.S
1 /*
2 * Exception handling for Microblaze
3 *
4 * Rewriten interrupt handling
5 *
6 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
7 * Copyright (C) 2008-2009 PetaLogix
8 *
9 * uClinux customisation (C) 2005 John Williams
10 *
11 * MMU code derived from arch/ppc/kernel/head_4xx.S:
12 * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
13 * Initial PowerPC version.
14 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
15 * Rewritten for PReP
16 * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
17 * Low-level exception handers, MMU support, and rewrite.
18 * Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
19 * PowerPC 8xx modifications.
20 * Copyright (C) 1998-1999 TiVo, Inc.
21 * PowerPC 403GCX modifications.
22 * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
23 * PowerPC 403GCX/405GP modifications.
24 * Copyright 2000 MontaVista Software Inc.
25 * PPC405 modifications
26 * PowerPC 403GCX/405GP modifications.
27 * Author: MontaVista Software, Inc.
28 * frank_rowand@mvista.com or source@mvista.com
29 * debbie_chu@mvista.com
30 *
31 * Original code
32 * Copyright (C) 2004 Xilinx, Inc.
33 *
34 * This program is free software; you can redistribute it and/or modify it
35 * under the terms of the GNU General Public License version 2 as published
36 * by the Free Software Foundation.
37 */
38
39 /*
40 * Here are the handlers which don't require enabling translation
41 * and calling other kernel code thus we can keep their design very simple
42 * and do all processing in real mode. All what they need is a valid current
43 * (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
44 * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
45 * these registers are saved/restored
46 * The handlers which require translation are in entry.S --KAA
47 *
48 * Microblaze HW Exception Handler
49 * - Non self-modifying exception handler for the following exception conditions
50 * - Unalignment
51 * - Instruction bus error
52 * - Data bus error
53 * - Illegal instruction opcode
54 * - Divide-by-zero
55 *
56 * - Privileged instruction exception (MMU)
57 * - Data storage exception (MMU)
58 * - Instruction storage exception (MMU)
59 * - Data TLB miss exception (MMU)
60 * - Instruction TLB miss exception (MMU)
61 *
62 * Note we disable interrupts during exception handling, otherwise we will
63 * possibly get multiple re-entrancy if interrupt handles themselves cause
64 * exceptions. JW
65 */
66
67 #include <asm/exceptions.h>
68 #include <asm/unistd.h>
69 #include <asm/page.h>
70
71 #include <asm/entry.h>
72 #include <asm/current.h>
73 #include <linux/linkage.h>
74
75 #include <asm/mmu.h>
76 #include <asm/pgtable.h>
77 #include <asm/signal.h>
78 #include <asm/asm-offsets.h>
79
80 /* Helpful Macros */
81 #define NUM_TO_REG(num) r ## num
82
83 #ifdef CONFIG_MMU
84 #define RESTORE_STATE \
85 lwi r5, r1, 0; \
86 mts rmsr, r5; \
87 nop; \
88 lwi r3, r1, PT_R3; \
89 lwi r4, r1, PT_R4; \
90 lwi r5, r1, PT_R5; \
91 lwi r6, r1, PT_R6; \
92 lwi r11, r1, PT_R11; \
93 lwi r31, r1, PT_R31; \
94 lwi r1, r0, TOPHYS(r0_ram + 0);
95 #endif /* CONFIG_MMU */
96
97 #define LWREG_NOP \
98 bri ex_handler_unhandled; \
99 nop;
100
101 #define SWREG_NOP \
102 bri ex_handler_unhandled; \
103 nop;
104
105 /* FIXME this is weird - for noMMU kernel is not possible to use brid
106 * instruction which can shorten executed time
107 */
108
109 /* r3 is the source */
110 #define R3_TO_LWREG_V(regnum) \
111 swi r3, r1, 4 * regnum; \
112 bri ex_handler_done;
113
114 /* r3 is the source */
115 #define R3_TO_LWREG(regnum) \
116 or NUM_TO_REG (regnum), r0, r3; \
117 bri ex_handler_done;
118
119 /* r3 is the target */
120 #define SWREG_TO_R3_V(regnum) \
121 lwi r3, r1, 4 * regnum; \
122 bri ex_sw_tail;
123
124 /* r3 is the target */
125 #define SWREG_TO_R3(regnum) \
126 or r3, r0, NUM_TO_REG (regnum); \
127 bri ex_sw_tail;
128
129 #ifdef CONFIG_MMU
130 #define R3_TO_LWREG_VM_V(regnum) \
131 brid ex_lw_end_vm; \
132 swi r3, r7, 4 * regnum;
133
134 #define R3_TO_LWREG_VM(regnum) \
135 brid ex_lw_end_vm; \
136 or NUM_TO_REG (regnum), r0, r3;
137
138 #define SWREG_TO_R3_VM_V(regnum) \
139 brid ex_sw_tail_vm; \
140 lwi r3, r7, 4 * regnum;
141
142 #define SWREG_TO_R3_VM(regnum) \
143 brid ex_sw_tail_vm; \
144 or r3, r0, NUM_TO_REG (regnum);
145
146 /* Shift right instruction depending on available configuration */
147 #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
148 #define BSRLI(rD, rA, imm) \
149 bsrli rD, rA, imm
150 #else
151 #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
152 /* Only the used shift constants defined here - add more if needed */
153 #define BSRLI2(rD, rA) \
154 srl rD, rA; /* << 1 */ \
155 srl rD, rD; /* << 2 */
156 #define BSRLI10(rD, rA) \
157 srl rD, rA; /* << 1 */ \
158 srl rD, rD; /* << 2 */ \
159 srl rD, rD; /* << 3 */ \
160 srl rD, rD; /* << 4 */ \
161 srl rD, rD; /* << 5 */ \
162 srl rD, rD; /* << 6 */ \
163 srl rD, rD; /* << 7 */ \
164 srl rD, rD; /* << 8 */ \
165 srl rD, rD; /* << 9 */ \
166 srl rD, rD /* << 10 */
167 #define BSRLI20(rD, rA) \
168 BSRLI10(rD, rA); \
169 BSRLI10(rD, rD)
170 #endif
171 #endif /* CONFIG_MMU */
172
173 .extern other_exception_handler /* Defined in exception.c */
174
175 /*
176 * hw_exception_handler - Handler for exceptions
177 *
178 * Exception handler notes:
179 * - Handles all exceptions
180 * - Does not handle unaligned exceptions during load into r17, r1, r0.
181 * - Does not handle unaligned exceptions during store from r17 (cannot be
182 * done) and r1 (slows down common case)
183 *
184 * Relevant register structures
185 *
186 * EAR - |----|----|----|----|----|----|----|----|
187 * - < ## 32 bit faulting address ## >
188 *
189 * ESR - |----|----|----|----|----| - | - |-----|-----|
190 * - W S REG EXC
191 *
192 *
193 * STACK FRAME STRUCTURE (for NO_MMU)
194 * ---------------------------------
195 *
196 * +-------------+ + 0
197 * | MSR |
198 * +-------------+ + 4
199 * | r1 |
200 * | . |
201 * | . |
202 * | . |
203 * | . |
204 * | r18 |
205 * +-------------+ + 76
206 * | . |
207 * | . |
208 *
209 * NO_MMU kernel use the same r0_ram pointed space - look to vmlinux.lds.S
210 * which is used for storing register values - old style was, that value were
211 * stored in stack but in case of failure you lost information about register.
212 * Currently you can see register value in memory in specific place.
213 * In compare to with previous solution the speed should be the same.
214 *
215 * MMU exception handler has different handling compare to no MMU kernel.
216 * Exception handler use jump table for directing of what happen. For MMU kernel
217 * is this approach better because MMU relate exception are handled by asm code
218 * in this file. In compare to with MMU expect of unaligned exception
219 * is everything handled by C code.
220 */
221
222 /*
223 * every of these handlers is entered having R3/4/5/6/11/current saved on stack
224 * and clobbered so care should be taken to restore them if someone is going to
225 * return from exception
226 */
227
228 /* wrappers to restore state before coming to entry.S */
229
230 #ifdef CONFIG_MMU
231 .section .rodata
232 .align 4
233 _MB_HW_ExceptionVectorTable:
234 /* 0 - Undefined */
235 .long TOPHYS(ex_handler_unhandled)
236 /* 1 - Unaligned data access exception */
237 .long TOPHYS(handle_unaligned_ex)
238 /* 2 - Illegal op-code exception */
239 .long TOPHYS(full_exception_trapw)
240 /* 3 - Instruction bus error exception */
241 .long TOPHYS(full_exception_trapw)
242 /* 4 - Data bus error exception */
243 .long TOPHYS(full_exception_trapw)
244 /* 5 - Divide by zero exception */
245 .long TOPHYS(full_exception_trapw)
246 /* 6 - Floating point unit exception */
247 .long TOPHYS(full_exception_trapw)
248 /* 7 - Privileged instruction exception */
249 .long TOPHYS(full_exception_trapw)
250 /* 8 - 15 - Undefined */
251 .long TOPHYS(ex_handler_unhandled)
252 .long TOPHYS(ex_handler_unhandled)
253 .long TOPHYS(ex_handler_unhandled)
254 .long TOPHYS(ex_handler_unhandled)
255 .long TOPHYS(ex_handler_unhandled)
256 .long TOPHYS(ex_handler_unhandled)
257 .long TOPHYS(ex_handler_unhandled)
258 .long TOPHYS(ex_handler_unhandled)
259 /* 16 - Data storage exception */
260 .long TOPHYS(handle_data_storage_exception)
261 /* 17 - Instruction storage exception */
262 .long TOPHYS(handle_instruction_storage_exception)
263 /* 18 - Data TLB miss exception */
264 .long TOPHYS(handle_data_tlb_miss_exception)
265 /* 19 - Instruction TLB miss exception */
266 .long TOPHYS(handle_instruction_tlb_miss_exception)
267 /* 20 - 31 - Undefined */
268 .long TOPHYS(ex_handler_unhandled)
269 .long TOPHYS(ex_handler_unhandled)
270 .long TOPHYS(ex_handler_unhandled)
271 .long TOPHYS(ex_handler_unhandled)
272 .long TOPHYS(ex_handler_unhandled)
273 .long TOPHYS(ex_handler_unhandled)
274 .long TOPHYS(ex_handler_unhandled)
275 .long TOPHYS(ex_handler_unhandled)
276 .long TOPHYS(ex_handler_unhandled)
277 .long TOPHYS(ex_handler_unhandled)
278 .long TOPHYS(ex_handler_unhandled)
279 .long TOPHYS(ex_handler_unhandled)
280 #endif
281
282 .global _hw_exception_handler
283 .section .text
284 .align 4
285 .ent _hw_exception_handler
286 _hw_exception_handler:
287 #ifndef CONFIG_MMU
288 addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
289 #else
290 swi r1, r0, TOPHYS(r0_ram + 0); /* GET_SP */
291 /* Save date to kernel memory. Here is the problem
292 * when you came from user space */
293 ori r1, r0, TOPHYS(r0_ram + 28);
294 #endif
295 swi r3, r1, PT_R3
296 swi r4, r1, PT_R4
297 swi r5, r1, PT_R5
298 swi r6, r1, PT_R6
299
300 #ifdef CONFIG_MMU
301 swi r11, r1, PT_R11
302 swi r31, r1, PT_R31
303 lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */
304 #endif
305
306 mfs r5, rmsr;
307 nop
308 swi r5, r1, 0;
309 mfs r4, resr
310 nop
311 mfs r3, rear;
312 nop
313
314 #ifndef CONFIG_MMU
315 andi r5, r4, 0x1000; /* Check ESR[DS] */
316 beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
317 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
318 nop
319 not_in_delay_slot:
320 swi r17, r1, PT_R17
321 #endif
322
323 andi r5, r4, 0x1F; /* Extract ESR[EXC] */
324
325 #ifdef CONFIG_MMU
326 /* Calculate exception vector offset = r5 << 2 */
327 addk r6, r5, r5; /* << 1 */
328 addk r6, r6, r6; /* << 2 */
329
330 #ifdef DEBUG
331 /* counting which exception happen */
332 lwi r5, r0, 0x200 + TOPHYS(r0_ram)
333 addi r5, r5, 1
334 swi r5, r0, 0x200 + TOPHYS(r0_ram)
335 lwi r5, r6, 0x200 + TOPHYS(r0_ram)
336 addi r5, r5, 1
337 swi r5, r6, 0x200 + TOPHYS(r0_ram)
338 #endif
339 /* end */
340 /* Load the HW Exception vector */
341 lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
342 bra r6
343
344 full_exception_trapw:
345 RESTORE_STATE
346 bri full_exception_trap
347 #else
348 /* Exceptions enabled here. This will allow nested exceptions */
349 mfs r6, rmsr;
350 nop
351 swi r6, r1, 0; /* RMSR_OFFSET */
352 ori r6, r6, 0x100; /* Turn ON the EE bit */
353 andi r6, r6, ~2; /* Disable interrupts */
354 mts rmsr, r6;
355 nop
356
357 xori r6, r5, 1; /* 00001 = Unaligned Exception */
358 /* Jump to unalignment exception handler */
359 beqi r6, handle_unaligned_ex;
360
361 handle_other_ex: /* Handle Other exceptions here */
362 /* Save other volatiles before we make procedure calls below */
363 swi r7, r1, PT_R7
364 swi r8, r1, PT_R8
365 swi r9, r1, PT_R9
366 swi r10, r1, PT_R10
367 swi r11, r1, PT_R11
368 swi r12, r1, PT_R12
369 swi r14, r1, PT_R14
370 swi r15, r1, PT_R15
371 swi r18, r1, PT_R18
372
373 or r5, r1, r0
374 andi r6, r4, 0x1F; /* Load ESR[EC] */
375 lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
376 swi r7, r1, PT_MODE
377 mfs r7, rfsr
378 nop
379 addk r8, r17, r0; /* Load exception address */
380 bralid r15, full_exception; /* Branch to the handler */
381 nop;
382 mts rfsr, r0; /* Clear sticky fsr */
383 nop
384
385 /*
386 * Trigger execution of the signal handler by enabling
387 * interrupts and calling an invalid syscall.
388 */
389 mfs r5, rmsr;
390 nop
391 ori r5, r5, 2;
392 mts rmsr, r5; /* enable interrupt */
393 nop
394 addi r12, r0, __NR_syscalls;
395 brki r14, 0x08;
396 mfs r5, rmsr; /* disable interrupt */
397 nop
398 andi r5, r5, ~2;
399 mts rmsr, r5;
400 nop
401
402 lwi r7, r1, PT_R7
403 lwi r8, r1, PT_R8
404 lwi r9, r1, PT_R9
405 lwi r10, r1, PT_R10
406 lwi r11, r1, PT_R11
407 lwi r12, r1, PT_R12
408 lwi r14, r1, PT_R14
409 lwi r15, r1, PT_R15
410 lwi r18, r1, PT_R18
411
412 bri ex_handler_done; /* Complete exception handling */
413 #endif
414
415 /* 0x01 - Unaligned data access exception
416 * This occurs when a word access is not aligned on a word boundary,
417 * or when a 16-bit access is not aligned on a 16-bit boundary.
418 * This handler perform the access, and returns, except for MMU when
419 * the unaligned address is last on a 4k page or the physical address is
420 * not found in the page table, in which case unaligned_data_trap is called.
421 */
422 handle_unaligned_ex:
423 /* Working registers already saved: R3, R4, R5, R6
424 * R4 = ESR
425 * R3 = EAR
426 */
427 #ifdef CONFIG_MMU
428 andi r6, r4, 0x1000 /* Check ESR[DS] */
429 beqi r6, _no_delayslot /* Branch if ESR[DS] not set */
430 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
431 nop
432 _no_delayslot:
433 /* jump to high level unaligned handler */
434 RESTORE_STATE;
435 bri unaligned_data_trap
436 #endif
437 andi r6, r4, 0x3E0; /* Mask and extract the register operand */
438 srl r6, r6; /* r6 >> 5 */
439 srl r6, r6;
440 srl r6, r6;
441 srl r6, r6;
442 srl r6, r6;
443 /* Store the register operand in a temporary location */
444 sbi r6, r0, TOPHYS(ex_reg_op);
445
446 andi r6, r4, 0x400; /* Extract ESR[S] */
447 bnei r6, ex_sw;
448 ex_lw:
449 andi r6, r4, 0x800; /* Extract ESR[W] */
450 beqi r6, ex_lhw;
451 lbui r5, r3, 0; /* Exception address in r3 */
452 /* Load a word, byte-by-byte from destination address
453 and save it in tmp space */
454 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
455 lbui r5, r3, 1;
456 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
457 lbui r5, r3, 2;
458 sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
459 lbui r5, r3, 3;
460 sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
461 /* Get the destination register value into r4 */
462 lwi r4, r0, TOPHYS(ex_tmp_data_loc_0);
463 bri ex_lw_tail;
464 ex_lhw:
465 lbui r5, r3, 0; /* Exception address in r3 */
466 /* Load a half-word, byte-by-byte from destination
467 address and save it in tmp space */
468 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
469 lbui r5, r3, 1;
470 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
471 /* Get the destination register value into r4 */
472 lhui r4, r0, TOPHYS(ex_tmp_data_loc_0);
473 ex_lw_tail:
474 /* Get the destination register number into r5 */
475 lbui r5, r0, TOPHYS(ex_reg_op);
476 /* Form load_word jump table offset (lw_table + (8 * regnum)) */
477 la r6, r0, TOPHYS(lw_table);
478 addk r5, r5, r5;
479 addk r5, r5, r5;
480 addk r5, r5, r5;
481 addk r5, r5, r6;
482 bra r5;
483 ex_lw_end: /* Exception handling of load word, ends */
484 ex_sw:
485 /* Get the destination register number into r5 */
486 lbui r5, r0, TOPHYS(ex_reg_op);
487 /* Form store_word jump table offset (sw_table + (8 * regnum)) */
488 la r6, r0, TOPHYS(sw_table);
489 add r5, r5, r5;
490 add r5, r5, r5;
491 add r5, r5, r5;
492 add r5, r5, r6;
493 bra r5;
494 ex_sw_tail:
495 mfs r6, resr;
496 nop
497 andi r6, r6, 0x800; /* Extract ESR[W] */
498 beqi r6, ex_shw;
499 /* Get the word - delay slot */
500 swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
501 /* Store the word, byte-by-byte into destination address */
502 lbui r4, r0, TOPHYS(ex_tmp_data_loc_0);
503 sbi r4, r3, 0;
504 lbui r4, r0, TOPHYS(ex_tmp_data_loc_1);
505 sbi r4, r3, 1;
506 lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
507 sbi r4, r3, 2;
508 lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
509 sbi r4, r3, 3;
510 bri ex_handler_done;
511
512 ex_shw:
513 /* Store the lower half-word, byte-by-byte into destination address */
514 swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
515 lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
516 sbi r4, r3, 0;
517 lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
518 sbi r4, r3, 1;
519 ex_sw_end: /* Exception handling of store word, ends. */
520
521 ex_handler_done:
522 #ifndef CONFIG_MMU
523 lwi r5, r1, 0 /* RMSR */
524 mts rmsr, r5
525 nop
526 lwi r3, r1, PT_R3
527 lwi r4, r1, PT_R4
528 lwi r5, r1, PT_R5
529 lwi r6, r1, PT_R6
530 lwi r17, r1, PT_R17
531
532 rted r17, 0
533 addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
534 #else
535 RESTORE_STATE;
536 rted r17, 0
537 nop
538 #endif
539
540 #ifdef CONFIG_MMU
541 /* Exception vector entry code. This code runs with address translation
542 * turned off (i.e. using physical addresses). */
543
544 /* Exception vectors. */
545
546 /* 0x10 - Data Storage Exception
547 * This happens for just a few reasons. U0 set (but we don't do that),
548 * or zone protection fault (user violation, write to protected page).
549 * If this is just an update of modified status, we do that quickly
550 * and exit. Otherwise, we call heavyweight functions to do the work.
551 */
552 handle_data_storage_exception:
553 /* Working registers already saved: R3, R4, R5, R6
554 * R3 = ESR
555 */
556 mfs r11, rpid
557 nop
558 /* If we are faulting a kernel address, we have to use the
559 * kernel page tables.
560 */
561 ori r5, r0, CONFIG_KERNEL_START
562 cmpu r5, r3, r5
563 bgti r5, ex3
564 /* First, check if it was a zone fault (which means a user
565 * tried to access a kernel or read-protected page - always
566 * a SEGV). All other faults here must be stores, so no
567 * need to check ESR_S as well. */
568 andi r4, r4, 0x800 /* ESR_Z - zone protection */
569 bnei r4, ex2
570
571 ori r4, r0, swapper_pg_dir
572 mts rpid, r0 /* TLB will have 0 TID */
573 nop
574 bri ex4
575
576 /* Get the PGD for the current thread. */
577 ex3:
578 /* First, check if it was a zone fault (which means a user
579 * tried to access a kernel or read-protected page - always
580 * a SEGV). All other faults here must be stores, so no
581 * need to check ESR_S as well. */
582 andi r4, r4, 0x800 /* ESR_Z */
583 bnei r4, ex2
584 /* get current task address */
585 addi r4 ,CURRENT_TASK, TOPHYS(0);
586 lwi r4, r4, TASK_THREAD+PGDIR
587 ex4:
588 tophys(r4,r4)
589 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
590 andi r5, r5, 0xffc
591 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
592 or r4, r4, r5
593 lwi r4, r4, 0 /* Get L1 entry */
594 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
595 beqi r5, ex2 /* Bail if no table */
596
597 tophys(r5,r5)
598 BSRLI(r6,r3,10) /* Compute PTE address */
599 andi r6, r6, 0xffc
600 andi r5, r5, 0xfffff003
601 or r5, r5, r6
602 lwi r4, r5, 0 /* Get Linux PTE */
603
604 andi r6, r4, _PAGE_RW /* Is it writeable? */
605 beqi r6, ex2 /* Bail if not */
606
607 /* Update 'changed' */
608 ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
609 swi r4, r5, 0 /* Update Linux page table */
610
611 /* Most of the Linux PTE is ready to load into the TLB LO.
612 * We set ZSEL, where only the LS-bit determines user access.
613 * We set execute, because we don't have the granularity to
614 * properly set this at the page level (Linux problem).
615 * If shared is set, we cause a zero PID->TID load.
616 * Many of these bits are software only. Bits we don't set
617 * here we (properly should) assume have the appropriate value.
618 */
619 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
620 ori r4, r4, _PAGE_HWEXEC /* make it executable */
621
622 /* find the TLB index that caused the fault. It has to be here*/
623 mts rtlbsx, r3
624 nop
625 mfs r5, rtlbx /* DEBUG: TBD */
626 nop
627 mts rtlblo, r4 /* Load TLB LO */
628 nop
629 /* Will sync shadow TLBs */
630
631 /* Done...restore registers and get out of here. */
632 mts rpid, r11
633 nop
634 bri 4
635
636 RESTORE_STATE;
637 rted r17, 0
638 nop
639 ex2:
640 /* The bailout. Restore registers to pre-exception conditions
641 * and call the heavyweights to help us out. */
642 mts rpid, r11
643 nop
644 bri 4
645 RESTORE_STATE;
646 bri page_fault_data_trap
647
648
649 /* 0x11 - Instruction Storage Exception
650 * This is caused by a fetch from non-execute or guarded pages. */
651 handle_instruction_storage_exception:
652 /* Working registers already saved: R3, R4, R5, R6
653 * R3 = ESR
654 */
655
656 RESTORE_STATE;
657 bri page_fault_instr_trap
658
659 /* 0x12 - Data TLB Miss Exception
660 * As the name implies, translation is not in the MMU, so search the
661 * page tables and fix it. The only purpose of this function is to
662 * load TLB entries from the page table if they exist.
663 */
664 handle_data_tlb_miss_exception:
665 /* Working registers already saved: R3, R4, R5, R6
666 * R3 = EAR, R4 = ESR
667 */
668 mfs r11, rpid
669 nop
670
671 /* If we are faulting a kernel address, we have to use the
672 * kernel page tables. */
673 ori r6, r0, CONFIG_KERNEL_START
674 cmpu r4, r3, r6
675 bgti r4, ex5
676 ori r4, r0, swapper_pg_dir
677 mts rpid, r0 /* TLB will have 0 TID */
678 nop
679 bri ex6
680
681 /* Get the PGD for the current thread. */
682 ex5:
683 /* get current task address */
684 addi r4 ,CURRENT_TASK, TOPHYS(0);
685 lwi r4, r4, TASK_THREAD+PGDIR
686 ex6:
687 tophys(r4,r4)
688 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
689 andi r5, r5, 0xffc
690 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
691 or r4, r4, r5
692 lwi r4, r4, 0 /* Get L1 entry */
693 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
694 beqi r5, ex7 /* Bail if no table */
695
696 tophys(r5,r5)
697 BSRLI(r6,r3,10) /* Compute PTE address */
698 andi r6, r6, 0xffc
699 andi r5, r5, 0xfffff003
700 or r5, r5, r6
701 lwi r4, r5, 0 /* Get Linux PTE */
702
703 andi r6, r4, _PAGE_PRESENT
704 beqi r6, ex7
705
706 ori r4, r4, _PAGE_ACCESSED
707 swi r4, r5, 0
708
709 /* Most of the Linux PTE is ready to load into the TLB LO.
710 * We set ZSEL, where only the LS-bit determines user access.
711 * We set execute, because we don't have the granularity to
712 * properly set this at the page level (Linux problem).
713 * If shared is set, we cause a zero PID->TID load.
714 * Many of these bits are software only. Bits we don't set
715 * here we (properly should) assume have the appropriate value.
716 */
717 brid finish_tlb_load
718 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
719 ex7:
720 /* The bailout. Restore registers to pre-exception conditions
721 * and call the heavyweights to help us out.
722 */
723 mts rpid, r11
724 nop
725 bri 4
726 RESTORE_STATE;
727 bri page_fault_data_trap
728
729 /* 0x13 - Instruction TLB Miss Exception
730 * Nearly the same as above, except we get our information from
731 * different registers and bailout to a different point.
732 */
733 handle_instruction_tlb_miss_exception:
734 /* Working registers already saved: R3, R4, R5, R6
735 * R3 = ESR
736 */
737 mfs r11, rpid
738 nop
739
740 /* If we are faulting a kernel address, we have to use the
741 * kernel page tables.
742 */
743 ori r4, r0, CONFIG_KERNEL_START
744 cmpu r4, r3, r4
745 bgti r4, ex8
746 ori r4, r0, swapper_pg_dir
747 mts rpid, r0 /* TLB will have 0 TID */
748 nop
749 bri ex9
750
751 /* Get the PGD for the current thread. */
752 ex8:
753 /* get current task address */
754 addi r4 ,CURRENT_TASK, TOPHYS(0);
755 lwi r4, r4, TASK_THREAD+PGDIR
756 ex9:
757 tophys(r4,r4)
758 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
759 andi r5, r5, 0xffc
760 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
761 or r4, r4, r5
762 lwi r4, r4, 0 /* Get L1 entry */
763 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
764 beqi r5, ex10 /* Bail if no table */
765
766 tophys(r5,r5)
767 BSRLI(r6,r3,10) /* Compute PTE address */
768 andi r6, r6, 0xffc
769 andi r5, r5, 0xfffff003
770 or r5, r5, r6
771 lwi r4, r5, 0 /* Get Linux PTE */
772
773 andi r6, r4, _PAGE_PRESENT
774 beqi r6, ex10
775
776 ori r4, r4, _PAGE_ACCESSED
777 swi r4, r5, 0
778
779 /* Most of the Linux PTE is ready to load into the TLB LO.
780 * We set ZSEL, where only the LS-bit determines user access.
781 * We set execute, because we don't have the granularity to
782 * properly set this at the page level (Linux problem).
783 * If shared is set, we cause a zero PID->TID load.
784 * Many of these bits are software only. Bits we don't set
785 * here we (properly should) assume have the appropriate value.
786 */
787 brid finish_tlb_load
788 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
789 ex10:
790 /* The bailout. Restore registers to pre-exception conditions
791 * and call the heavyweights to help us out.
792 */
793 mts rpid, r11
794 nop
795 bri 4
796 RESTORE_STATE;
797 bri page_fault_instr_trap
798
799 /* Both the instruction and data TLB miss get to this point to load the TLB.
800 * r3 - EA of fault
801 * r4 - TLB LO (info from Linux PTE)
802 * r5, r6 - available to use
803 * PID - loaded with proper value when we get here
804 * Upon exit, we reload everything and RFI.
805 * A common place to load the TLB.
806 */
807 tlb_index:
808 .long 1 /* MS: storing last used tlb index */
809 finish_tlb_load:
810 /* MS: load the last used TLB index. */
811 lwi r5, r0, TOPHYS(tlb_index)
812 addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
813
814 /* MS: FIXME this is potential fault, because this is mask not count */
815 andi r5, r5, (MICROBLAZE_TLB_SIZE-1)
816 ori r6, r0, 1
817 cmp r31, r5, r6
818 blti r31, ex12
819 addik r5, r6, 1
820 ex12:
821 /* MS: save back current TLB index */
822 swi r5, r0, TOPHYS(tlb_index)
823
824 ori r4, r4, _PAGE_HWEXEC /* make it executable */
825 mts rtlbx, r5 /* MS: save current TLB */
826 nop
827 mts rtlblo, r4 /* MS: save to TLB LO */
828 nop
829
830 /* Create EPN. This is the faulting address plus a static
831 * set of bits. These are size, valid, E, U0, and ensure
832 * bits 20 and 21 are zero.
833 */
834 andi r3, r3, 0xfffff000
835 ori r3, r3, 0x0c0
836 mts rtlbhi, r3 /* Load TLB HI */
837 nop
838
839 /* Done...restore registers and get out of here. */
840 mts rpid, r11
841 nop
842 bri 4
843 RESTORE_STATE;
844 rted r17, 0
845 nop
846
847 /* extern void giveup_fpu(struct task_struct *prev)
848 *
849 * The MicroBlaze processor may have an FPU, so this should not just
850 * return: TBD.
851 */
852 .globl giveup_fpu;
853 .align 4;
854 giveup_fpu:
855 bralid r15,0 /* TBD */
856 nop
857
858 /* At present, this routine just hangs. - extern void abort(void) */
859 .globl abort;
860 .align 4;
861 abort:
862 br r0
863
864 .globl set_context;
865 .align 4;
866 set_context:
867 mts rpid, r5 /* Shadow TLBs are automatically */
868 nop
869 bri 4 /* flushed by changing PID */
870 rtsd r15,8
871 nop
872
873 #endif
874 .end _hw_exception_handler
875
876 #ifdef CONFIG_MMU
877 /* Unaligned data access exception last on a 4k page for MMU.
878 * When this is called, we are in virtual mode with exceptions enabled
879 * and registers 1-13,15,17,18 saved.
880 *
881 * R3 = ESR
882 * R4 = EAR
883 * R7 = pointer to saved registers (struct pt_regs *regs)
884 *
885 * This handler perform the access, and returns via ret_from_exc.
886 */
887 .global _unaligned_data_exception
888 .ent _unaligned_data_exception
889 _unaligned_data_exception:
890 andi r8, r3, 0x3E0; /* Mask and extract the register operand */
891 BSRLI(r8,r8,2); /* r8 >> 2 = register operand * 8 */
892 andi r6, r3, 0x400; /* Extract ESR[S] */
893 bneid r6, ex_sw_vm;
894 andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
895 ex_lw_vm:
896 beqid r6, ex_lhw_vm;
897 load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
898 /* Load a word, byte-by-byte from destination address and save it in tmp space*/
899 la r6, r0, ex_tmp_data_loc_0;
900 sbi r5, r6, 0;
901 load2: lbui r5, r4, 1;
902 sbi r5, r6, 1;
903 load3: lbui r5, r4, 2;
904 sbi r5, r6, 2;
905 load4: lbui r5, r4, 3;
906 sbi r5, r6, 3;
907 brid ex_lw_tail_vm;
908 /* Get the destination register value into r3 - delay slot */
909 lwi r3, r6, 0;
910 ex_lhw_vm:
911 /* Load a half-word, byte-by-byte from destination address and
912 * save it in tmp space */
913 la r6, r0, ex_tmp_data_loc_0;
914 sbi r5, r6, 0;
915 load5: lbui r5, r4, 1;
916 sbi r5, r6, 1;
917 lhui r3, r6, 0; /* Get the destination register value into r3 */
918 ex_lw_tail_vm:
919 /* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */
920 addik r5, r8, lw_table_vm;
921 bra r5;
922 ex_lw_end_vm: /* Exception handling of load word, ends */
923 brai ret_from_exc;
924 ex_sw_vm:
925 /* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */
926 addik r5, r8, sw_table_vm;
927 bra r5;
928 ex_sw_tail_vm:
929 la r5, r0, ex_tmp_data_loc_0;
930 beqid r6, ex_shw_vm;
931 swi r3, r5, 0; /* Get the word - delay slot */
932 /* Store the word, byte-by-byte into destination address */
933 lbui r3, r5, 0;
934 store1: sbi r3, r4, 0;
935 lbui r3, r5, 1;
936 store2: sbi r3, r4, 1;
937 lbui r3, r5, 2;
938 store3: sbi r3, r4, 2;
939 lbui r3, r5, 3;
940 brid ret_from_exc;
941 store4: sbi r3, r4, 3; /* Delay slot */
942 ex_shw_vm:
943 /* Store the lower half-word, byte-by-byte into destination address */
944 #ifdef __MICROBLAZEEL__
945 lbui r3, r5, 0;
946 store5: sbi r3, r4, 0;
947 lbui r3, r5, 1;
948 brid ret_from_exc;
949 store6: sbi r3, r4, 1; /* Delay slot */
950 #else
951 lbui r3, r5, 2;
952 store5: sbi r3, r4, 0;
953 lbui r3, r5, 3;
954 brid ret_from_exc;
955 store6: sbi r3, r4, 1; /* Delay slot */
956 #endif
957
958 ex_sw_end_vm: /* Exception handling of store word, ends. */
959
960 /* We have to prevent cases that get/put_user macros get unaligned pointer
961 * to bad page area. We have to find out which origin instruction caused it
962 * and called fixup for that origin instruction not instruction in unaligned
963 * handler */
964 ex_unaligned_fixup:
965 ori r5, r7, 0 /* setup pointer to pt_regs */
966 lwi r6, r7, PT_PC; /* faulting address is one instruction above */
967 addik r6, r6, -4 /* for finding proper fixup */
968 swi r6, r7, PT_PC; /* a save back it to PT_PC */
969 addik r7, r0, SIGSEGV
970 /* call bad_page_fault for finding aligned fixup, fixup address is saved
971 * in PT_PC which is used as return address from exception */
972 la r15, r0, ret_from_exc-8 /* setup return address */
973 brid bad_page_fault
974 nop
975
976 /* We prevent all load/store because it could failed any attempt to access */
977 .section __ex_table,"a";
978 .word load1,ex_unaligned_fixup;
979 .word load2,ex_unaligned_fixup;
980 .word load3,ex_unaligned_fixup;
981 .word load4,ex_unaligned_fixup;
982 .word load5,ex_unaligned_fixup;
983 .word store1,ex_unaligned_fixup;
984 .word store2,ex_unaligned_fixup;
985 .word store3,ex_unaligned_fixup;
986 .word store4,ex_unaligned_fixup;
987 .word store5,ex_unaligned_fixup;
988 .word store6,ex_unaligned_fixup;
989 .previous;
990 .end _unaligned_data_exception
991 #endif /* CONFIG_MMU */
992
993 .global ex_handler_unhandled
994 ex_handler_unhandled:
995 /* FIXME add handle function for unhandled exception - dump register */
996 bri 0
997
998 /*
999 * hw_exception_handler Jump Table
1000 * - Contains code snippets for each register that caused the unalign exception
1001 * - Hence exception handler is NOT self-modifying
1002 * - Separate table for load exceptions and store exceptions.
1003 * - Each table is of size: (8 * 32) = 256 bytes
1004 */
1005
1006 .section .text
1007 .align 4
1008 lw_table:
1009 lw_r0: R3_TO_LWREG (0);
1010 lw_r1: LWREG_NOP;
1011 lw_r2: R3_TO_LWREG (2);
1012 lw_r3: R3_TO_LWREG_V (3);
1013 lw_r4: R3_TO_LWREG_V (4);
1014 lw_r5: R3_TO_LWREG_V (5);
1015 lw_r6: R3_TO_LWREG_V (6);
1016 lw_r7: R3_TO_LWREG (7);
1017 lw_r8: R3_TO_LWREG (8);
1018 lw_r9: R3_TO_LWREG (9);
1019 lw_r10: R3_TO_LWREG (10);
1020 lw_r11: R3_TO_LWREG (11);
1021 lw_r12: R3_TO_LWREG (12);
1022 lw_r13: R3_TO_LWREG (13);
1023 lw_r14: R3_TO_LWREG (14);
1024 lw_r15: R3_TO_LWREG (15);
1025 lw_r16: R3_TO_LWREG (16);
1026 lw_r17: LWREG_NOP;
1027 lw_r18: R3_TO_LWREG (18);
1028 lw_r19: R3_TO_LWREG (19);
1029 lw_r20: R3_TO_LWREG (20);
1030 lw_r21: R3_TO_LWREG (21);
1031 lw_r22: R3_TO_LWREG (22);
1032 lw_r23: R3_TO_LWREG (23);
1033 lw_r24: R3_TO_LWREG (24);
1034 lw_r25: R3_TO_LWREG (25);
1035 lw_r26: R3_TO_LWREG (26);
1036 lw_r27: R3_TO_LWREG (27);
1037 lw_r28: R3_TO_LWREG (28);
1038 lw_r29: R3_TO_LWREG (29);
1039 lw_r30: R3_TO_LWREG (30);
1040 #ifdef CONFIG_MMU
1041 lw_r31: R3_TO_LWREG_V (31);
1042 #else
1043 lw_r31: R3_TO_LWREG (31);
1044 #endif
1045
1046 sw_table:
1047 sw_r0: SWREG_TO_R3 (0);
1048 sw_r1: SWREG_NOP;
1049 sw_r2: SWREG_TO_R3 (2);
1050 sw_r3: SWREG_TO_R3_V (3);
1051 sw_r4: SWREG_TO_R3_V (4);
1052 sw_r5: SWREG_TO_R3_V (5);
1053 sw_r6: SWREG_TO_R3_V (6);
1054 sw_r7: SWREG_TO_R3 (7);
1055 sw_r8: SWREG_TO_R3 (8);
1056 sw_r9: SWREG_TO_R3 (9);
1057 sw_r10: SWREG_TO_R3 (10);
1058 sw_r11: SWREG_TO_R3 (11);
1059 sw_r12: SWREG_TO_R3 (12);
1060 sw_r13: SWREG_TO_R3 (13);
1061 sw_r14: SWREG_TO_R3 (14);
1062 sw_r15: SWREG_TO_R3 (15);
1063 sw_r16: SWREG_TO_R3 (16);
1064 sw_r17: SWREG_NOP;
1065 sw_r18: SWREG_TO_R3 (18);
1066 sw_r19: SWREG_TO_R3 (19);
1067 sw_r20: SWREG_TO_R3 (20);
1068 sw_r21: SWREG_TO_R3 (21);
1069 sw_r22: SWREG_TO_R3 (22);
1070 sw_r23: SWREG_TO_R3 (23);
1071 sw_r24: SWREG_TO_R3 (24);
1072 sw_r25: SWREG_TO_R3 (25);
1073 sw_r26: SWREG_TO_R3 (26);
1074 sw_r27: SWREG_TO_R3 (27);
1075 sw_r28: SWREG_TO_R3 (28);
1076 sw_r29: SWREG_TO_R3 (29);
1077 sw_r30: SWREG_TO_R3 (30);
1078 #ifdef CONFIG_MMU
1079 sw_r31: SWREG_TO_R3_V (31);
1080 #else
1081 sw_r31: SWREG_TO_R3 (31);
1082 #endif
1083
1084 #ifdef CONFIG_MMU
1085 lw_table_vm:
1086 lw_r0_vm: R3_TO_LWREG_VM (0);
1087 lw_r1_vm: R3_TO_LWREG_VM_V (1);
1088 lw_r2_vm: R3_TO_LWREG_VM_V (2);
1089 lw_r3_vm: R3_TO_LWREG_VM_V (3);
1090 lw_r4_vm: R3_TO_LWREG_VM_V (4);
1091 lw_r5_vm: R3_TO_LWREG_VM_V (5);
1092 lw_r6_vm: R3_TO_LWREG_VM_V (6);
1093 lw_r7_vm: R3_TO_LWREG_VM_V (7);
1094 lw_r8_vm: R3_TO_LWREG_VM_V (8);
1095 lw_r9_vm: R3_TO_LWREG_VM_V (9);
1096 lw_r10_vm: R3_TO_LWREG_VM_V (10);
1097 lw_r11_vm: R3_TO_LWREG_VM_V (11);
1098 lw_r12_vm: R3_TO_LWREG_VM_V (12);
1099 lw_r13_vm: R3_TO_LWREG_VM_V (13);
1100 lw_r14_vm: R3_TO_LWREG_VM (14);
1101 lw_r15_vm: R3_TO_LWREG_VM_V (15);
1102 lw_r16_vm: R3_TO_LWREG_VM (16);
1103 lw_r17_vm: R3_TO_LWREG_VM_V (17);
1104 lw_r18_vm: R3_TO_LWREG_VM_V (18);
1105 lw_r19_vm: R3_TO_LWREG_VM (19);
1106 lw_r20_vm: R3_TO_LWREG_VM (20);
1107 lw_r21_vm: R3_TO_LWREG_VM (21);
1108 lw_r22_vm: R3_TO_LWREG_VM (22);
1109 lw_r23_vm: R3_TO_LWREG_VM (23);
1110 lw_r24_vm: R3_TO_LWREG_VM (24);
1111 lw_r25_vm: R3_TO_LWREG_VM (25);
1112 lw_r26_vm: R3_TO_LWREG_VM (26);
1113 lw_r27_vm: R3_TO_LWREG_VM (27);
1114 lw_r28_vm: R3_TO_LWREG_VM (28);
1115 lw_r29_vm: R3_TO_LWREG_VM (29);
1116 lw_r30_vm: R3_TO_LWREG_VM (30);
1117 lw_r31_vm: R3_TO_LWREG_VM_V (31);
1118
1119 sw_table_vm:
1120 sw_r0_vm: SWREG_TO_R3_VM (0);
1121 sw_r1_vm: SWREG_TO_R3_VM_V (1);
1122 sw_r2_vm: SWREG_TO_R3_VM_V (2);
1123 sw_r3_vm: SWREG_TO_R3_VM_V (3);
1124 sw_r4_vm: SWREG_TO_R3_VM_V (4);
1125 sw_r5_vm: SWREG_TO_R3_VM_V (5);
1126 sw_r6_vm: SWREG_TO_R3_VM_V (6);
1127 sw_r7_vm: SWREG_TO_R3_VM_V (7);
1128 sw_r8_vm: SWREG_TO_R3_VM_V (8);
1129 sw_r9_vm: SWREG_TO_R3_VM_V (9);
1130 sw_r10_vm: SWREG_TO_R3_VM_V (10);
1131 sw_r11_vm: SWREG_TO_R3_VM_V (11);
1132 sw_r12_vm: SWREG_TO_R3_VM_V (12);
1133 sw_r13_vm: SWREG_TO_R3_VM_V (13);
1134 sw_r14_vm: SWREG_TO_R3_VM (14);
1135 sw_r15_vm: SWREG_TO_R3_VM_V (15);
1136 sw_r16_vm: SWREG_TO_R3_VM (16);
1137 sw_r17_vm: SWREG_TO_R3_VM_V (17);
1138 sw_r18_vm: SWREG_TO_R3_VM_V (18);
1139 sw_r19_vm: SWREG_TO_R3_VM (19);
1140 sw_r20_vm: SWREG_TO_R3_VM (20);
1141 sw_r21_vm: SWREG_TO_R3_VM (21);
1142 sw_r22_vm: SWREG_TO_R3_VM (22);
1143 sw_r23_vm: SWREG_TO_R3_VM (23);
1144 sw_r24_vm: SWREG_TO_R3_VM (24);
1145 sw_r25_vm: SWREG_TO_R3_VM (25);
1146 sw_r26_vm: SWREG_TO_R3_VM (26);
1147 sw_r27_vm: SWREG_TO_R3_VM (27);
1148 sw_r28_vm: SWREG_TO_R3_VM (28);
1149 sw_r29_vm: SWREG_TO_R3_VM (29);
1150 sw_r30_vm: SWREG_TO_R3_VM (30);
1151 sw_r31_vm: SWREG_TO_R3_VM_V (31);
1152 #endif /* CONFIG_MMU */
1153
1154 /* Temporary data structures used in the handler */
1155 .section .data
1156 .align 4
1157 ex_tmp_data_loc_0:
1158 .byte 0
1159 ex_tmp_data_loc_1:
1160 .byte 0
1161 ex_tmp_data_loc_2:
1162 .byte 0
1163 ex_tmp_data_loc_3:
1164 .byte 0
1165 ex_reg_op:
1166 .byte 0
Linux kernel - Deliverables
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