2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_pci.h>
34 #include <linux/export.h>
36 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
41 static DEFINE_SPINLOCK(hose_spinlock
);
44 /* XXX kill that some day ... */
45 static int global_phb_number
; /* Global phb counter */
47 /* ISA Memory physical address */
48 resource_size_t isa_mem_base
;
50 unsigned long isa_io_base
;
51 EXPORT_SYMBOL(isa_io_base
);
53 static int pci_bus_count
;
55 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
57 struct pci_controller
*phb
;
59 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
62 spin_lock(&hose_spinlock
);
63 phb
->global_number
= global_phb_number
++;
64 list_add_tail(&phb
->list_node
, &hose_list
);
65 spin_unlock(&hose_spinlock
);
67 phb
->is_dynamic
= mem_init_done
;
71 void pcibios_free_controller(struct pci_controller
*phb
)
73 spin_lock(&hose_spinlock
);
74 list_del(&phb
->list_node
);
75 spin_unlock(&hose_spinlock
);
81 static resource_size_t
pcibios_io_size(const struct pci_controller
*hose
)
83 return resource_size(&hose
->io_resource
);
86 int pcibios_vaddr_is_ioport(void __iomem
*address
)
89 struct pci_controller
*hose
;
92 spin_lock(&hose_spinlock
);
93 list_for_each_entry(hose
, &hose_list
, list_node
) {
94 size
= pcibios_io_size(hose
);
95 if (address
>= hose
->io_base_virt
&&
96 address
< (hose
->io_base_virt
+ size
)) {
101 spin_unlock(&hose_spinlock
);
105 unsigned long pci_address_to_pio(phys_addr_t address
)
107 struct pci_controller
*hose
;
108 resource_size_t size
;
109 unsigned long ret
= ~0;
111 spin_lock(&hose_spinlock
);
112 list_for_each_entry(hose
, &hose_list
, list_node
) {
113 size
= pcibios_io_size(hose
);
114 if (address
>= hose
->io_base_phys
&&
115 address
< (hose
->io_base_phys
+ size
)) {
117 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
118 ret
= base
+ (address
- hose
->io_base_phys
);
122 spin_unlock(&hose_spinlock
);
126 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
128 /* This routine is meant to be used early during boot, when the
129 * PCI bus numbers have not yet been assigned, and you need to
130 * issue PCI config cycles to an OF device.
131 * It could also be used to "fix" RTAS config cycles if you want
132 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
135 struct pci_controller
*pci_find_hose_for_OF_device(struct device_node
*node
)
138 struct pci_controller
*hose
, *tmp
;
139 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
140 if (hose
->dn
== node
)
147 void pcibios_set_master(struct pci_dev
*dev
)
149 /* No special bus mastering setup handling */
153 * Platform support for /proc/bus/pci/X/Y mmap()s,
154 * modelled on the sparc64 implementation by Dave Miller.
159 * Adjust vm_pgoff of VMA such that it is the physical page offset
160 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
162 * Basically, the user finds the base address for his device which he wishes
163 * to mmap. They read the 32-bit value from the config space base register,
164 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
165 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
167 * Returns negative error code on failure, zero on success.
169 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
170 resource_size_t
*offset
,
171 enum pci_mmap_state mmap_state
)
173 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
174 unsigned long io_offset
= 0;
178 return NULL
; /* should never happen */
180 /* If memory, add on the PCI bridge address offset */
181 if (mmap_state
== pci_mmap_mem
) {
182 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
183 *offset
+= hose
->pci_mem_offset
;
185 res_bit
= IORESOURCE_MEM
;
187 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
188 *offset
+= io_offset
;
189 res_bit
= IORESOURCE_IO
;
193 * Check that the offset requested corresponds to one of the
194 * resources of the device.
196 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
197 struct resource
*rp
= &dev
->resource
[i
];
198 int flags
= rp
->flags
;
200 /* treat ROM as memory (should be already) */
201 if (i
== PCI_ROM_RESOURCE
)
202 flags
|= IORESOURCE_MEM
;
204 /* Active and same type? */
205 if ((flags
& res_bit
) == 0)
208 /* In the range of this resource? */
209 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
212 /* found it! construct the final physical address */
213 if (mmap_state
== pci_mmap_io
)
214 *offset
+= hose
->io_base_phys
- io_offset
;
222 * This one is used by /dev/mem and fbdev who have no clue about the
223 * PCI device, it tries to find the PCI device first and calls the
226 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
231 struct pci_dev
*pdev
= NULL
;
232 struct resource
*found
= NULL
;
233 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
236 if (page_is_ram(pfn
))
239 prot
= pgprot_noncached(prot
);
240 for_each_pci_dev(pdev
) {
241 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
242 struct resource
*rp
= &pdev
->resource
[i
];
243 int flags
= rp
->flags
;
245 /* Active and same type? */
246 if ((flags
& IORESOURCE_MEM
) == 0)
248 /* In the range of this resource? */
249 if (offset
< (rp
->start
& PAGE_MASK
) ||
259 if (found
->flags
& IORESOURCE_PREFETCH
)
260 prot
= pgprot_noncached_wc(prot
);
264 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
265 (unsigned long long)offset
, pgprot_val(prot
));
271 * Perform the actual remap of the pages for a PCI device mapping, as
272 * appropriate for this architecture. The region in the process to map
273 * is described by vm_start and vm_end members of VMA, the base physical
274 * address is found in vm_pgoff.
275 * The pci device structure is provided so that architectures may make mapping
276 * decisions on a per-device or per-bus basis.
278 * Returns a negative error code on failure, zero on success.
280 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
281 enum pci_mmap_state mmap_state
, int write_combine
)
283 resource_size_t offset
=
284 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
288 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
292 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
293 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
295 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
296 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
301 /* This provides legacy IO read access on a bus */
302 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
304 unsigned long offset
;
305 struct pci_controller
*hose
= pci_bus_to_host(bus
);
306 struct resource
*rp
= &hose
->io_resource
;
309 /* Check if port can be supported by that bus. We only check
310 * the ranges of the PHB though, not the bus itself as the rules
311 * for forwarding legacy cycles down bridges are not our problem
312 * here. So if the host bridge supports it, we do it.
314 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
317 if (!(rp
->flags
& IORESOURCE_IO
))
319 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
321 addr
= hose
->io_base_virt
+ port
;
325 *((u8
*)val
) = in_8(addr
);
330 *((u16
*)val
) = in_le16(addr
);
335 *((u32
*)val
) = in_le32(addr
);
341 /* This provides legacy IO write access on a bus */
342 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
344 unsigned long offset
;
345 struct pci_controller
*hose
= pci_bus_to_host(bus
);
346 struct resource
*rp
= &hose
->io_resource
;
349 /* Check if port can be supported by that bus. We only check
350 * the ranges of the PHB though, not the bus itself as the rules
351 * for forwarding legacy cycles down bridges are not our problem
352 * here. So if the host bridge supports it, we do it.
354 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
357 if (!(rp
->flags
& IORESOURCE_IO
))
359 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
361 addr
= hose
->io_base_virt
+ port
;
363 /* WARNING: The generic code is idiotic. It gets passed a pointer
364 * to what can be a 1, 2 or 4 byte quantity and always reads that
365 * as a u32, which means that we have to correct the location of
366 * the data read within those 32 bits for size 1 and 2
370 out_8(addr
, val
>> 24);
375 out_le16(addr
, val
>> 16);
386 /* This provides legacy IO or memory mmap access on a bus */
387 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
388 struct vm_area_struct
*vma
,
389 enum pci_mmap_state mmap_state
)
391 struct pci_controller
*hose
= pci_bus_to_host(bus
);
392 resource_size_t offset
=
393 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
394 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
397 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
398 pci_domain_nr(bus
), bus
->number
,
399 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
400 (unsigned long long)offset
,
401 (unsigned long long)(offset
+ size
- 1));
403 if (mmap_state
== pci_mmap_mem
) {
406 * Because X is lame and can fail starting if it gets an error
407 * trying to mmap legacy_mem (instead of just moving on without
408 * legacy memory access) we fake it here by giving it anonymous
409 * memory, effectively behaving just like /dev/zero
411 if ((offset
+ size
) > hose
->isa_mem_size
) {
413 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
414 current
->comm
, current
->pid
);
415 pr_debug("legacy memory for 0%04x:%02x\n",
416 pci_domain_nr(bus
), bus
->number
);
418 if (vma
->vm_flags
& VM_SHARED
)
419 return shmem_zero_setup(vma
);
422 offset
+= hose
->isa_mem_phys
;
424 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
-
426 unsigned long roffset
= offset
+ io_offset
;
427 rp
= &hose
->io_resource
;
428 if (!(rp
->flags
& IORESOURCE_IO
))
430 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
432 offset
+= hose
->io_base_phys
;
434 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
436 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
437 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
438 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
439 vma
->vm_end
- vma
->vm_start
,
443 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
444 const struct resource
*rsrc
,
445 resource_size_t
*start
, resource_size_t
*end
)
447 struct pci_bus_region region
;
449 if (rsrc
->flags
& IORESOURCE_IO
) {
450 pcibios_resource_to_bus(dev
->bus
, ®ion
,
451 (struct resource
*) rsrc
);
452 *start
= region
.start
;
457 /* We pass a CPU physical address to userland for MMIO instead of a
458 * BAR value because X is lame and expects to be able to use that
459 * to pass to /dev/mem!
461 * That means we may have 64-bit values where some apps only expect
462 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
464 *start
= rsrc
->start
;
469 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
470 * @hose: newly allocated pci_controller to be setup
471 * @dev: device node of the host bridge
472 * @primary: set if primary bus (32 bits only, soon to be deprecated)
474 * This function will parse the "ranges" property of a PCI host bridge device
475 * node and setup the resource mapping of a pci controller based on its
478 * Life would be boring if it wasn't for a few issues that we have to deal
481 * - We can only cope with one IO space range and up to 3 Memory space
482 * ranges. However, some machines (thanks Apple !) tend to split their
483 * space into lots of small contiguous ranges. So we have to coalesce.
485 * - We can only cope with all memory ranges having the same offset
486 * between CPU addresses and PCI addresses. Unfortunately, some bridges
487 * are setup for a large 1:1 mapping along with a small "window" which
488 * maps PCI address 0 to some arbitrary high address of the CPU space in
489 * order to give access to the ISA memory hole.
490 * The way out of here that I've chosen for now is to always set the
491 * offset based on the first resource found, then override it if we
492 * have a different offset and the previous was set by an ISA hole.
494 * - Some busses have IO space not starting at 0, which causes trouble with
495 * the way we do our IO resource renumbering. The code somewhat deals with
496 * it for 64 bits but I would expect problems on 32 bits.
498 * - Some 32 bits platforms such as 4xx can have physical space larger than
499 * 32 bits so we need to use 64 bits values for the parsing
501 void pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
502 struct device_node
*dev
, int primary
)
504 int memno
= 0, isa_hole
= -1;
505 unsigned long long isa_mb
= 0;
506 struct resource
*res
;
507 struct of_pci_range range
;
508 struct of_pci_range_parser parser
;
510 pr_info("PCI host bridge %s %s ranges:\n",
511 dev
->full_name
, primary
? "(primary)" : "");
513 /* Check for ranges property */
514 if (of_pci_range_parser_init(&parser
, dev
))
517 pr_debug("Parsing ranges property...\n");
518 for_each_of_pci_range(&parser
, &range
) {
519 /* Read next ranges element */
520 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
521 range
.pci_space
, range
.pci_addr
);
522 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
523 range
.cpu_addr
, range
.size
);
525 /* If we failed translation or got a zero-sized region
526 * (some FW try to feed us with non sensical zero sized regions
527 * such as power3 which look like some kind of attempt
528 * at exposing the VGA memory hole)
530 if (range
.cpu_addr
== OF_BAD_ADDR
|| range
.size
== 0)
533 /* Act based on address space type */
535 switch (range
.flags
& IORESOURCE_TYPE_BITS
) {
537 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
538 range
.cpu_addr
, range
.cpu_addr
+ range
.size
- 1,
541 /* We support only one IO range */
542 if (hose
->pci_io_size
) {
543 pr_info(" \\--> Skipped (too many) !\n");
546 /* On 32 bits, limit I/O space to 16MB */
547 if (range
.size
> 0x01000000)
548 range
.size
= 0x01000000;
550 /* 32 bits needs to map IOs here */
551 hose
->io_base_virt
= ioremap(range
.cpu_addr
,
554 /* Expect trouble if pci_addr is not 0 */
557 (unsigned long)hose
->io_base_virt
;
558 /* pci_io_size and io_base_phys always represent IO
559 * space starting at 0 so we factor in pci_addr
561 hose
->pci_io_size
= range
.pci_addr
+ range
.size
;
562 hose
->io_base_phys
= range
.cpu_addr
- range
.pci_addr
;
565 res
= &hose
->io_resource
;
566 range
.cpu_addr
= range
.pci_addr
;
570 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
571 range
.cpu_addr
, range
.cpu_addr
+ range
.size
- 1,
573 (range
.pci_space
& 0x40000000) ?
576 /* We support only 3 memory ranges */
578 pr_info(" \\--> Skipped (too many) !\n");
581 /* Handles ISA memory hole space here */
582 if (range
.pci_addr
== 0) {
583 isa_mb
= range
.cpu_addr
;
585 if (primary
|| isa_mem_base
== 0)
586 isa_mem_base
= range
.cpu_addr
;
587 hose
->isa_mem_phys
= range
.cpu_addr
;
588 hose
->isa_mem_size
= range
.size
;
591 /* We get the PCI/Mem offset from the first range or
592 * the, current one if the offset came from an ISA
593 * hole. If they don't match, bugger.
596 (isa_hole
>= 0 && range
.pci_addr
!= 0 &&
597 hose
->pci_mem_offset
== isa_mb
))
598 hose
->pci_mem_offset
= range
.cpu_addr
-
600 else if (range
.pci_addr
!= 0 &&
601 hose
->pci_mem_offset
!= range
.cpu_addr
-
603 pr_info(" \\--> Skipped (offset mismatch) !\n");
608 res
= &hose
->mem_resources
[memno
++];
612 res
->name
= dev
->full_name
;
613 res
->flags
= range
.flags
;
614 res
->start
= range
.cpu_addr
;
615 res
->end
= range
.cpu_addr
+ range
.size
- 1;
616 res
->parent
= res
->child
= res
->sibling
= NULL
;
620 /* If there's an ISA hole and the pci_mem_offset is -not- matching
621 * the ISA hole offset, then we need to remove the ISA hole from
622 * the resource list for that brige
624 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
625 unsigned int next
= isa_hole
+ 1;
626 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb
);
628 memmove(&hose
->mem_resources
[isa_hole
],
629 &hose
->mem_resources
[next
],
630 sizeof(struct resource
) * (memno
- next
));
631 hose
->mem_resources
[--memno
].flags
= 0;
635 /* Decide whether to display the domain number in /proc */
636 int pci_proc_domain(struct pci_bus
*bus
)
641 /* This header fixup will do the resource fixup for all devices as they are
642 * probed, but not for bridge ranges
644 static void pcibios_fixup_resources(struct pci_dev
*dev
)
646 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
650 pr_err("No host bridge for PCI dev %s !\n",
654 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
655 struct resource
*res
= dev
->resource
+ i
;
658 if (res
->start
== 0) {
659 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
661 (unsigned long long)res
->start
,
662 (unsigned long long)res
->end
,
663 (unsigned int)res
->flags
);
664 pr_debug("is unassigned\n");
665 res
->end
-= res
->start
;
667 res
->flags
|= IORESOURCE_UNSET
;
671 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
673 (unsigned long long)res
->start
,
674 (unsigned long long)res
->end
,
675 (unsigned int)res
->flags
);
678 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
680 /* This function tries to figure out if a bridge resource has been initialized
681 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
682 * things go more smoothly when it gets it right. It should covers cases such
683 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
685 static int pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
686 struct resource
*res
)
688 struct pci_controller
*hose
= pci_bus_to_host(bus
);
689 struct pci_dev
*dev
= bus
->self
;
690 resource_size_t offset
;
694 /* Job is a bit different between memory and IO */
695 if (res
->flags
& IORESOURCE_MEM
) {
696 /* If the BAR is non-0 (res != pci_mem_offset) then it's
697 * probably been initialized by somebody
699 if (res
->start
!= hose
->pci_mem_offset
)
702 /* The BAR is 0, let's check if memory decoding is enabled on
703 * the bridge. If not, we consider it unassigned
705 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
706 if ((command
& PCI_COMMAND_MEMORY
) == 0)
709 /* Memory decoding is enabled and the BAR is 0. If any of
710 * the bridge resources covers that starting address (0 then
711 * it's good enough for us for memory
713 for (i
= 0; i
< 3; i
++) {
714 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
715 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
719 /* Well, it starts at 0 and we know it will collide so we may as
720 * well consider it as unassigned. That covers the Apple case.
724 /* If the BAR is non-0, then we consider it assigned */
725 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
726 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
729 /* Here, we are a bit different than memory as typically IO
730 * space starting at low addresses -is- valid. What we do
731 * instead if that we consider as unassigned anything that
732 * doesn't have IO enabled in the PCI command register,
735 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
736 if (command
& PCI_COMMAND_IO
)
739 /* It's starting at 0 and IO is disabled in the bridge, consider
746 /* Fixup resources of a PCI<->PCI bridge */
747 static void pcibios_fixup_bridge(struct pci_bus
*bus
)
749 struct resource
*res
;
752 struct pci_dev
*dev
= bus
->self
;
754 pci_bus_for_each_resource(bus
, res
, i
) {
759 if (i
>= 3 && bus
->self
->transparent
)
762 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
764 (unsigned long long)res
->start
,
765 (unsigned long long)res
->end
,
766 (unsigned int)res
->flags
);
768 /* Try to detect uninitialized P2P bridge resources,
769 * and clear them out so they get re-assigned later
771 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
773 pr_debug("PCI:%s (unassigned)\n",
776 pr_debug("PCI:%s %016llx-%016llx\n",
778 (unsigned long long)res
->start
,
779 (unsigned long long)res
->end
);
784 void pcibios_setup_bus_self(struct pci_bus
*bus
)
786 /* Fix up the bus resources for P2P bridges */
787 if (bus
->self
!= NULL
)
788 pcibios_fixup_bridge(bus
);
791 void pcibios_setup_bus_devices(struct pci_bus
*bus
)
795 pr_debug("PCI: Fixup bus devices %d (%s)\n",
796 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
798 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
799 /* Setup OF node pointer in archdata */
800 dev
->dev
.of_node
= pci_device_to_OF_node(dev
);
802 /* Fixup NUMA node as it may not be setup yet by the generic
803 * code and is needed by the DMA init
805 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
807 /* Read default IRQs and fixup if necessary */
808 dev
->irq
= of_irq_parse_and_map_pci(dev
, 0, 0);
812 void pcibios_fixup_bus(struct pci_bus
*bus
)
816 EXPORT_SYMBOL(pcibios_fixup_bus
);
819 * We need to avoid collisions with `mirrored' VGA ports
820 * and other strange ISA hardware, so we always want the
821 * addresses to be allocated in the 0x000-0x0ff region
824 * Why? Because some silly external IO cards only decode
825 * the low 10 bits of the IO address. The 0x00-0xff region
826 * is reserved for motherboard devices that decode all 16
827 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
828 * but we want to try to avoid allocating at 0x2900-0x2bff
829 * which might have be mirrored at 0x0100-0x03ff..
831 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
832 resource_size_t size
, resource_size_t align
)
836 EXPORT_SYMBOL(pcibios_align_resource
);
838 int pcibios_add_device(struct pci_dev
*dev
)
840 dev
->irq
= of_irq_parse_and_map_pci(dev
, 0, 0);
844 EXPORT_SYMBOL(pcibios_add_device
);
847 * Reparent resource children of pr that conflict with res
848 * under res, and make res replace those children.
850 static int __init
reparent_resources(struct resource
*parent
,
851 struct resource
*res
)
853 struct resource
*p
, **pp
;
854 struct resource
**firstpp
= NULL
;
856 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
857 if (p
->end
< res
->start
)
859 if (res
->end
< p
->start
)
861 if (p
->start
< res
->start
|| p
->end
> res
->end
)
862 return -1; /* not completely contained */
867 return -1; /* didn't find any conflicting entries? */
868 res
->parent
= parent
;
869 res
->child
= *firstpp
;
873 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
875 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
877 (unsigned long long)p
->start
,
878 (unsigned long long)p
->end
, res
->name
);
884 * Handle resources of PCI devices. If the world were perfect, we could
885 * just allocate all the resource regions and do nothing more. It isn't.
886 * On the other hand, we cannot just re-allocate all devices, as it would
887 * require us to know lots of host bridge internals. So we attempt to
888 * keep as much of the original configuration as possible, but tweak it
889 * when it's found to be wrong.
891 * Known BIOS problems we have to work around:
892 * - I/O or memory regions not configured
893 * - regions configured, but not enabled in the command register
894 * - bogus I/O addresses above 64K used
895 * - expansion ROMs left enabled (this may sound harmless, but given
896 * the fact the PCI specs explicitly allow address decoders to be
897 * shared between expansion ROMs and other resource regions, it's
898 * at least dangerous)
901 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
902 * This gives us fixed barriers on where we can allocate.
903 * (2) Allocate resources for all enabled devices. If there is
904 * a collision, just mark the resource as unallocated. Also
905 * disable expansion ROMs during this step.
906 * (3) Try to allocate resources for disabled devices. If the
907 * resources were assigned correctly, everything goes well,
908 * if they weren't, they won't disturb allocation of other
910 * (4) Assign new addresses to resources which were either
911 * not configured at all or misconfigured. If explicitly
912 * requested by the user, configure expansion ROM address
916 static void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
920 struct resource
*res
, *pr
;
922 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
923 pci_domain_nr(bus
), bus
->number
);
925 pci_bus_for_each_resource(bus
, res
, i
) {
926 if (!res
|| !res
->flags
927 || res
->start
> res
->end
|| res
->parent
)
929 if (bus
->parent
== NULL
)
930 pr
= (res
->flags
& IORESOURCE_IO
) ?
931 &ioport_resource
: &iomem_resource
;
933 /* Don't bother with non-root busses when
934 * re-assigning all resources. We clear the
935 * resource flags as if they were colliding
936 * and as such ensure proper re-allocation
939 pr
= pci_find_parent_resource(bus
->self
, res
);
941 /* this happens when the generic PCI
942 * code (wrongly) decides that this
943 * bridge is transparent -- paulus
949 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
950 bus
->self
? pci_name(bus
->self
) : "PHB",
952 (unsigned long long)res
->start
,
953 (unsigned long long)res
->end
);
954 pr_debug("[0x%x], parent %p (%s)\n",
955 (unsigned int)res
->flags
,
956 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
958 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
959 struct pci_dev
*dev
= bus
->self
;
961 if (request_resource(pr
, res
) == 0)
964 * Must be a conflict with an existing entry.
965 * Move that entry (or entries) under the
966 * bridge resource and try again.
968 if (reparent_resources(pr
, res
) == 0)
971 if (dev
&& i
< PCI_BRIDGE_RESOURCE_NUM
&&
972 pci_claim_bridge_resource(dev
,
973 i
+ PCI_BRIDGE_RESOURCES
) == 0)
977 pr_warn("PCI: Cannot allocate resource region ");
978 pr_cont("%d of PCI bridge %d, will remap\n", i
, bus
->number
);
979 res
->start
= res
->end
= 0;
983 list_for_each_entry(b
, &bus
->children
, node
)
984 pcibios_allocate_bus_resources(b
);
987 static inline void alloc_resource(struct pci_dev
*dev
, int idx
)
989 struct resource
*pr
, *r
= &dev
->resource
[idx
];
991 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
993 (unsigned long long)r
->start
,
994 (unsigned long long)r
->end
,
995 (unsigned int)r
->flags
);
997 pr
= pci_find_parent_resource(dev
, r
);
998 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
999 request_resource(pr
, r
) < 0) {
1000 pr_warn("PCI: Cannot allocate resource region %d ", idx
);
1001 pr_cont("of device %s, will remap\n", pci_name(dev
));
1003 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1005 (unsigned long long)pr
->start
,
1006 (unsigned long long)pr
->end
,
1007 (unsigned int)pr
->flags
);
1008 /* We'll assign a new address later */
1009 r
->flags
|= IORESOURCE_UNSET
;
1015 static void __init
pcibios_allocate_resources(int pass
)
1017 struct pci_dev
*dev
= NULL
;
1022 for_each_pci_dev(dev
) {
1023 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1024 for (idx
= 0; idx
<= PCI_ROM_RESOURCE
; idx
++) {
1025 r
= &dev
->resource
[idx
];
1026 if (r
->parent
) /* Already allocated */
1028 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1029 continue; /* Not assigned at all */
1030 /* We only allocate ROMs on pass 1 just in case they
1031 * have been screwed up by firmware
1033 if (idx
== PCI_ROM_RESOURCE
)
1035 if (r
->flags
& IORESOURCE_IO
)
1036 disabled
= !(command
& PCI_COMMAND_IO
);
1038 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1039 if (pass
== disabled
)
1040 alloc_resource(dev
, idx
);
1044 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1046 /* Turn the ROM off, leave the resource region,
1047 * but keep it unregistered.
1050 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1051 if (reg
& PCI_ROM_ADDRESS_ENABLE
) {
1052 pr_debug("PCI: Switching off ROM of %s\n",
1054 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1055 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1056 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1062 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1064 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1065 resource_size_t offset
;
1066 struct resource
*res
, *pres
;
1069 pr_debug("Reserving legacy ranges for domain %04x\n",
1070 pci_domain_nr(bus
));
1073 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1075 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1076 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1077 BUG_ON(res
== NULL
);
1078 res
->name
= "Legacy IO";
1079 res
->flags
= IORESOURCE_IO
;
1080 res
->start
= offset
;
1081 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1082 pr_debug("Candidate legacy IO: %pR\n", res
);
1083 if (request_resource(&hose
->io_resource
, res
)) {
1084 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1085 pci_domain_nr(bus
), bus
->number
, res
);
1090 /* Check for memory */
1091 offset
= hose
->pci_mem_offset
;
1092 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset
);
1093 for (i
= 0; i
< 3; i
++) {
1094 pres
= &hose
->mem_resources
[i
];
1095 if (!(pres
->flags
& IORESOURCE_MEM
))
1097 pr_debug("hose mem res: %pR\n", pres
);
1098 if ((pres
->start
- offset
) <= 0xa0000 &&
1099 (pres
->end
- offset
) >= 0xbffff)
1104 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1105 BUG_ON(res
== NULL
);
1106 res
->name
= "Legacy VGA memory";
1107 res
->flags
= IORESOURCE_MEM
;
1108 res
->start
= 0xa0000 + offset
;
1109 res
->end
= 0xbffff + offset
;
1110 pr_debug("Candidate VGA memory: %pR\n", res
);
1111 if (request_resource(pres
, res
)) {
1112 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1113 pci_domain_nr(bus
), bus
->number
, res
);
1118 void __init
pcibios_resource_survey(void)
1122 /* Allocate and assign resources. If we re-assign everything, then
1123 * we skip the allocate phase
1125 list_for_each_entry(b
, &pci_root_buses
, node
)
1126 pcibios_allocate_bus_resources(b
);
1128 pcibios_allocate_resources(0);
1129 pcibios_allocate_resources(1);
1131 /* Before we start assigning unassigned resource, we try to reserve
1132 * the low IO area and the VGA memory area if they intersect the
1133 * bus available resources to avoid allocating things on top of them
1135 list_for_each_entry(b
, &pci_root_buses
, node
)
1136 pcibios_reserve_legacy_regions(b
);
1138 /* Now proceed to assigning things that were left unassigned */
1139 pr_debug("PCI: Assigning unassigned resources...\n");
1140 pci_assign_unassigned_resources();
1143 /* This is used by the PCI hotplug driver to allocate resource
1144 * of newly plugged busses. We can try to consolidate with the
1145 * rest of the code later, for now, keep it as-is as our main
1146 * resource allocation function doesn't deal with sub-trees yet.
1148 void pcibios_claim_one_bus(struct pci_bus
*bus
)
1150 struct pci_dev
*dev
;
1151 struct pci_bus
*child_bus
;
1153 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1156 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1157 struct resource
*r
= &dev
->resource
[i
];
1159 if (r
->parent
|| !r
->start
|| !r
->flags
)
1162 pr_debug("PCI: Claiming %s: ", pci_name(dev
));
1163 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1164 i
, (unsigned long long)r
->start
,
1165 (unsigned long long)r
->end
,
1166 (unsigned int)r
->flags
);
1168 if (pci_claim_resource(dev
, i
) == 0)
1171 pci_claim_bridge_resource(dev
, i
);
1175 list_for_each_entry(child_bus
, &bus
->children
, node
)
1176 pcibios_claim_one_bus(child_bus
);
1178 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1181 /* pcibios_finish_adding_to_bus
1183 * This is to be called by the hotplug code after devices have been
1184 * added to a bus, this include calling it for a PHB that is just
1187 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1189 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1190 pci_domain_nr(bus
), bus
->number
);
1192 /* Allocate bus and devices resources */
1193 pcibios_allocate_bus_resources(bus
);
1194 pcibios_claim_one_bus(bus
);
1196 /* Add new devices to global lists. Register in proc, sysfs. */
1197 pci_bus_add_devices(bus
);
1200 /* eeh_add_device_tree_late(bus); */
1202 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1204 static void pcibios_setup_phb_resources(struct pci_controller
*hose
,
1205 struct list_head
*resources
)
1207 unsigned long io_offset
;
1208 struct resource
*res
;
1211 /* Hookup PHB IO resource */
1212 res
= &hose
->io_resource
;
1214 /* Fixup IO space offset */
1215 io_offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1216 res
->start
= (res
->start
+ io_offset
) & 0xffffffffu
;
1217 res
->end
= (res
->end
+ io_offset
) & 0xffffffffu
;
1220 pr_warn("PCI: I/O resource not set for host ");
1221 pr_cont("bridge %s (domain %d)\n",
1222 hose
->dn
->full_name
, hose
->global_number
);
1223 /* Workaround for lack of IO resource only on 32-bit */
1224 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1225 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1226 res
->flags
= IORESOURCE_IO
;
1228 pci_add_resource_offset(resources
, res
,
1229 (__force resource_size_t
)(hose
->io_base_virt
- _IO_BASE
));
1231 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1232 (unsigned long long)res
->start
,
1233 (unsigned long long)res
->end
,
1234 (unsigned long)res
->flags
);
1236 /* Hookup PHB Memory resources */
1237 for (i
= 0; i
< 3; ++i
) {
1238 res
= &hose
->mem_resources
[i
];
1242 pr_err("PCI: Memory resource 0 not set for ");
1243 pr_cont("host bridge %s (domain %d)\n",
1244 hose
->dn
->full_name
, hose
->global_number
);
1246 /* Workaround for lack of MEM resource only on 32-bit */
1247 res
->start
= hose
->pci_mem_offset
;
1248 res
->end
= (resource_size_t
)-1LL;
1249 res
->flags
= IORESOURCE_MEM
;
1252 pci_add_resource_offset(resources
, res
, hose
->pci_mem_offset
);
1254 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1255 i
, (unsigned long long)res
->start
,
1256 (unsigned long long)res
->end
,
1257 (unsigned long)res
->flags
);
1260 pr_debug("PCI: PHB MEM offset = %016llx\n",
1261 (unsigned long long)hose
->pci_mem_offset
);
1262 pr_debug("PCI: PHB IO offset = %08lx\n",
1263 (unsigned long)hose
->io_base_virt
- _IO_BASE
);
1266 static void pcibios_scan_phb(struct pci_controller
*hose
)
1268 LIST_HEAD(resources
);
1269 struct pci_bus
*bus
;
1270 struct device_node
*node
= hose
->dn
;
1272 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node
));
1274 pcibios_setup_phb_resources(hose
, &resources
);
1276 bus
= pci_scan_root_bus(hose
->parent
, hose
->first_busno
,
1277 hose
->ops
, hose
, &resources
);
1279 pr_err("Failed to create bus for PCI domain %04x\n",
1280 hose
->global_number
);
1281 pci_free_resource_list(&resources
);
1284 bus
->busn_res
.start
= hose
->first_busno
;
1287 hose
->last_busno
= bus
->busn_res
.end
;
1290 static int __init
pcibios_init(void)
1292 struct pci_controller
*hose
, *tmp
;
1295 pr_info("PCI: Probing PCI hardware\n");
1297 /* Scan all of the recorded PCI controllers. */
1298 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1299 hose
->last_busno
= 0xff;
1300 pcibios_scan_phb(hose
);
1301 if (next_busno
<= hose
->last_busno
)
1302 next_busno
= hose
->last_busno
+ 1;
1304 pci_bus_count
= next_busno
;
1306 /* Call common code to handle resource allocation */
1307 pcibios_resource_survey();
1308 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1310 pci_bus_add_devices(hose
->bus
);
1316 subsys_initcall(pcibios_init
);
1318 static struct pci_controller
*pci_bus_to_hose(int bus
)
1320 struct pci_controller
*hose
, *tmp
;
1322 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1323 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
1328 /* Provide information on locations of various I/O regions in physical
1329 * memory. Do this on a per-card basis so that we choose the right
1331 * Note that the returned IO or memory base is a physical address
1334 long sys_pciconfig_iobase(long which
, unsigned long bus
, unsigned long devfn
)
1336 struct pci_controller
*hose
;
1337 long result
= -EOPNOTSUPP
;
1339 hose
= pci_bus_to_hose(bus
);
1344 case IOBASE_BRIDGE_NUMBER
:
1345 return (long)hose
->first_busno
;
1347 return (long)hose
->pci_mem_offset
;
1349 return (long)hose
->io_base_phys
;
1351 return (long)isa_io_base
;
1352 case IOBASE_ISA_MEM
:
1353 return (long)isa_mem_base
;
1360 * Null PCI config access functions, for the case when we can't
1363 #define NULL_PCI_OP(rw, size, type) \
1365 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1367 return PCIBIOS_DEVICE_NOT_FOUND; \
1371 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1374 return PCIBIOS_DEVICE_NOT_FOUND
;
1378 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1381 return PCIBIOS_DEVICE_NOT_FOUND
;
1384 static struct pci_ops null_pci_ops
= {
1385 .read
= null_read_config
,
1386 .write
= null_write_config
,
1390 * These functions are used early on before PCI scanning is done
1391 * and all of the pci_dev and pci_bus structures have been created.
1393 static struct pci_bus
*
1394 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1396 static struct pci_bus bus
;
1399 pr_err("Can't find hose for PCI bus %d!\n", busnr
);
1403 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1407 #define EARLY_PCI_OP(rw, size, type) \
1408 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1409 int devfn, int offset, type value) \
1411 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1412 devfn, offset, value); \
1415 EARLY_PCI_OP(read
, byte
, u8
*)
1416 EARLY_PCI_OP(read
, word
, u16
*)
1417 EARLY_PCI_OP(read
, dword
, u32
*)
1418 EARLY_PCI_OP(write
, byte
, u8
)
1419 EARLY_PCI_OP(write
, word
, u16
)
1420 EARLY_PCI_OP(write
, dword
, u32
)
1422 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
1425 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);