4 * Exposes all configurable internal clock sources to the clk framework.
7 * - Root source, usually 12MHz supplied by an external crystal
8 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
11 * - 6 clock dividers with:
12 * * selectable source [one of the PLLs],
13 * * output divided between [2 .. 512 in steps of 2] (!Au1300)
14 * or [1 .. 256 in steps of 1] (Au1300),
15 * * can be enabled individually.
17 * - up to 6 "internal" (fixed) consumers which:
18 * * take either AUXPLL or one of the above 6 dividers as input,
19 * * divide this input by 1, 2, or 4 (and 3 on Au1300).
20 * * can be disabled separately.
23 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
24 * depends on board design and should be set by bootloader, read-only.
25 * - peripheral clock: half the rate of sysbus clock, source for a lot
26 * of peripheral blocks, read-only.
27 * - memory clock: clk rate to main memory chips, depends on board
28 * design and is read-only,
29 * - lrclk: the static bus clock signal for synchronous operation.
30 * depends on board design, must be set by bootloader,
31 * but may be required to correctly configure devices attached to
32 * the static bus. The Au1000/1500/1100 manuals call it LCLK, on
33 * later models it's called RCLK.
36 #include <linux/init.h>
38 #include <linux/clk-provider.h>
39 #include <linux/clkdev.h>
40 #include <linux/clk-private.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/types.h>
44 #include <asm/mach-au1x00/au1000.h>
46 /* Base clock: 12MHz is the default in all databooks, and I haven't
47 * found any board yet which uses a different rate.
49 #define ALCHEMY_ROOTCLK_RATE 12000000
52 * the internal sources which can be driven by the PLLs and dividers.
53 * Names taken from the databooks, refer to them for more information,
54 * especially which ones are share a clock line.
56 static const char * const alchemy_au1300_intclknames
[] = {
57 "lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk",
61 static const char * const alchemy_au1200_intclknames
[] = {
62 "lcd_intclk", NULL
, NULL
, NULL
, "EXTCLK0", "EXTCLK1"
65 static const char * const alchemy_au1550_intclknames
[] = {
66 "usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko",
70 static const char * const alchemy_au1100_intclknames
[] = {
71 "usb_clk", "lcd_intclk", NULL
, "i2s_clk", "EXTCLK0", "EXTCLK1"
74 static const char * const alchemy_au1500_intclknames
[] = {
75 NULL
, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1"
78 static const char * const alchemy_au1000_intclknames
[] = {
79 "irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0",
83 /* aliases for a few on-chip sources which are either shared
84 * or have gone through name changes.
86 static struct clk_aliastable
{
90 } alchemy_clk_aliases
[] __initdata
= {
91 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
92 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
93 { "irda_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
94 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1550
},
95 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1550
},
96 { "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550
},
97 { "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550
},
98 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200
},
99 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200
},
100 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300
},
101 { "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300
},
102 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300
},
103 { "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300
},
108 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))
110 /* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
111 static spinlock_t alchemy_clk_fg0_lock
;
112 static spinlock_t alchemy_clk_fg1_lock
;
113 static spinlock_t alchemy_clk_csrc_lock
;
115 /* CPU Core clock *****************************************************/
117 static unsigned long alchemy_clk_cpu_recalc(struct clk_hw
*hw
,
118 unsigned long parent_rate
)
123 * On early Au1000, sys_cpupll was write-only. Since these
124 * silicon versions of Au1000 are not sold, we don't bend
125 * over backwards trying to determine the frequency.
127 if (unlikely(au1xxx_cpu_has_pll_wo()))
130 t
= alchemy_rdsys(AU1000_SYS_CPUPLL
) & 0x7f;
137 static struct clk_ops alchemy_clkops_cpu
= {
138 .recalc_rate
= alchemy_clk_cpu_recalc
,
141 static struct clk __init
*alchemy_clk_setup_cpu(const char *parent_name
,
144 struct clk_init_data id
;
147 h
= kzalloc(sizeof(*h
), GFP_KERNEL
);
149 return ERR_PTR(-ENOMEM
);
151 id
.name
= ALCHEMY_CPU_CLK
;
152 id
.parent_names
= &parent_name
;
154 id
.flags
= CLK_IS_BASIC
;
155 id
.ops
= &alchemy_clkops_cpu
;
158 return clk_register(NULL
, h
);
161 /* AUXPLLs ************************************************************/
163 struct alchemy_auxpll_clk
{
165 unsigned long reg
; /* au1300 has also AUXPLL2 */
166 int maxmult
; /* max multiplier */
168 #define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
170 static unsigned long alchemy_clk_aux_recalc(struct clk_hw
*hw
,
171 unsigned long parent_rate
)
173 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
175 return (alchemy_rdsys(a
->reg
) & 0xff) * parent_rate
;
178 static int alchemy_clk_aux_setr(struct clk_hw
*hw
,
180 unsigned long parent_rate
)
182 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
183 unsigned long d
= rate
;
190 /* minimum is 84MHz, max is 756-1032 depending on variant */
191 if (((d
< 7) && (d
!= 0)) || (d
> a
->maxmult
))
194 alchemy_wrsys(d
, a
->reg
);
198 static long alchemy_clk_aux_roundr(struct clk_hw
*hw
,
200 unsigned long *parent_rate
)
202 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
205 if (!rate
|| !*parent_rate
)
208 mult
= rate
/ (*parent_rate
);
210 if (mult
&& (mult
< 7))
212 if (mult
> a
->maxmult
)
215 return (*parent_rate
) * mult
;
218 static struct clk_ops alchemy_clkops_aux
= {
219 .recalc_rate
= alchemy_clk_aux_recalc
,
220 .set_rate
= alchemy_clk_aux_setr
,
221 .round_rate
= alchemy_clk_aux_roundr
,
224 static struct clk __init
*alchemy_clk_setup_aux(const char *parent_name
,
225 char *name
, int maxmult
,
228 struct clk_init_data id
;
230 struct alchemy_auxpll_clk
*a
;
232 a
= kzalloc(sizeof(*a
), GFP_KERNEL
);
234 return ERR_PTR(-ENOMEM
);
237 id
.parent_names
= &parent_name
;
239 id
.flags
= CLK_GET_RATE_NOCACHE
;
240 id
.ops
= &alchemy_clkops_aux
;
243 a
->maxmult
= maxmult
;
246 c
= clk_register(NULL
, &a
->hw
);
248 clk_register_clkdev(c
, name
, NULL
);
255 /* sysbus_clk *********************************************************/
257 static struct clk __init
*alchemy_clk_setup_sysbus(const char *pn
)
259 unsigned long v
= (alchemy_rdsys(AU1000_SYS_POWERCTRL
) & 3) + 2;
262 c
= clk_register_fixed_factor(NULL
, ALCHEMY_SYSBUS_CLK
,
265 clk_register_clkdev(c
, ALCHEMY_SYSBUS_CLK
, NULL
);
269 /* Peripheral Clock ***************************************************/
271 static struct clk __init
*alchemy_clk_setup_periph(const char *pn
)
273 /* Peripheral clock runs at half the rate of sysbus clk */
276 c
= clk_register_fixed_factor(NULL
, ALCHEMY_PERIPH_CLK
,
279 clk_register_clkdev(c
, ALCHEMY_PERIPH_CLK
, NULL
);
283 /* mem clock **********************************************************/
285 static struct clk __init
*alchemy_clk_setup_mem(const char *pn
, int ct
)
287 void __iomem
*addr
= IOMEM(AU1000_MEM_PHYS_ADDR
);
293 case ALCHEMY_CPU_AU1550
:
294 case ALCHEMY_CPU_AU1200
:
295 v
= __raw_readl(addr
+ AU1550_MEM_SDCONFIGB
);
296 div
= (v
& (1 << 15)) ? 1 : 2;
298 case ALCHEMY_CPU_AU1300
:
299 v
= __raw_readl(addr
+ AU1550_MEM_SDCONFIGB
);
300 div
= (v
& (1 << 31)) ? 1 : 2;
302 case ALCHEMY_CPU_AU1000
:
303 case ALCHEMY_CPU_AU1500
:
304 case ALCHEMY_CPU_AU1100
:
310 c
= clk_register_fixed_factor(NULL
, ALCHEMY_MEM_CLK
, pn
,
313 clk_register_clkdev(c
, ALCHEMY_MEM_CLK
, NULL
);
317 /* lrclk: external synchronous static bus clock ***********************/
319 static struct clk __init
*alchemy_clk_setup_lrclk(const char *pn
)
321 /* MEM_STCFG0[15:13] = divisor.
322 * L/RCLK = periph_clk / (divisor + 1)
323 * On Au1000, Au1500, Au1100 it's called LCLK,
324 * on later models it's called RCLK, but it's the same thing.
327 unsigned long v
= alchemy_rdsmem(AU1000_MEM_STCFG0
) >> 13;
330 c
= clk_register_fixed_factor(NULL
, ALCHEMY_LR_CLK
,
333 clk_register_clkdev(c
, ALCHEMY_LR_CLK
, NULL
);
337 /* Clock dividers and muxes *******************************************/
339 /* data for fgen and csrc mux-dividers */
340 struct alchemy_fgcs_clk
{
342 spinlock_t
*reglock
; /* register lock */
343 unsigned long reg
; /* SYS_FREQCTRL0/1 */
344 int shift
; /* offset in register */
345 int parent
; /* parent before disable [Au1300] */
346 int isen
; /* is it enabled? */
347 int *dt
; /* dividertable for csrc */
349 #define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw)
351 static long alchemy_calc_div(unsigned long rate
, unsigned long prate
,
352 int scale
, int maxdiv
, unsigned long *rv
)
357 if ((prate
/ div1
) > rate
)
360 if (scale
== 2) { /* only div-by-multiple-of-2 possible */
362 div1
++; /* stay <=prate */
365 div2
= (div1
/ scale
) - 1; /* value to write to register */
372 div1
= ((div2
+ 1) * scale
);
376 static long alchemy_clk_fgcs_detr(struct clk_hw
*hw
, unsigned long rate
,
377 unsigned long *best_parent_rate
,
378 struct clk_hw
**best_parent_clk
,
379 int scale
, int maxdiv
)
381 struct clk
*pc
, *bpc
, *free
;
382 long tdv
, tpr
, pr
, nr
, br
, bpr
, diff
, lastdiff
;
391 /* look at the rates each enabled parent supplies and select
392 * the one that gets closest to but not over the requested rate.
394 for (j
= 0; j
< 7; j
++) {
395 pc
= clk_get_parent_by_index(hw
->clk
, j
);
399 /* if this parent is currently unused, remember it.
400 * XXX: I know it's a layering violation, but it works
401 * so well.. (if (!clk_has_active_children(pc)) )
403 if (pc
->prepare_count
== 0) {
408 pr
= clk_get_rate(pc
);
412 /* what can hardware actually provide */
413 tdv
= alchemy_calc_div(rate
, pr
, scale
, maxdiv
, NULL
);
419 if (diff
< lastdiff
) {
429 /* if we couldn't get the exact rate we wanted from the enabled
430 * parents, maybe we can tell an available disabled/inactive one
431 * to give us a rate we can divide down to the requested rate.
433 if (lastdiff
&& free
) {
434 for (j
= (maxdiv
== 4) ? 1 : scale
; j
<= maxdiv
; j
+= scale
) {
438 pr
= clk_round_rate(free
, tpr
);
440 tdv
= alchemy_calc_div(rate
, pr
, scale
, maxdiv
, NULL
);
445 if (diff
< lastdiff
) {
456 *best_parent_rate
= bpr
;
457 *best_parent_clk
= __clk_get_hw(bpc
);
461 static int alchemy_clk_fgv1_en(struct clk_hw
*hw
)
463 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
464 unsigned long v
, flags
;
466 spin_lock_irqsave(c
->reglock
, flags
);
467 v
= alchemy_rdsys(c
->reg
);
468 v
|= (1 << 1) << c
->shift
;
469 alchemy_wrsys(v
, c
->reg
);
470 spin_unlock_irqrestore(c
->reglock
, flags
);
475 static int alchemy_clk_fgv1_isen(struct clk_hw
*hw
)
477 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
478 unsigned long v
= alchemy_rdsys(c
->reg
) >> (c
->shift
+ 1);
483 static void alchemy_clk_fgv1_dis(struct clk_hw
*hw
)
485 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
486 unsigned long v
, flags
;
488 spin_lock_irqsave(c
->reglock
, flags
);
489 v
= alchemy_rdsys(c
->reg
);
490 v
&= ~((1 << 1) << c
->shift
);
491 alchemy_wrsys(v
, c
->reg
);
492 spin_unlock_irqrestore(c
->reglock
, flags
);
495 static int alchemy_clk_fgv1_setp(struct clk_hw
*hw
, u8 index
)
497 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
498 unsigned long v
, flags
;
500 spin_lock_irqsave(c
->reglock
, flags
);
501 v
= alchemy_rdsys(c
->reg
);
503 v
|= (1 << c
->shift
);
505 v
&= ~(1 << c
->shift
);
506 alchemy_wrsys(v
, c
->reg
);
507 spin_unlock_irqrestore(c
->reglock
, flags
);
512 static u8
alchemy_clk_fgv1_getp(struct clk_hw
*hw
)
514 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
516 return (alchemy_rdsys(c
->reg
) >> c
->shift
) & 1;
519 static int alchemy_clk_fgv1_setr(struct clk_hw
*hw
, unsigned long rate
,
520 unsigned long parent_rate
)
522 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
523 unsigned long div
, v
, flags
, ret
;
524 int sh
= c
->shift
+ 2;
526 if (!rate
|| !parent_rate
|| rate
> (parent_rate
/ 2))
528 ret
= alchemy_calc_div(rate
, parent_rate
, 2, 512, &div
);
529 spin_lock_irqsave(c
->reglock
, flags
);
530 v
= alchemy_rdsys(c
->reg
);
533 alchemy_wrsys(v
, c
->reg
);
534 spin_unlock_irqrestore(c
->reglock
, flags
);
539 static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw
*hw
,
540 unsigned long parent_rate
)
542 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
543 unsigned long v
= alchemy_rdsys(c
->reg
) >> (c
->shift
+ 2);
545 v
= ((v
& 0xff) + 1) * 2;
546 return parent_rate
/ v
;
549 static long alchemy_clk_fgv1_detr(struct clk_hw
*hw
, unsigned long rate
,
550 unsigned long *best_parent_rate
,
551 struct clk_hw
**best_parent_clk
)
553 return alchemy_clk_fgcs_detr(hw
, rate
, best_parent_rate
,
554 best_parent_clk
, 2, 512);
557 /* Au1000, Au1100, Au15x0, Au12x0 */
558 static struct clk_ops alchemy_clkops_fgenv1
= {
559 .recalc_rate
= alchemy_clk_fgv1_recalc
,
560 .determine_rate
= alchemy_clk_fgv1_detr
,
561 .set_rate
= alchemy_clk_fgv1_setr
,
562 .set_parent
= alchemy_clk_fgv1_setp
,
563 .get_parent
= alchemy_clk_fgv1_getp
,
564 .enable
= alchemy_clk_fgv1_en
,
565 .disable
= alchemy_clk_fgv1_dis
,
566 .is_enabled
= alchemy_clk_fgv1_isen
,
569 static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk
*c
)
571 unsigned long v
= alchemy_rdsys(c
->reg
);
573 v
&= ~(3 << c
->shift
);
574 v
|= (c
->parent
& 3) << c
->shift
;
575 alchemy_wrsys(v
, c
->reg
);
579 static int alchemy_clk_fgv2_en(struct clk_hw
*hw
)
581 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
584 /* enable by setting the previous parent clock */
585 spin_lock_irqsave(c
->reglock
, flags
);
586 __alchemy_clk_fgv2_en(c
);
587 spin_unlock_irqrestore(c
->reglock
, flags
);
592 static int alchemy_clk_fgv2_isen(struct clk_hw
*hw
)
594 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
596 return ((alchemy_rdsys(c
->reg
) >> c
->shift
) & 3) != 0;
599 static void alchemy_clk_fgv2_dis(struct clk_hw
*hw
)
601 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
602 unsigned long v
, flags
;
604 spin_lock_irqsave(c
->reglock
, flags
);
605 v
= alchemy_rdsys(c
->reg
);
606 v
&= ~(3 << c
->shift
); /* set input mux to "disabled" state */
607 alchemy_wrsys(v
, c
->reg
);
609 spin_unlock_irqrestore(c
->reglock
, flags
);
612 static int alchemy_clk_fgv2_setp(struct clk_hw
*hw
, u8 index
)
614 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
617 spin_lock_irqsave(c
->reglock
, flags
);
618 c
->parent
= index
+ 1; /* value to write to register */
620 __alchemy_clk_fgv2_en(c
);
621 spin_unlock_irqrestore(c
->reglock
, flags
);
626 static u8
alchemy_clk_fgv2_getp(struct clk_hw
*hw
)
628 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
629 unsigned long flags
, v
;
631 spin_lock_irqsave(c
->reglock
, flags
);
633 spin_unlock_irqrestore(c
->reglock
, flags
);
637 /* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the
638 * dividers behave exactly as on previous models (dividers are multiples
639 * of 2); with the bit set, dividers are multiples of 1, halving their
640 * range, but making them also much more flexible.
642 static int alchemy_clk_fgv2_setr(struct clk_hw
*hw
, unsigned long rate
,
643 unsigned long parent_rate
)
645 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
646 int sh
= c
->shift
+ 2;
647 unsigned long div
, v
, flags
, ret
;
649 if (!rate
|| !parent_rate
|| rate
> parent_rate
)
652 v
= alchemy_rdsys(c
->reg
) & (1 << 30); /* test "scale" bit */
653 ret
= alchemy_calc_div(rate
, parent_rate
, v
? 1 : 2,
654 v
? 256 : 512, &div
);
656 spin_lock_irqsave(c
->reglock
, flags
);
657 v
= alchemy_rdsys(c
->reg
);
659 v
|= (div
& 0xff) << sh
;
660 alchemy_wrsys(v
, c
->reg
);
661 spin_unlock_irqrestore(c
->reglock
, flags
);
666 static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw
*hw
,
667 unsigned long parent_rate
)
669 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
670 int sh
= c
->shift
+ 2;
673 v
= alchemy_rdsys(c
->reg
);
674 t
= parent_rate
/ (((v
>> sh
) & 0xff) + 1);
675 if ((v
& (1 << 30)) == 0) /* test scale bit */
681 static long alchemy_clk_fgv2_detr(struct clk_hw
*hw
, unsigned long rate
,
682 unsigned long *best_parent_rate
,
683 struct clk_hw
**best_parent_clk
)
685 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
688 if (alchemy_rdsys(c
->reg
) & (1 << 30)) {
696 return alchemy_clk_fgcs_detr(hw
, rate
, best_parent_rate
,
697 best_parent_clk
, scale
, maxdiv
);
700 /* Au1300 larger input mux, no separate disable bit, flexible divider */
701 static struct clk_ops alchemy_clkops_fgenv2
= {
702 .recalc_rate
= alchemy_clk_fgv2_recalc
,
703 .determine_rate
= alchemy_clk_fgv2_detr
,
704 .set_rate
= alchemy_clk_fgv2_setr
,
705 .set_parent
= alchemy_clk_fgv2_setp
,
706 .get_parent
= alchemy_clk_fgv2_getp
,
707 .enable
= alchemy_clk_fgv2_en
,
708 .disable
= alchemy_clk_fgv2_dis
,
709 .is_enabled
= alchemy_clk_fgv2_isen
,
712 static const char * const alchemy_clk_fgv1_parents
[] = {
713 ALCHEMY_CPU_CLK
, ALCHEMY_AUXPLL_CLK
716 static const char * const alchemy_clk_fgv2_parents
[] = {
717 ALCHEMY_AUXPLL2_CLK
, ALCHEMY_CPU_CLK
, ALCHEMY_AUXPLL_CLK
720 static const char * const alchemy_clk_fgen_names
[] = {
721 ALCHEMY_FG0_CLK
, ALCHEMY_FG1_CLK
, ALCHEMY_FG2_CLK
,
722 ALCHEMY_FG3_CLK
, ALCHEMY_FG4_CLK
, ALCHEMY_FG5_CLK
};
724 static int __init
alchemy_clk_init_fgens(int ctype
)
727 struct clk_init_data id
;
728 struct alchemy_fgcs_clk
*a
;
733 case ALCHEMY_CPU_AU1000
...ALCHEMY_CPU_AU1200
:
734 id
.ops
= &alchemy_clkops_fgenv1
;
735 id
.parent_names
= (const char **)alchemy_clk_fgv1_parents
;
738 case ALCHEMY_CPU_AU1300
:
739 id
.ops
= &alchemy_clkops_fgenv2
;
740 id
.parent_names
= (const char **)alchemy_clk_fgv2_parents
;
746 id
.flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
;
748 a
= kzalloc((sizeof(*a
)) * 6, GFP_KERNEL
);
752 spin_lock_init(&alchemy_clk_fg0_lock
);
753 spin_lock_init(&alchemy_clk_fg1_lock
);
755 for (i
= 0; i
< 6; i
++) {
756 id
.name
= alchemy_clk_fgen_names
[i
];
757 a
->shift
= 10 * (i
< 3 ? i
: i
- 3);
759 a
->reg
= AU1000_SYS_FREQCTRL1
;
760 a
->reglock
= &alchemy_clk_fg1_lock
;
762 a
->reg
= AU1000_SYS_FREQCTRL0
;
763 a
->reglock
= &alchemy_clk_fg0_lock
;
766 /* default to first parent if bootloader has set
767 * the mux to disabled state.
769 if (ctype
== ALCHEMY_CPU_AU1300
) {
770 v
= alchemy_rdsys(a
->reg
);
771 a
->parent
= (v
>> a
->shift
) & 3;
780 c
= clk_register(NULL
, &a
->hw
);
784 clk_register_clkdev(c
, id
.name
, NULL
);
791 /* internal sources muxes *********************************************/
793 static int alchemy_clk_csrc_isen(struct clk_hw
*hw
)
795 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
796 unsigned long v
= alchemy_rdsys(c
->reg
);
798 return (((v
>> c
->shift
) >> 2) & 7) != 0;
801 static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk
*c
)
803 unsigned long v
= alchemy_rdsys(c
->reg
);
805 v
&= ~((7 << 2) << c
->shift
);
806 v
|= ((c
->parent
& 7) << 2) << c
->shift
;
807 alchemy_wrsys(v
, c
->reg
);
811 static int alchemy_clk_csrc_en(struct clk_hw
*hw
)
813 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
816 /* enable by setting the previous parent clock */
817 spin_lock_irqsave(c
->reglock
, flags
);
818 __alchemy_clk_csrc_en(c
);
819 spin_unlock_irqrestore(c
->reglock
, flags
);
824 static void alchemy_clk_csrc_dis(struct clk_hw
*hw
)
826 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
827 unsigned long v
, flags
;
829 spin_lock_irqsave(c
->reglock
, flags
);
830 v
= alchemy_rdsys(c
->reg
);
831 v
&= ~((3 << 2) << c
->shift
); /* mux to "disabled" state */
832 alchemy_wrsys(v
, c
->reg
);
834 spin_unlock_irqrestore(c
->reglock
, flags
);
837 static int alchemy_clk_csrc_setp(struct clk_hw
*hw
, u8 index
)
839 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
842 spin_lock_irqsave(c
->reglock
, flags
);
843 c
->parent
= index
+ 1; /* value to write to register */
845 __alchemy_clk_csrc_en(c
);
846 spin_unlock_irqrestore(c
->reglock
, flags
);
851 static u8
alchemy_clk_csrc_getp(struct clk_hw
*hw
)
853 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
855 return c
->parent
- 1;
858 static unsigned long alchemy_clk_csrc_recalc(struct clk_hw
*hw
,
859 unsigned long parent_rate
)
861 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
862 unsigned long v
= (alchemy_rdsys(c
->reg
) >> c
->shift
) & 3;
864 return parent_rate
/ c
->dt
[v
];
867 static int alchemy_clk_csrc_setr(struct clk_hw
*hw
, unsigned long rate
,
868 unsigned long parent_rate
)
870 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
871 unsigned long d
, v
, flags
;
874 if (!rate
|| !parent_rate
|| rate
> parent_rate
)
877 d
= (parent_rate
+ (rate
/ 2)) / rate
;
880 if ((d
== 3) && (c
->dt
[2] != 3))
883 for (i
= 0; i
< 4; i
++)
888 return -EINVAL
; /* oops */
890 spin_lock_irqsave(c
->reglock
, flags
);
891 v
= alchemy_rdsys(c
->reg
);
892 v
&= ~(3 << c
->shift
);
893 v
|= (i
& 3) << c
->shift
;
894 alchemy_wrsys(v
, c
->reg
);
895 spin_unlock_irqrestore(c
->reglock
, flags
);
900 static long alchemy_clk_csrc_detr(struct clk_hw
*hw
, unsigned long rate
,
901 unsigned long *best_parent_rate
,
902 struct clk_hw
**best_parent_clk
)
904 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
905 int scale
= c
->dt
[2] == 3 ? 1 : 2; /* au1300 check */
907 return alchemy_clk_fgcs_detr(hw
, rate
, best_parent_rate
,
908 best_parent_clk
, scale
, 4);
911 static struct clk_ops alchemy_clkops_csrc
= {
912 .recalc_rate
= alchemy_clk_csrc_recalc
,
913 .determine_rate
= alchemy_clk_csrc_detr
,
914 .set_rate
= alchemy_clk_csrc_setr
,
915 .set_parent
= alchemy_clk_csrc_setp
,
916 .get_parent
= alchemy_clk_csrc_getp
,
917 .enable
= alchemy_clk_csrc_en
,
918 .disable
= alchemy_clk_csrc_dis
,
919 .is_enabled
= alchemy_clk_csrc_isen
,
922 static const char * const alchemy_clk_csrc_parents
[] = {
923 /* disabled at index 0 */ ALCHEMY_AUXPLL_CLK
,
924 ALCHEMY_FG0_CLK
, ALCHEMY_FG1_CLK
, ALCHEMY_FG2_CLK
,
925 ALCHEMY_FG3_CLK
, ALCHEMY_FG4_CLK
, ALCHEMY_FG5_CLK
929 static int alchemy_csrc_dt1
[] = { 1, 4, 1, 2 }; /* rest */
930 static int alchemy_csrc_dt2
[] = { 1, 4, 3, 2 }; /* Au1300 */
932 static int __init
alchemy_clk_setup_imux(int ctype
)
934 struct alchemy_fgcs_clk
*a
;
935 const char * const *names
;
936 struct clk_init_data id
;
941 id
.ops
= &alchemy_clkops_csrc
;
942 id
.parent_names
= (const char **)alchemy_clk_csrc_parents
;
944 id
.flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
;
946 dt
= alchemy_csrc_dt1
;
948 case ALCHEMY_CPU_AU1000
:
949 names
= alchemy_au1000_intclknames
;
951 case ALCHEMY_CPU_AU1500
:
952 names
= alchemy_au1500_intclknames
;
954 case ALCHEMY_CPU_AU1100
:
955 names
= alchemy_au1100_intclknames
;
957 case ALCHEMY_CPU_AU1550
:
958 names
= alchemy_au1550_intclknames
;
960 case ALCHEMY_CPU_AU1200
:
961 names
= alchemy_au1200_intclknames
;
963 case ALCHEMY_CPU_AU1300
:
964 dt
= alchemy_csrc_dt2
;
965 names
= alchemy_au1300_intclknames
;
971 a
= kzalloc((sizeof(*a
)) * 6, GFP_KERNEL
);
975 spin_lock_init(&alchemy_clk_csrc_lock
);
978 for (i
= 0; i
< 6; i
++) {
984 a
->reg
= AU1000_SYS_CLKSRC
;
985 a
->reglock
= &alchemy_clk_csrc_lock
;
988 /* default to first parent clock if mux is initially
989 * set to disabled state.
991 v
= alchemy_rdsys(a
->reg
);
992 a
->parent
= ((v
>> a
->shift
) >> 2) & 7;
1000 c
= clk_register(NULL
, &a
->hw
);
1004 clk_register_clkdev(c
, id
.name
, NULL
);
1013 /**********************************************************************/
1022 static int __init
alchemy_clk_init(void)
1024 int ctype
= alchemy_get_cputype(), ret
, i
;
1025 struct clk_aliastable
*t
= alchemy_clk_aliases
;
1028 /* Root of the Alchemy clock tree: external 12MHz crystal osc */
1029 c
= clk_register_fixed_rate(NULL
, ALCHEMY_ROOT_CLK
, NULL
,
1031 ALCHEMY_ROOTCLK_RATE
);
1034 /* CPU core clock */
1035 c
= alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK
, ctype
);
1038 /* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */
1039 i
= (ctype
== ALCHEMY_CPU_AU1300
) ? 84 : 63;
1040 c
= alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK
, ALCHEMY_AUXPLL_CLK
,
1041 i
, AU1000_SYS_AUXPLL
);
1044 if (ctype
== ALCHEMY_CPU_AU1300
) {
1045 c
= alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK
,
1046 ALCHEMY_AUXPLL2_CLK
, i
,
1047 AU1300_SYS_AUXPLL2
);
1051 /* sysbus clock: cpu core clock divided by 2, 3 or 4 */
1052 c
= alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK
);
1055 /* peripheral clock: runs at half rate of sysbus clk */
1056 c
= alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK
);
1059 /* SDR/DDR memory clock */
1060 c
= alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK
, ctype
);
1063 /* L/RCLK: external static bus clock for synchronous mode */
1064 c
= alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK
);
1067 /* Frequency dividers 0-5 */
1068 ret
= alchemy_clk_init_fgens(ctype
);
1074 /* diving muxes for internal sources */
1075 ret
= alchemy_clk_setup_imux(ctype
);
1081 /* set up aliases drivers might look for */
1083 if (t
->cputype
== ctype
)
1084 clk_add_alias(t
->alias
, NULL
, t
->base
, NULL
);
1088 pr_info("Alchemy clocktree installed\n");
1094 postcore_initcall(alchemy_clk_init
);