arch/mips/alchemy/devboards/db1x00/board_setup.c

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *      Alchemy Db1x00 board setup.
   5  *
   6  * Copyright 2000, 2008 MontaVista Software Inc.
   7  * Author: MontaVista Software, Inc. <source@mvista.com>
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  *
  14  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  15  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  16  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  17  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  18  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  20  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  22  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  *  You should have received a copy of the  GNU General Public License along
  26  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  27  *  675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29
  30 #include <linux/gpio.h>
  31 #include <linux/init.h>
  32 #include <linux/interrupt.h>
  33
  34 #include <asm/mach-au1x00/au1000.h>
  35 #include <asm/mach-db1x00/db1x00.h>
  36 #include <asm/mach-db1x00/bcsr.h>
  37
  38 #include <prom.h>
  39
  40 #ifdef CONFIG_MIPS_DB1500
  41 char irq_tab_alchemy[][5] __initdata = {
  42         [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371   */
  43         [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
  44 };
  45 #endif
  46
  47 #ifdef CONFIG_MIPS_BOSPORUS
  48 char irq_tab_alchemy[][5] __initdata = {
  49         [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI  */
  50         [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741   */
  51         [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
  52 };
  53 #endif
  54
  55 #ifdef CONFIG_MIPS_MIRAGE
  56 char irq_tab_alchemy[][5] __initdata = {
  57         [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
  58         [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
  59         [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
  60 };
  61 #endif
  62
  63 #ifdef CONFIG_MIPS_DB1550
  64 char irq_tab_alchemy[][5] __initdata = {
  65         [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
  66         [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
  67         [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
  68 };
  69 #endif
  70
  71 const char *get_system_type(void)
  72 {
  73 #ifdef CONFIG_MIPS_BOSPORUS
  74         return "Alchemy Bosporus Gateway Reference";
  75 #else
  76         return "Alchemy Db1x00";
  77 #endif
  78 }
  79
  80 void board_reset(void)
  81 {
  82         bcsr_write(BCSR_SYSTEM, 0);
  83 }
  84
  85 void __init board_setup(void)
  86 {
  87         unsigned long bcsr1, bcsr2;
  88         u32 pin_func = 0;
  89         char *argptr;
  90
  91         bcsr1 = DB1000_BCSR_PHYS_ADDR;
  92         bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
  93
  94 #ifdef CONFIG_MIPS_DB1000
  95         printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
  96 #endif
  97 #ifdef CONFIG_MIPS_DB1500
  98         printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
  99 #endif
 100 #ifdef CONFIG_MIPS_DB1100
 101         printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
 102 #endif
 103 #ifdef CONFIG_MIPS_BOSPORUS
 104         printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
 105 #endif
 106 #ifdef CONFIG_MIPS_MIRAGE
 107         printk(KERN_INFO "AMD Alchemy Mirage Board\n");
 108 #endif
 109 #ifdef CONFIG_MIPS_DB1550
 110         printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
 111
 112         bcsr1 = DB1550_BCSR_PHYS_ADDR;
 113         bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
 114 #endif
 115
 116         /* initialize board register space */
 117         bcsr_init(bcsr1, bcsr2);
 118
 119         argptr = prom_getcmdline();
 120 #ifdef CONFIG_SERIAL_8250_CONSOLE
 121         argptr = strstr(argptr, "console=");
 122         if (argptr == NULL) {
 123                 argptr = prom_getcmdline();
 124                 strcat(argptr, " console=ttyS0,115200");
 125         }
 126 #endif
 127
 128 #ifdef CONFIG_FB_AU1100
 129         argptr = strstr(argptr, "video=");
 130         if (argptr == NULL) {
 131                 argptr = prom_getcmdline();
 132                 /* default panel */
 133                 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
 134         }
 135 #endif
 136
 137 #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
 138         /* au1000 does not support vra, au1500 and au1100 do */
 139         strcat(argptr, " au1000_audio=vra");
 140         argptr = prom_getcmdline();
 141 #endif
 142
 143         /* Not valid for Au1550 */
 144 #if defined(CONFIG_IRDA) && \
 145    (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
 146         /* Set IRFIRSEL instead of GPIO15 */
 147         pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
 148         au_writel(pin_func, SYS_PINFUNC);
 149         /* Power off until the driver is in use */
 150         bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
 151                                 BCSR_RESETS_IRDA_MODE_OFF);
 152 #endif
 153         bcsr_write(BCSR_PCMCIA, 0);     /* turn off PCMCIA power */
 154
 155         /* Enable GPIO[31:0] inputs */
 156         alchemy_gpio1_input_enable();
 157
 158 #ifdef CONFIG_MIPS_MIRAGE
 159         /* GPIO[20] is output */
 160         alchemy_gpio_direction_output(20, 0);
 161
 162         /* Set GPIO[210:208] instead of SSI_0 */
 163         pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
 164
 165         /* Set GPIO[215:211] for LEDs */
 166         pin_func |= 5 << 2;
 167
 168         /* Set GPIO[214:213] for more LEDs */
 169         pin_func |= 5 << 12;
 170
 171         /* Set GPIO[207:200] instead of PCMCIA/LCD */
 172         pin_func |= SYS_PF_LCD | SYS_PF_PC;
 173         au_writel(pin_func, SYS_PINFUNC);
 174
 175         /*
 176          * Enable speaker amplifier.  This should
 177          * be part of the audio driver.
 178          */
 179         alchemy_gpio_direction_output(209, 1);
 180 #endif
 181
 182         au_sync();
 183 }
 184
 185 static int __init db1x00_init_irq(void)
 186 {
 187 #if defined(CONFIG_MIPS_MIRAGE)
 188         set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
 189 #elif defined(CONFIG_MIPS_DB1550)
 190         set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);  /* CD0# */
 191         set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);  /* CD1# */
 192         set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW);  /* CARD0# */
 193         set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW);  /* CARD1# */
 194         set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
 195         set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
 196 #elif defined(CONFIG_MIPS_DB1500)
 197         set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
 198         set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
 199         set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
 200         set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
 201         set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
 202         set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
 203 #elif defined(CONFIG_MIPS_DB1100)
 204         set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
 205         set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
 206         set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
 207         set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
 208         set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
 209         set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
 210 #elif defined(CONFIG_MIPS_DB1000)
 211         set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
 212         set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
 213         set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
 214         set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
 215         set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
 216         set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
 217 #endif
 218         return 0;
 219 }
 220 arch_initcall(db1x00_init_irq);