arch/mips/alchemy/devboards/db1x00/platform.c

   1 /*
   2  * DBAu1xxx board platform device registration
   3  *
   4  * Copyright (C) 2009 Manuel Lauss
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23
  24 #include <asm/mach-au1x00/au1xxx.h>
  25 #include <asm/mach-db1x00/bcsr.h>
  26 #include "../platform.h"
  27
  28 struct pci_dev;
  29
  30 /* DB1xxx PCMCIA interrupt sources:
  31  * CD0/1        GPIO0/3
  32  * STSCHG0/1    GPIO1/4
  33  * CARD0/1      GPIO2/5
  34  * Db1550:      0/1, 21/22, 3/5
  35  */
  36
  37 #define DB1XXX_HAS_PCMCIA
  38 #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
  39
  40 #if defined(CONFIG_MIPS_DB1000)
  41 #define DB1XXX_PCMCIA_CD0       AU1000_GPIO0_INT
  42 #define DB1XXX_PCMCIA_STSCHG0   AU1000_GPIO1_INT
  43 #define DB1XXX_PCMCIA_CARD0     AU1000_GPIO2_INT
  44 #define DB1XXX_PCMCIA_CD1       AU1000_GPIO3_INT
  45 #define DB1XXX_PCMCIA_STSCHG1   AU1000_GPIO4_INT
  46 #define DB1XXX_PCMCIA_CARD1     AU1000_GPIO5_INT
  47 #define BOARD_FLASH_SIZE        0x02000000 /* 32MB */
  48 #define BOARD_FLASH_WIDTH       4 /* 32-bits */
  49 #elif defined(CONFIG_MIPS_DB1100)
  50 #define DB1XXX_PCMCIA_CD0       AU1100_GPIO0_INT
  51 #define DB1XXX_PCMCIA_STSCHG0   AU1100_GPIO1_INT
  52 #define DB1XXX_PCMCIA_CARD0     AU1100_GPIO2_INT
  53 #define DB1XXX_PCMCIA_CD1       AU1100_GPIO3_INT
  54 #define DB1XXX_PCMCIA_STSCHG1   AU1100_GPIO4_INT
  55 #define DB1XXX_PCMCIA_CARD1     AU1100_GPIO5_INT
  56 #define BOARD_FLASH_SIZE        0x02000000 /* 32MB */
  57 #define BOARD_FLASH_WIDTH       4 /* 32-bits */
  58 #elif defined(CONFIG_MIPS_DB1500)
  59 #define DB1XXX_PCMCIA_CD0       AU1500_GPIO0_INT
  60 #define DB1XXX_PCMCIA_STSCHG0   AU1500_GPIO1_INT
  61 #define DB1XXX_PCMCIA_CARD0     AU1500_GPIO2_INT
  62 #define DB1XXX_PCMCIA_CD1       AU1500_GPIO3_INT
  63 #define DB1XXX_PCMCIA_STSCHG1   AU1500_GPIO4_INT
  64 #define DB1XXX_PCMCIA_CARD1     AU1500_GPIO5_INT
  65 #define BOARD_FLASH_SIZE        0x02000000 /* 32MB */
  66 #define BOARD_FLASH_WIDTH       4 /* 32-bits */
  67 #elif defined(CONFIG_MIPS_DB1550)
  68 #define DB1XXX_PCMCIA_CD0       AU1550_GPIO0_INT
  69 #define DB1XXX_PCMCIA_STSCHG0   AU1550_GPIO21_INT
  70 #define DB1XXX_PCMCIA_CARD0     AU1550_GPIO3_INT
  71 #define DB1XXX_PCMCIA_CD1       AU1550_GPIO1_INT
  72 #define DB1XXX_PCMCIA_STSCHG1   AU1550_GPIO22_INT
  73 #define DB1XXX_PCMCIA_CARD1     AU1550_GPIO5_INT
  74 #define BOARD_FLASH_SIZE        0x08000000 /* 128MB */
  75 #define BOARD_FLASH_WIDTH       4 /* 32-bits */
  76 #else
  77 /* other board: no PCMCIA */
  78 #undef DB1XXX_HAS_PCMCIA
  79 #undef F_SWAPPED
  80 #define F_SWAPPED 0
  81 #if defined(CONFIG_MIPS_BOSPORUS)
  82 #define BOARD_FLASH_SIZE        0x01000000 /* 16MB */
  83 #define BOARD_FLASH_WIDTH       2 /* 16-bits */
  84 #elif defined(CONFIG_MIPS_MIRAGE)
  85 #define BOARD_FLASH_SIZE        0x04000000 /* 64MB */
  86 #define BOARD_FLASH_WIDTH       4 /* 32-bits */
  87 #endif
  88 #endif
  89
  90 #ifdef CONFIG_PCI
  91 #ifdef CONFIG_MIPS_DB1500
  92 static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
  93 {
  94         if ((slot < 12) || (slot > 13) || pin == 0)
  95                 return -1;
  96         if (slot == 12)
  97                 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
  98         if (slot == 13) {
  99                 switch (pin) {
 100                 case 1: return AU1500_PCI_INTA;
 101                 case 2: return AU1500_PCI_INTB;
 102                 case 3: return AU1500_PCI_INTC;
 103                 case 4: return AU1500_PCI_INTD;
 104                 }
 105         }
 106         return -1;
 107 }
 108 #endif
 109
 110 #ifdef CONFIG_MIPS_DB1550
 111 static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 112 {
 113         if ((slot < 11) || (slot > 13) || pin == 0)
 114                 return -1;
 115         if (slot == 11)
 116                 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
 117         if (slot == 12) {
 118                 switch (pin) {
 119                 case 1: return AU1550_PCI_INTB;
 120                 case 2: return AU1550_PCI_INTC;
 121                 case 3: return AU1550_PCI_INTD;
 122                 case 4: return AU1550_PCI_INTA;
 123                 }
 124         }
 125         if (slot == 13) {
 126                 switch (pin) {
 127                 case 1: return AU1550_PCI_INTA;
 128                 case 2: return AU1550_PCI_INTB;
 129                 case 3: return AU1550_PCI_INTC;
 130                 case 4: return AU1550_PCI_INTD;
 131                 }
 132         }
 133         return -1;
 134 }
 135 #endif
 136
 137 #ifdef CONFIG_MIPS_BOSPORUS
 138 static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 139 {
 140         if ((slot < 11) || (slot > 13) || pin == 0)
 141                 return -1;
 142         if (slot == 12)
 143                 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
 144         if (slot == 11) {
 145                 switch (pin) {
 146                 case 1: return AU1500_PCI_INTA;
 147                 case 2: return AU1500_PCI_INTB;
 148                 default: return 0xff;
 149                 }
 150         }
 151         if (slot == 13) {
 152                 switch (pin) {
 153                 case 1: return AU1500_PCI_INTA;
 154                 case 2: return AU1500_PCI_INTB;
 155                 case 3: return AU1500_PCI_INTC;
 156                 case 4: return AU1500_PCI_INTD;
 157                 }
 158         }
 159         return -1;
 160 }
 161 #endif
 162
 163 #ifdef CONFIG_MIPS_MIRAGE
 164 static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 165 {
 166         if ((slot < 11) || (slot > 13) || pin == 0)
 167                 return -1;
 168         if (slot == 11)
 169                 return (pin == 1) ? AU1500_PCI_INTD : 0xff;
 170         if (slot == 12)
 171                 return (pin == 3) ? AU1500_PCI_INTC : 0xff;
 172         if (slot == 13) {
 173                 switch (pin) {
 174                 case 1: return AU1500_PCI_INTA;
 175                 case 2: return AU1500_PCI_INTB;
 176                 default: return 0xff;
 177                 }
 178         }
 179         return -1;
 180 }
 181 #endif
 182
 183 static struct resource alchemy_pci_host_res[] = {
 184         [0] = {
 185                 .start  = AU1500_PCI_PHYS_ADDR,
 186                 .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
 187                 .flags  = IORESOURCE_MEM,
 188         },
 189 };
 190
 191 static struct alchemy_pci_platdata db1xxx_pci_pd = {
 192         .board_map_irq  = db1xxx_map_pci_irq,
 193 };
 194
 195 static struct platform_device db1xxx_pci_host_dev = {
 196         .dev.platform_data = &db1xxx_pci_pd,
 197         .name           = "alchemy-pci",
 198         .id             = 0,
 199         .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
 200         .resource       = alchemy_pci_host_res,
 201 };
 202
 203 static int __init db15x0_pci_init(void)
 204 {
 205         return platform_device_register(&db1xxx_pci_host_dev);
 206 }
 207 /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
 208 arch_initcall(db15x0_pci_init);
 209 #endif
 210
 211 static int __init db1xxx_dev_init(void)
 212 {
 213 #ifdef DB1XXX_HAS_PCMCIA
 214         db1x_register_pcmcia_socket(
 215                 AU1000_PCMCIA_ATTR_PHYS_ADDR,
 216                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
 217                 AU1000_PCMCIA_MEM_PHYS_ADDR,
 218                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
 219                 AU1000_PCMCIA_IO_PHYS_ADDR,
 220                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
 221                 DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0,
 222                 /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0);
 223
 224         db1x_register_pcmcia_socket(
 225                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
 226                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
 227                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
 228                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
 229                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
 230                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
 231                 DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
 232                 /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
 233 #endif
 234         db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
 235         return 0;
 236 }
 237 device_initcall(db1xxx_dev_init);