arch/mips/alchemy/devboards/pb1000/board_setup.c

   1 /*
   2  * Copyright 2000, 2008 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  11  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  13  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  14  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  15  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  16  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  17  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  18  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  19  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  20  *
  21  *  You should have received a copy of the  GNU General Public License along
  22  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  23  *  675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/delay.h>
  27 #include <linux/gpio.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/pm.h>
  31 #include <asm/mach-au1x00/au1000.h>
  32 #include <asm/mach-pb1x00/pb1000.h>
  33 #include <asm/reboot.h>
  34 #include <prom.h>
  35
  36 #include "../platform.h"
  37
  38 const char *get_system_type(void)
  39 {
  40         return "Alchemy Pb1000";
  41 }
  42
  43 static void board_reset(char *c)
  44 {
  45         asm volatile ("jr %0" : : "r" (0xbfc00000));
  46 }
  47
  48 static void board_power_off(void)
  49 {
  50         printk(KERN_ALERT "It's now safe to remove power\n");
  51         while (1)
  52                 asm volatile (".set mips3 ; wait ; .set mips1");
  53 }
  54
  55 void __init board_setup(void)
  56 {
  57         u32 pin_func, static_cfg0;
  58         u32 sys_freqctrl, sys_clksrc;
  59         u32 prid = read_c0_prid();
  60
  61         sys_freqctrl = 0;
  62         sys_clksrc = 0;
  63
  64         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
  65         au_writel(8, SYS_AUXPLL);
  66         au_writel(0, SYS_PINSTATERD);
  67         udelay(100);
  68
  69 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  70         /* Zero and disable FREQ2 */
  71         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  72         sys_freqctrl &= ~0xFFF00000;
  73         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  74
  75         /* Zero and disable USBH/USBD clocks */
  76         sys_clksrc = au_readl(SYS_CLKSRC);
  77         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  78                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  79         au_writel(sys_clksrc, SYS_CLKSRC);
  80
  81         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  82         sys_freqctrl &= ~0xFFF00000;
  83
  84         sys_clksrc = au_readl(SYS_CLKSRC);
  85         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  86                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  87
  88         switch (prid & 0x000000FF) {
  89         case 0x00: /* DA */
  90         case 0x01: /* HA */
  91         case 0x02: /* HB */
  92                 /* CPU core freq to 48 MHz to slow it way down... */
  93                 au_writel(4, SYS_CPUPLL);
  94
  95                 /*
  96                  * Setup 48 MHz FREQ2 from CPUPLL for USB Host
  97                  * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
  98                  */
  99                 sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
 100                 au_writel(sys_freqctrl, SYS_FREQCTRL0);
 101
 102                 /* CPU core freq to 384 MHz */
 103                 au_writel(0x20, SYS_CPUPLL);
 104
 105                 printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
 106                 break;
 107
 108         default: /* HC and newer */
 109                 /* FREQ2 = aux / 2 = 48 MHz */
 110                 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
 111                                  SYS_FC_FE2 | SYS_FC_FS2;
 112                 au_writel(sys_freqctrl, SYS_FREQCTRL0);
 113                 break;
 114         }
 115
 116         /*
 117          * Route 48 MHz FREQ2 into USB Host and/or Device
 118          */
 119         sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
 120         au_writel(sys_clksrc, SYS_CLKSRC);
 121
 122         /* Configure pins GPIO[14:9] as GPIO */
 123         pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
 124
 125         /* 2nd USB port is USB host */
 126         pin_func |= SYS_PF_USB;
 127
 128         au_writel(pin_func, SYS_PINFUNC);
 129
 130         alchemy_gpio_direction_input(11);
 131         alchemy_gpio_direction_input(13);
 132         alchemy_gpio_direction_output(4, 0);
 133         alchemy_gpio_direction_output(5, 0);
 134 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
 135
 136         /* Make GPIO 15 an input (for interrupt line) */
 137         pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
 138         /* We don't need I2S, so make it available for GPIO[31:29] */
 139         pin_func |= SYS_PF_I2S;
 140         au_writel(pin_func, SYS_PINFUNC);
 141
 142         alchemy_gpio_direction_input(15);
 143
 144         static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
 145         au_writel(static_cfg0, MEM_STCFG0);
 146
 147         /* configure RCE2* for LCD */
 148         au_writel(0x00000004, MEM_STCFG2);
 149
 150         /* MEM_STTIME2 */
 151         au_writel(0x09000000, MEM_STTIME2);
 152
 153         /* Set 32-bit base address decoding for RCE2* */
 154         au_writel(0x10003ff0, MEM_STADDR2);
 155
 156         /*
 157          * PCI CPLD setup
 158          * Expand CE0 to cover PCI
 159          */
 160         au_writel(0x11803e40, MEM_STADDR1);
 161
 162         /* Burst visibility on */
 163         au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
 164
 165         au_writel(0x83, MEM_STCFG1);         /* ewait enabled, flash timing */
 166         au_writel(0x33030a10, MEM_STTIME1);  /* slower timing for FPGA */
 167
 168         /* Setup the static bus controller */
 169         au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
 170         au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
 171         au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
 172
 173         /*
 174          * Enable Au1000 BCLK switching - note: sed1356 must not use
 175          * its BCLK (Au1000 LCLK) for any timings
 176          */
 177         switch (prid & 0x000000FF) {
 178         case 0x00: /* DA */
 179         case 0x01: /* HA */
 180         case 0x02: /* HB */
 181                 break;
 182         default:  /* HC and newer */
 183                 /*
 184                  * Enable sys bus clock divider when IDLE state or no bus
 185                  * activity.
 186                  */
 187                 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
 188                 break;
 189         }
 190
 191         pm_power_off = board_power_off;
 192         _machine_halt = board_power_off;
 193         _machine_restart = board_reset;
 194 }
 195
 196 static int __init pb1000_init_irq(void)
 197 {
 198         set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
 199         return 0;
 200 }
 201 arch_initcall(pb1000_init_irq);
 202
 203 static int __init pb1000_device_init(void)
 204 {
 205         return db1x_register_norflash(8 * 1024 * 1024, 4, 0);
 206 }
 207 device_initcall(pb1000_device_init);