arch/mips/alchemy/devboards/pb1000/board_setup.c

   1 /*
   2  * Copyright 2000, 2008 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  11  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  13  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  14  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  15  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  16  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  17  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  18  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  19  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  20  *
  21  *  You should have received a copy of the  GNU General Public License along
  22  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  23  *  675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/delay.h>
  27 #include <linux/gpio.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <asm/mach-au1x00/au1000.h>
  31 #include <asm/mach-pb1x00/pb1000.h>
  32 #include <prom.h>
  33
  34
  35 const char *get_system_type(void)
  36 {
  37         return "Alchemy Pb1000";
  38 }
  39
  40 void board_reset(void)
  41 {
  42 }
  43
  44 void __init board_setup(void)
  45 {
  46         u32 pin_func, static_cfg0;
  47         u32 sys_freqctrl, sys_clksrc;
  48         u32 prid = read_c0_prid();
  49
  50 #ifdef CONFIG_SERIAL_8250_CONSOLE
  51         char *argptr = prom_getcmdline();
  52         argptr = strstr(argptr, "console=");
  53         if (argptr == NULL) {
  54                 argptr = prom_getcmdline();
  55                 strcat(argptr, " console=ttyS0,115200");
  56         }
  57 #endif
  58
  59         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
  60         au_writel(8, SYS_AUXPLL);
  61         au_writel(0, SYS_PINSTATERD);
  62         udelay(100);
  63
  64 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  65         /* Zero and disable FREQ2 */
  66         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  67         sys_freqctrl &= ~0xFFF00000;
  68         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  69
  70         /* Zero and disable USBH/USBD clocks */
  71         sys_clksrc = au_readl(SYS_CLKSRC);
  72         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  73                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  74         au_writel(sys_clksrc, SYS_CLKSRC);
  75
  76         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  77         sys_freqctrl &= ~0xFFF00000;
  78
  79         sys_clksrc = au_readl(SYS_CLKSRC);
  80         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  81                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  82
  83         switch (prid & 0x000000FF) {
  84         case 0x00: /* DA */
  85         case 0x01: /* HA */
  86         case 0x02: /* HB */
  87                 /* CPU core freq to 48 MHz to slow it way down... */
  88                 au_writel(4, SYS_CPUPLL);
  89
  90                 /*
  91                  * Setup 48 MHz FREQ2 from CPUPLL for USB Host
  92                  * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
  93                  */
  94                 sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
  95                 au_writel(sys_freqctrl, SYS_FREQCTRL0);
  96
  97                 /* CPU core freq to 384 MHz */
  98                 au_writel(0x20, SYS_CPUPLL);
  99
 100                 printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
 101                 break;
 102
 103         default: /* HC and newer */
 104                 /* FREQ2 = aux / 2 = 48 MHz */
 105                 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
 106                                  SYS_FC_FE2 | SYS_FC_FS2;
 107                 au_writel(sys_freqctrl, SYS_FREQCTRL0);
 108                 break;
 109         }
 110
 111         /*
 112          * Route 48 MHz FREQ2 into USB Host and/or Device
 113          */
 114         sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
 115         au_writel(sys_clksrc, SYS_CLKSRC);
 116
 117         /* Configure pins GPIO[14:9] as GPIO */
 118         pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
 119
 120         /* 2nd USB port is USB host */
 121         pin_func |= SYS_PF_USB;
 122
 123         au_writel(pin_func, SYS_PINFUNC);
 124
 125         alchemy_gpio_direction_input(11);
 126         alchemy_gpio_direction_input(13);
 127         alchemy_gpio_direction_output(4, 0);
 128         alchemy_gpio_direction_output(5, 0);
 129 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
 130
 131         /* Make GPIO 15 an input (for interrupt line) */
 132         pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
 133         /* We don't need I2S, so make it available for GPIO[31:29] */
 134         pin_func |= SYS_PF_I2S;
 135         au_writel(pin_func, SYS_PINFUNC);
 136
 137         alchemy_gpio_direction_input(15);
 138
 139         static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
 140         au_writel(static_cfg0, MEM_STCFG0);
 141
 142         /* configure RCE2* for LCD */
 143         au_writel(0x00000004, MEM_STCFG2);
 144
 145         /* MEM_STTIME2 */
 146         au_writel(0x09000000, MEM_STTIME2);
 147
 148         /* Set 32-bit base address decoding for RCE2* */
 149         au_writel(0x10003ff0, MEM_STADDR2);
 150
 151         /*
 152          * PCI CPLD setup
 153          * Expand CE0 to cover PCI
 154          */
 155         au_writel(0x11803e40, MEM_STADDR1);
 156
 157         /* Burst visibility on */
 158         au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
 159
 160         au_writel(0x83, MEM_STCFG1);         /* ewait enabled, flash timing */
 161         au_writel(0x33030a10, MEM_STTIME1);  /* slower timing for FPGA */
 162
 163         /* Setup the static bus controller */
 164         au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
 165         au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
 166         au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
 167
 168         /*
 169          * Enable Au1000 BCLK switching - note: sed1356 must not use
 170          * its BCLK (Au1000 LCLK) for any timings
 171          */
 172         switch (prid & 0x000000FF) {
 173         case 0x00: /* DA */
 174         case 0x01: /* HA */
 175         case 0x02: /* HB */
 176                 break;
 177         default:  /* HC and newer */
 178                 /*
 179                  * Enable sys bus clock divider when IDLE state or no bus
 180                  * activity.
 181                  */
 182                 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
 183                 break;
 184         }
 185 }
 186
 187 static int __init pb1000_init_irq(void)
 188 {
 189         set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
 190         return 0;
 191 }
 192 arch_initcall(pb1000_init_irq);