arch/mips/alchemy/pb1500/board_setup.c

   1 /*
   2  * Copyright 2000, 2008 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  11  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  13  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  14  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  15  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  16  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  17  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  18  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  19  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  20  *
  21  *  You should have received a copy of the  GNU General Public License along
  22  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  23  *  675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28
  29 #include <asm/mach-au1x00/au1000.h>
  30 #include <asm/mach-pb1x00/pb1500.h>
  31
  32 void board_reset(void)
  33 {
  34         /* Hit BCSR.RST_VDDI[SOFT_RESET] */
  35         au_writel(0x00000000, PB1500_RST_VDDI);
  36 }
  37
  38 void __init board_setup(void)
  39 {
  40         u32 pin_func;
  41         u32 sys_freqctrl, sys_clksrc;
  42
  43         sys_clksrc = sys_freqctrl = pin_func = 0;
  44         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
  45         au_writel(8, SYS_AUXPLL);
  46         au_writel(0, SYS_PINSTATERD);
  47         udelay(100);
  48
  49 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  50
  51         /* GPIO201 is input for PCMCIA card detect */
  52         /* GPIO203 is input for PCMCIA interrupt request */
  53         au_writel(au_readl(GPIO2_DIR) & ~((1 << 1) | (1 << 3)), GPIO2_DIR);
  54
  55         /* Zero and disable FREQ2 */
  56         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  57         sys_freqctrl &= ~0xFFF00000;
  58         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  59
  60         /* zero and disable USBH/USBD clocks */
  61         sys_clksrc = au_readl(SYS_CLKSRC);
  62         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  63                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  64         au_writel(sys_clksrc, SYS_CLKSRC);
  65
  66         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  67         sys_freqctrl &= ~0xFFF00000;
  68
  69         sys_clksrc = au_readl(SYS_CLKSRC);
  70         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  71                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  72
  73         /* FREQ2 = aux/2 = 48 MHz */
  74         sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
  75         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  76
  77         /*
  78          * Route 48MHz FREQ2 into USB Host and/or Device
  79          */
  80         sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
  81         au_writel(sys_clksrc, SYS_CLKSRC);
  82
  83         pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
  84         /* 2nd USB port is USB host */
  85         pin_func |= SYS_PF_USB;
  86         au_writel(pin_func, SYS_PINFUNC);
  87 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
  88
  89 #ifdef CONFIG_PCI
  90         /* Setup PCI bus controller */
  91         au_writel(0, Au1500_PCI_CMEM);
  92         au_writel(0x00003fff, Au1500_CFG_BASE);
  93 #if defined(__MIPSEB__)
  94         au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
  95 #else
  96         au_writel(0xf, Au1500_PCI_CFG);
  97 #endif
  98         au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
  99         au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
 100         au_writel(0x02a00356, Au1500_PCI_STATCMD);
 101         au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
 102         au_writel(0x00000008, Au1500_PCI_MBAR);
 103         au_sync();
 104 #endif
 105
 106         /* Enable sys bus clock divider when IDLE state or no bus activity. */
 107         au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
 108
 109         /* Enable the RTC if not already enabled */
 110         if (!(au_readl(0xac000028) & 0x20)) {
 111                 printk(KERN_INFO "enabling clock ...\n");
 112                 au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
 113         }
 114         /* Put the clock in BCD mode */
 115         if (au_readl(0xac00002c) & 0x4) { /* reg B */
 116                 au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
 117                 au_sync();
 118         }
 119 }