arch/mips/alchemy/xxs1500/board_setup.c

   1 /*
   2  * Copyright 2000-2003, 2008 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  11  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  13  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  14  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  15  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  16  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  17  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  18  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  19  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  20  *
  21  *  You should have received a copy of the  GNU General Public License along
  22  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  23  *  675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/gpio.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/delay.h>
  30 #include <linux/pm.h>
  31
  32 #include <asm/reboot.h>
  33 #include <asm/mach-au1x00/au1000.h>
  34
  35 #include <prom.h>
  36
  37 static void xxs1500_reset(char *c)
  38 {
  39         /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
  40         au_writel(0x00000000, 0xAE00001C);
  41 }
  42
  43 static void xxs1500_power_off(void)
  44 {
  45         while (1)
  46                 asm volatile (
  47                 "       .set    mips32                                  \n"
  48                 "       wait                                            \n"
  49                 "       .set    mips0                                   \n");
  50 }
  51
  52 void __init board_setup(void)
  53 {
  54         u32 pin_func;
  55
  56         pm_power_off = xxs1500_power_off;
  57         _machine_halt = xxs1500_power_off;
  58         _machine_restart = xxs1500_reset;
  59
  60         alchemy_gpio1_input_enable();
  61         alchemy_gpio2_enable();
  62
  63         /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
  64         pin_func  = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
  65         pin_func |= SYS_PF_UR3;
  66         au_writel(pin_func, SYS_PINFUNC);
  67
  68         /* Enable UART */
  69         au_writel(0x01, UART3_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
  70         mdelay(10);
  71         au_writel(0x03, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
  72         mdelay(10);
  73
  74         /* Enable DTR = USB power up */
  75         au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */
  76
  77 #ifdef CONFIG_PCI
  78 #if defined(__MIPSEB__)
  79         au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
  80 #else
  81         au_writel(0xf, Au1500_PCI_CFG);
  82 #endif
  83 #endif
  84 }
  85
  86 static int __init xxs1500_init_irq(void)
  87 {
  88         set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
  89         set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
  90         set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
  91         set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
  92         set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
  93         set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
  94
  95         set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
  96         set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
  97         set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
  98         set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
  99         set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
 100         set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
 101
 102         return 0;
 103 }
 104 arch_initcall(xxs1500_init_irq);