2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
10 * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
14 * Platform devices for Atheros AR5312 SoCs
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/reboot.h>
20 #include <asm/bootinfo.h>
21 #include <asm/reboot.h>
26 #include "ar5312_regs.h"
28 static void __iomem
*ar5312_rst_base
;
30 static inline u32
ar5312_rst_reg_read(u32 reg
)
32 return __raw_readl(ar5312_rst_base
+ reg
);
35 static inline void ar5312_rst_reg_write(u32 reg
, u32 val
)
37 __raw_writel(val
, ar5312_rst_base
+ reg
);
40 static inline void ar5312_rst_reg_mask(u32 reg
, u32 mask
, u32 val
)
42 u32 ret
= ar5312_rst_reg_read(reg
);
46 ar5312_rst_reg_write(reg
, ret
);
49 static void ar5312_restart(char *command
)
51 /* reset the system */
54 ar5312_rst_reg_write(AR5312_RESET
, AR5312_RESET_SYSTEM
);
58 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
59 * to determine the predevisor value.
61 static unsigned clockctl1_predivide_table
[4] __initdata
= { 1, 2, 4, 5 };
63 static unsigned __init
ar5312_cpu_frequency(void)
65 u32 scratch
, devid
, clock_ctl1
;
66 u32 predivide_mask
, multiplier_mask
, doubler_mask
;
67 unsigned predivide_shift
, multiplier_shift
;
68 unsigned predivide_select
, predivisor
, multiplier
;
70 /* Trust the bootrom's idea of cpu frequency. */
71 scratch
= ar5312_rst_reg_read(AR5312_SCRATCH
);
75 devid
= ar5312_rst_reg_read(AR5312_REV
);
76 devid
= (devid
& AR5312_REV_MAJ
) >> AR5312_REV_MAJ_S
;
77 if (devid
== AR5312_REV_MAJ_AR2313
) {
78 predivide_mask
= AR2313_CLOCKCTL1_PREDIVIDE_MASK
;
79 predivide_shift
= AR2313_CLOCKCTL1_PREDIVIDE_SHIFT
;
80 multiplier_mask
= AR2313_CLOCKCTL1_MULTIPLIER_MASK
;
81 multiplier_shift
= AR2313_CLOCKCTL1_MULTIPLIER_SHIFT
;
82 doubler_mask
= AR2313_CLOCKCTL1_DOUBLER_MASK
;
83 } else { /* AR5312 and AR2312 */
84 predivide_mask
= AR5312_CLOCKCTL1_PREDIVIDE_MASK
;
85 predivide_shift
= AR5312_CLOCKCTL1_PREDIVIDE_SHIFT
;
86 multiplier_mask
= AR5312_CLOCKCTL1_MULTIPLIER_MASK
;
87 multiplier_shift
= AR5312_CLOCKCTL1_MULTIPLIER_SHIFT
;
88 doubler_mask
= AR5312_CLOCKCTL1_DOUBLER_MASK
;
92 * Clocking is derived from a fixed 40MHz input clock.
94 * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
95 * sys_freq = cpu_freq / 4 (used for APB clock, serial,
96 * flash, Timer, Watchdog Timer)
98 * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
100 * So, for example, with a PLL multiplier of 5, we have
106 * We compute the CPU frequency, based on PLL settings.
109 clock_ctl1
= ar5312_rst_reg_read(AR5312_CLOCKCTL1
);
110 predivide_select
= (clock_ctl1
& predivide_mask
) >> predivide_shift
;
111 predivisor
= clockctl1_predivide_table
[predivide_select
];
112 multiplier
= (clock_ctl1
& multiplier_mask
) >> multiplier_shift
;
114 if (clock_ctl1
& doubler_mask
)
117 return (40000000 / predivisor
) * multiplier
;
120 static inline unsigned ar5312_sys_frequency(void)
122 return ar5312_cpu_frequency() / 4;
125 void __init
ar5312_plat_time_init(void)
127 mips_hpt_frequency
= ar5312_cpu_frequency() / 2;
130 void __init
ar5312_plat_mem_setup(void)
132 void __iomem
*sdram_base
;
133 u32 memsize
, memcfg
, bank0_ac
, bank1_ac
;
135 /* Detect memory size */
136 sdram_base
= ioremap_nocache(AR5312_SDRAMCTL_BASE
,
137 AR5312_SDRAMCTL_SIZE
);
138 memcfg
= __raw_readl(sdram_base
+ AR5312_MEM_CFG1
);
139 bank0_ac
= ATH25_REG_MS(memcfg
, AR5312_MEM_CFG1_AC0
);
140 bank1_ac
= ATH25_REG_MS(memcfg
, AR5312_MEM_CFG1_AC1
);
141 memsize
= (bank0_ac
? (1 << (bank0_ac
+ 1)) : 0) +
142 (bank1_ac
? (1 << (bank1_ac
+ 1)) : 0);
144 add_memory_region(0, memsize
, BOOT_MEM_RAM
);
147 ar5312_rst_base
= ioremap_nocache(AR5312_RST_BASE
, AR5312_RST_SIZE
);
149 /* Clear any lingering AHB errors */
150 ar5312_rst_reg_read(AR5312_PROCADDR
);
151 ar5312_rst_reg_read(AR5312_DMAADDR
);
152 ar5312_rst_reg_write(AR5312_WDT_CTRL
, AR5312_WDT_CTRL_IGNORE
);
154 _machine_restart
= ar5312_restart
;