arch/mips/bcm63xx/irq.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/module.h>
  14 #include <linux/irq.h>
  15 #include <asm/irq_cpu.h>
  16 #include <asm/mipsregs.h>
  17 #include <bcm63xx_cpu.h>
  18 #include <bcm63xx_regs.h>
  19 #include <bcm63xx_io.h>
  20 #include <bcm63xx_irq.h>
  21
  22 static u32 irq_stat_addr[2];
  23 static u32 irq_mask_addr[2];
  24 static void (*dispatch_internal)(void);
  25 static int is_ext_irq_cascaded;
  26 static unsigned int ext_irq_count;
  27 static unsigned int ext_irq_start, ext_irq_end;
  28 static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
  29 static void (*internal_irq_mask)(unsigned int irq);
  30 static void (*internal_irq_unmask)(unsigned int irq);
  31
  32
  33 static inline u32 get_ext_irq_perf_reg(int irq)
  34 {
  35         if (irq < 4)
  36                 return ext_irq_cfg_reg1;
  37         return ext_irq_cfg_reg2;
  38 }
  39
  40 static inline void handle_internal(int intbit)
  41 {
  42         if (is_ext_irq_cascaded &&
  43             intbit >= ext_irq_start && intbit <= ext_irq_end)
  44                 do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
  45         else
  46                 do_IRQ(intbit + IRQ_INTERNAL_BASE);
  47 }
  48
  49 /*
  50  * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
  51  * prioritize any interrupt relatively to another. the static counter
  52  * will resume the loop where it ended the last time we left this
  53  * function.
  54  */
  55
  56 #define BUILD_IPIC_INTERNAL(width)                                      \
  57 void __dispatch_internal_##width(void)                                  \
  58 {                                                                       \
  59         u32 pending[width / 32];                                        \
  60         unsigned int src, tgt;                                          \
  61         bool irqs_pending = false;                                      \
  62         static unsigned int i;                                          \
  63                                                                         \
  64         /* read registers in reverse order */                           \
  65         for (src = 0, tgt = (width / 32); src < (width / 32); src++) {  \
  66                 u32 val;                                                \
  67                                                                         \
  68                 val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32));  \
  69                 val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \
  70                 pending[--tgt] = val;                                   \
  71                                                                         \
  72                 if (val)                                                \
  73                         irqs_pending = true;                            \
  74         }                                                               \
  75                                                                         \
  76         if (!irqs_pending)                                              \
  77                 return;                                                 \
  78                                                                         \
  79         while (1) {                                                     \
  80                 unsigned int to_call = i;                               \
  81                                                                         \
  82                 i = (i + 1) & (width - 1);                              \
  83                 if (pending[to_call / 32] & (1 << (to_call & 0x1f))) {  \
  84                         handle_internal(to_call);                       \
  85                         break;                                          \
  86                 }                                                       \
  87         }                                                               \
  88 }                                                                       \
  89                                                                         \
  90 static void __internal_irq_mask_##width(unsigned int irq)               \
  91 {                                                                       \
  92         u32 val;                                                        \
  93         unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
  94         unsigned bit = irq & 0x1f;                                      \
  95                                                                         \
  96         val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32));          \
  97         val &= ~(1 << bit);                                             \
  98         bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32));          \
  99 }                                                                       \
 100                                                                         \
 101 static void __internal_irq_unmask_##width(unsigned int irq)             \
 102 {                                                                       \
 103         u32 val;                                                        \
 104         unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
 105         unsigned bit = irq & 0x1f;                                      \
 106                                                                         \
 107         val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32));          \
 108         val |= (1 << bit);                                              \
 109         bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32));          \
 110 }
 111
 112 BUILD_IPIC_INTERNAL(32);
 113 BUILD_IPIC_INTERNAL(64);
 114
 115 asmlinkage void plat_irq_dispatch(void)
 116 {
 117         u32 cause;
 118
 119         do {
 120                 cause = read_c0_cause() & read_c0_status() & ST0_IM;
 121
 122                 if (!cause)
 123                         break;
 124
 125                 if (cause & CAUSEF_IP7)
 126                         do_IRQ(7);
 127                 if (cause & CAUSEF_IP0)
 128                         do_IRQ(0);
 129                 if (cause & CAUSEF_IP1)
 130                         do_IRQ(1);
 131                 if (cause & CAUSEF_IP2)
 132                         dispatch_internal();
 133                 if (!is_ext_irq_cascaded) {
 134                         if (cause & CAUSEF_IP3)
 135                                 do_IRQ(IRQ_EXT_0);
 136                         if (cause & CAUSEF_IP4)
 137                                 do_IRQ(IRQ_EXT_1);
 138                         if (cause & CAUSEF_IP5)
 139                                 do_IRQ(IRQ_EXT_2);
 140                         if (cause & CAUSEF_IP6)
 141                                 do_IRQ(IRQ_EXT_3);
 142                 }
 143         } while (1);
 144 }
 145
 146 /*
 147  * internal IRQs operations: only mask/unmask on PERF irq mask
 148  * register.
 149  */
 150 static void bcm63xx_internal_irq_mask(struct irq_data *d)
 151 {
 152         internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
 153 }
 154
 155 static void bcm63xx_internal_irq_unmask(struct irq_data *d)
 156 {
 157         internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
 158 }
 159
 160 /*
 161  * external IRQs operations: mask/unmask and clear on PERF external
 162  * irq control register.
 163  */
 164 static void bcm63xx_external_irq_mask(struct irq_data *d)
 165 {
 166         unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
 167         u32 reg, regaddr;
 168
 169         regaddr = get_ext_irq_perf_reg(irq);
 170         reg = bcm_perf_readl(regaddr);
 171
 172         if (BCMCPU_IS_6348())
 173                 reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
 174         else
 175                 reg &= ~EXTIRQ_CFG_MASK(irq % 4);
 176
 177         bcm_perf_writel(reg, regaddr);
 178         if (is_ext_irq_cascaded)
 179                 internal_irq_mask(irq + ext_irq_start);
 180 }
 181
 182 static void bcm63xx_external_irq_unmask(struct irq_data *d)
 183 {
 184         unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
 185         u32 reg, regaddr;
 186
 187         regaddr = get_ext_irq_perf_reg(irq);
 188         reg = bcm_perf_readl(regaddr);
 189
 190         if (BCMCPU_IS_6348())
 191                 reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
 192         else
 193                 reg |= EXTIRQ_CFG_MASK(irq % 4);
 194
 195         bcm_perf_writel(reg, regaddr);
 196
 197         if (is_ext_irq_cascaded)
 198                 internal_irq_unmask(irq + ext_irq_start);
 199 }
 200
 201 static void bcm63xx_external_irq_clear(struct irq_data *d)
 202 {
 203         unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
 204         u32 reg, regaddr;
 205
 206         regaddr = get_ext_irq_perf_reg(irq);
 207         reg = bcm_perf_readl(regaddr);
 208
 209         if (BCMCPU_IS_6348())
 210                 reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
 211         else
 212                 reg |= EXTIRQ_CFG_CLEAR(irq % 4);
 213
 214         bcm_perf_writel(reg, regaddr);
 215 }
 216
 217 static int bcm63xx_external_irq_set_type(struct irq_data *d,
 218                                          unsigned int flow_type)
 219 {
 220         unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
 221         u32 reg, regaddr;
 222         int levelsense, sense, bothedge;
 223
 224         flow_type &= IRQ_TYPE_SENSE_MASK;
 225
 226         if (flow_type == IRQ_TYPE_NONE)
 227                 flow_type = IRQ_TYPE_LEVEL_LOW;
 228
 229         levelsense = sense = bothedge = 0;
 230         switch (flow_type) {
 231         case IRQ_TYPE_EDGE_BOTH:
 232                 bothedge = 1;
 233                 break;
 234
 235         case IRQ_TYPE_EDGE_RISING:
 236                 sense = 1;
 237                 break;
 238
 239         case IRQ_TYPE_EDGE_FALLING:
 240                 break;
 241
 242         case IRQ_TYPE_LEVEL_HIGH:
 243                 levelsense = 1;
 244                 sense = 1;
 245                 break;
 246
 247         case IRQ_TYPE_LEVEL_LOW:
 248                 levelsense = 1;
 249                 break;
 250
 251         default:
 252                 printk(KERN_ERR "bogus flow type combination given !\n");
 253                 return -EINVAL;
 254         }
 255
 256         regaddr = get_ext_irq_perf_reg(irq);
 257         reg = bcm_perf_readl(regaddr);
 258         irq %= 4;
 259
 260         switch (bcm63xx_get_cpu_id()) {
 261         case BCM6348_CPU_ID:
 262                 if (levelsense)
 263                         reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
 264                 else
 265                         reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
 266                 if (sense)
 267                         reg |= EXTIRQ_CFG_SENSE_6348(irq);
 268                 else
 269                         reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
 270                 if (bothedge)
 271                         reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
 272                 else
 273                         reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
 274                 break;
 275
 276         case BCM3368_CPU_ID:
 277         case BCM6328_CPU_ID:
 278         case BCM6338_CPU_ID:
 279         case BCM6345_CPU_ID:
 280         case BCM6358_CPU_ID:
 281         case BCM6362_CPU_ID:
 282         case BCM6368_CPU_ID:
 283                 if (levelsense)
 284                         reg |= EXTIRQ_CFG_LEVELSENSE(irq);
 285                 else
 286                         reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
 287                 if (sense)
 288                         reg |= EXTIRQ_CFG_SENSE(irq);
 289                 else
 290                         reg &= ~EXTIRQ_CFG_SENSE(irq);
 291                 if (bothedge)
 292                         reg |= EXTIRQ_CFG_BOTHEDGE(irq);
 293                 else
 294                         reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
 295                 break;
 296         default:
 297                 BUG();
 298         }
 299
 300         bcm_perf_writel(reg, regaddr);
 301
 302         irqd_set_trigger_type(d, flow_type);
 303         if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 304                 __irq_set_handler_locked(d->irq, handle_level_irq);
 305         else
 306                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 307
 308         return IRQ_SET_MASK_OK_NOCOPY;
 309 }
 310
 311 static struct irq_chip bcm63xx_internal_irq_chip = {
 312         .name           = "bcm63xx_ipic",
 313         .irq_mask       = bcm63xx_internal_irq_mask,
 314         .irq_unmask     = bcm63xx_internal_irq_unmask,
 315 };
 316
 317 static struct irq_chip bcm63xx_external_irq_chip = {
 318         .name           = "bcm63xx_epic",
 319         .irq_ack        = bcm63xx_external_irq_clear,
 320
 321         .irq_mask       = bcm63xx_external_irq_mask,
 322         .irq_unmask     = bcm63xx_external_irq_unmask,
 323
 324         .irq_set_type   = bcm63xx_external_irq_set_type,
 325 };
 326
 327 static struct irqaction cpu_ip2_cascade_action = {
 328         .handler        = no_action,
 329         .name           = "cascade_ip2",
 330         .flags          = IRQF_NO_THREAD,
 331 };
 332
 333 static struct irqaction cpu_ext_cascade_action = {
 334         .handler        = no_action,
 335         .name           = "cascade_extirq",
 336         .flags          = IRQF_NO_THREAD,
 337 };
 338
 339 static void bcm63xx_init_irq(void)
 340 {
 341         int irq_bits;
 342
 343         irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
 344         irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
 345
 346         switch (bcm63xx_get_cpu_id()) {
 347         case BCM3368_CPU_ID:
 348                 irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
 349                 irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
 350                 irq_bits = 32;
 351                 ext_irq_count = 4;
 352                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
 353                 break;
 354         case BCM6328_CPU_ID:
 355                 irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
 356                 irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
 357                 irq_bits = 64;
 358                 ext_irq_count = 4;
 359                 is_ext_irq_cascaded = 1;
 360                 ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
 361                 ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
 362                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
 363                 break;
 364         case BCM6338_CPU_ID:
 365                 irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
 366                 irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
 367                 irq_bits = 32;
 368                 ext_irq_count = 4;
 369                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
 370                 break;
 371         case BCM6345_CPU_ID:
 372                 irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
 373                 irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
 374                 irq_bits = 32;
 375                 ext_irq_count = 4;
 376                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
 377                 break;
 378         case BCM6348_CPU_ID:
 379                 irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
 380                 irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
 381                 irq_bits = 32;
 382                 ext_irq_count = 4;
 383                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
 384                 break;
 385         case BCM6358_CPU_ID:
 386                 irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
 387                 irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
 388                 irq_bits = 32;
 389                 ext_irq_count = 4;
 390                 is_ext_irq_cascaded = 1;
 391                 ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
 392                 ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
 393                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
 394                 break;
 395         case BCM6362_CPU_ID:
 396                 irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
 397                 irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
 398                 irq_bits = 64;
 399                 ext_irq_count = 4;
 400                 is_ext_irq_cascaded = 1;
 401                 ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
 402                 ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
 403                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
 404                 break;
 405         case BCM6368_CPU_ID:
 406                 irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
 407                 irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
 408                 irq_bits = 64;
 409                 ext_irq_count = 6;
 410                 is_ext_irq_cascaded = 1;
 411                 ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
 412                 ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
 413                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
 414                 ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
 415                 break;
 416         default:
 417                 BUG();
 418         }
 419
 420         if (irq_bits == 32) {
 421                 dispatch_internal = __dispatch_internal_32;
 422                 internal_irq_mask = __internal_irq_mask_32;
 423                 internal_irq_unmask = __internal_irq_unmask_32;
 424         } else {
 425                 dispatch_internal = __dispatch_internal_64;
 426                 internal_irq_mask = __internal_irq_mask_64;
 427                 internal_irq_unmask = __internal_irq_unmask_64;
 428         }
 429 }
 430
 431 void __init arch_init_irq(void)
 432 {
 433         int i;
 434
 435         bcm63xx_init_irq();
 436         mips_cpu_irq_init();
 437         for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
 438                 irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
 439                                          handle_level_irq);
 440
 441         for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
 442                 irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
 443                                          handle_edge_irq);
 444
 445         if (!is_ext_irq_cascaded) {
 446                 for (i = 3; i < 3 + ext_irq_count; ++i)
 447                         setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
 448         }
 449
 450         setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
 451 }