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Merge tag 'master-2014-11-25' of git://git.kernel.org/pub/scm/linux/kernel/git/linvil...
[deliverable/linux.git] / arch / mips / cavium-octeon / octeon-irq.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2012 Cavium, Inc.
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/irqdomain.h>
11 #include <linux/bitops.h>
12 #include <linux/percpu.h>
13 #include <linux/slab.h>
14 #include <linux/irq.h>
15 #include <linux/smp.h>
16 #include <linux/of.h>
17
18 #include <asm/octeon/octeon.h>
19 #include <asm/octeon/cvmx-ciu2-defs.h>
20
21 static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror);
22 static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror);
23 static DEFINE_PER_CPU(raw_spinlock_t, octeon_irq_ciu_spinlock);
24
25 static __read_mostly u8 octeon_irq_ciu_to_irq[8][64];
26
27 union octeon_ciu_chip_data {
28 void *p;
29 unsigned long l;
30 struct {
31 unsigned long line:6;
32 unsigned long bit:6;
33 unsigned long gpio_line:6;
34 } s;
35 };
36
37 struct octeon_core_chip_data {
38 struct mutex core_irq_mutex;
39 bool current_en;
40 bool desired_en;
41 u8 bit;
42 };
43
44 #define MIPS_CORE_IRQ_LINES 8
45
46 static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES];
47
48 static void octeon_irq_set_ciu_mapping(int irq, int line, int bit, int gpio_line,
49 struct irq_chip *chip,
50 irq_flow_handler_t handler)
51 {
52 union octeon_ciu_chip_data cd;
53
54 irq_set_chip_and_handler(irq, chip, handler);
55
56 cd.l = 0;
57 cd.s.line = line;
58 cd.s.bit = bit;
59 cd.s.gpio_line = gpio_line;
60
61 irq_set_chip_data(irq, cd.p);
62 octeon_irq_ciu_to_irq[line][bit] = irq;
63 }
64
65 static void octeon_irq_force_ciu_mapping(struct irq_domain *domain,
66 int irq, int line, int bit)
67 {
68 irq_domain_associate(domain, irq, line << 6 | bit);
69 }
70
71 static int octeon_coreid_for_cpu(int cpu)
72 {
73 #ifdef CONFIG_SMP
74 return cpu_logical_map(cpu);
75 #else
76 return cvmx_get_core_num();
77 #endif
78 }
79
80 static int octeon_cpu_for_coreid(int coreid)
81 {
82 #ifdef CONFIG_SMP
83 return cpu_number_map(coreid);
84 #else
85 return smp_processor_id();
86 #endif
87 }
88
89 static void octeon_irq_core_ack(struct irq_data *data)
90 {
91 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
92 unsigned int bit = cd->bit;
93
94 /*
95 * We don't need to disable IRQs to make these atomic since
96 * they are already disabled earlier in the low level
97 * interrupt code.
98 */
99 clear_c0_status(0x100 << bit);
100 /* The two user interrupts must be cleared manually. */
101 if (bit < 2)
102 clear_c0_cause(0x100 << bit);
103 }
104
105 static void octeon_irq_core_eoi(struct irq_data *data)
106 {
107 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
108
109 /*
110 * We don't need to disable IRQs to make these atomic since
111 * they are already disabled earlier in the low level
112 * interrupt code.
113 */
114 set_c0_status(0x100 << cd->bit);
115 }
116
117 static void octeon_irq_core_set_enable_local(void *arg)
118 {
119 struct irq_data *data = arg;
120 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
121 unsigned int mask = 0x100 << cd->bit;
122
123 /*
124 * Interrupts are already disabled, so these are atomic.
125 */
126 if (cd->desired_en)
127 set_c0_status(mask);
128 else
129 clear_c0_status(mask);
130
131 }
132
133 static void octeon_irq_core_disable(struct irq_data *data)
134 {
135 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
136 cd->desired_en = false;
137 }
138
139 static void octeon_irq_core_enable(struct irq_data *data)
140 {
141 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
142 cd->desired_en = true;
143 }
144
145 static void octeon_irq_core_bus_lock(struct irq_data *data)
146 {
147 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
148
149 mutex_lock(&cd->core_irq_mutex);
150 }
151
152 static void octeon_irq_core_bus_sync_unlock(struct irq_data *data)
153 {
154 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
155
156 if (cd->desired_en != cd->current_en) {
157 on_each_cpu(octeon_irq_core_set_enable_local, data, 1);
158
159 cd->current_en = cd->desired_en;
160 }
161
162 mutex_unlock(&cd->core_irq_mutex);
163 }
164
165 static struct irq_chip octeon_irq_chip_core = {
166 .name = "Core",
167 .irq_enable = octeon_irq_core_enable,
168 .irq_disable = octeon_irq_core_disable,
169 .irq_ack = octeon_irq_core_ack,
170 .irq_eoi = octeon_irq_core_eoi,
171 .irq_bus_lock = octeon_irq_core_bus_lock,
172 .irq_bus_sync_unlock = octeon_irq_core_bus_sync_unlock,
173
174 .irq_cpu_online = octeon_irq_core_eoi,
175 .irq_cpu_offline = octeon_irq_core_ack,
176 .flags = IRQCHIP_ONOFFLINE_ENABLED,
177 };
178
179 static void __init octeon_irq_init_core(void)
180 {
181 int i;
182 int irq;
183 struct octeon_core_chip_data *cd;
184
185 for (i = 0; i < MIPS_CORE_IRQ_LINES; i++) {
186 cd = &octeon_irq_core_chip_data[i];
187 cd->current_en = false;
188 cd->desired_en = false;
189 cd->bit = i;
190 mutex_init(&cd->core_irq_mutex);
191
192 irq = OCTEON_IRQ_SW0 + i;
193 irq_set_chip_data(irq, cd);
194 irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
195 handle_percpu_irq);
196 }
197 }
198
199 static int next_cpu_for_irq(struct irq_data *data)
200 {
201
202 #ifdef CONFIG_SMP
203 int cpu;
204 int weight = cpumask_weight(data->affinity);
205
206 if (weight > 1) {
207 cpu = smp_processor_id();
208 for (;;) {
209 cpu = cpumask_next(cpu, data->affinity);
210 if (cpu >= nr_cpu_ids) {
211 cpu = -1;
212 continue;
213 } else if (cpumask_test_cpu(cpu, cpu_online_mask)) {
214 break;
215 }
216 }
217 } else if (weight == 1) {
218 cpu = cpumask_first(data->affinity);
219 } else {
220 cpu = smp_processor_id();
221 }
222 return cpu;
223 #else
224 return smp_processor_id();
225 #endif
226 }
227
228 static void octeon_irq_ciu_enable(struct irq_data *data)
229 {
230 int cpu = next_cpu_for_irq(data);
231 int coreid = octeon_coreid_for_cpu(cpu);
232 unsigned long *pen;
233 unsigned long flags;
234 union octeon_ciu_chip_data cd;
235 raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
236
237 cd.p = irq_data_get_irq_chip_data(data);
238
239 raw_spin_lock_irqsave(lock, flags);
240 if (cd.s.line == 0) {
241 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
242 __set_bit(cd.s.bit, pen);
243 /*
244 * Must be visible to octeon_irq_ip{2,3}_ciu() before
245 * enabling the irq.
246 */
247 wmb();
248 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
249 } else {
250 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
251 __set_bit(cd.s.bit, pen);
252 /*
253 * Must be visible to octeon_irq_ip{2,3}_ciu() before
254 * enabling the irq.
255 */
256 wmb();
257 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
258 }
259 raw_spin_unlock_irqrestore(lock, flags);
260 }
261
262 static void octeon_irq_ciu_enable_local(struct irq_data *data)
263 {
264 unsigned long *pen;
265 unsigned long flags;
266 union octeon_ciu_chip_data cd;
267 raw_spinlock_t *lock = this_cpu_ptr(&octeon_irq_ciu_spinlock);
268
269 cd.p = irq_data_get_irq_chip_data(data);
270
271 raw_spin_lock_irqsave(lock, flags);
272 if (cd.s.line == 0) {
273 pen = this_cpu_ptr(&octeon_irq_ciu0_en_mirror);
274 __set_bit(cd.s.bit, pen);
275 /*
276 * Must be visible to octeon_irq_ip{2,3}_ciu() before
277 * enabling the irq.
278 */
279 wmb();
280 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
281 } else {
282 pen = this_cpu_ptr(&octeon_irq_ciu1_en_mirror);
283 __set_bit(cd.s.bit, pen);
284 /*
285 * Must be visible to octeon_irq_ip{2,3}_ciu() before
286 * enabling the irq.
287 */
288 wmb();
289 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
290 }
291 raw_spin_unlock_irqrestore(lock, flags);
292 }
293
294 static void octeon_irq_ciu_disable_local(struct irq_data *data)
295 {
296 unsigned long *pen;
297 unsigned long flags;
298 union octeon_ciu_chip_data cd;
299 raw_spinlock_t *lock = this_cpu_ptr(&octeon_irq_ciu_spinlock);
300
301 cd.p = irq_data_get_irq_chip_data(data);
302
303 raw_spin_lock_irqsave(lock, flags);
304 if (cd.s.line == 0) {
305 pen = this_cpu_ptr(&octeon_irq_ciu0_en_mirror);
306 __clear_bit(cd.s.bit, pen);
307 /*
308 * Must be visible to octeon_irq_ip{2,3}_ciu() before
309 * enabling the irq.
310 */
311 wmb();
312 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
313 } else {
314 pen = this_cpu_ptr(&octeon_irq_ciu1_en_mirror);
315 __clear_bit(cd.s.bit, pen);
316 /*
317 * Must be visible to octeon_irq_ip{2,3}_ciu() before
318 * enabling the irq.
319 */
320 wmb();
321 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
322 }
323 raw_spin_unlock_irqrestore(lock, flags);
324 }
325
326 static void octeon_irq_ciu_disable_all(struct irq_data *data)
327 {
328 unsigned long flags;
329 unsigned long *pen;
330 int cpu;
331 union octeon_ciu_chip_data cd;
332 raw_spinlock_t *lock;
333
334 cd.p = irq_data_get_irq_chip_data(data);
335
336 for_each_online_cpu(cpu) {
337 int coreid = octeon_coreid_for_cpu(cpu);
338 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
339 if (cd.s.line == 0)
340 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
341 else
342 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
343
344 raw_spin_lock_irqsave(lock, flags);
345 __clear_bit(cd.s.bit, pen);
346 /*
347 * Must be visible to octeon_irq_ip{2,3}_ciu() before
348 * enabling the irq.
349 */
350 wmb();
351 if (cd.s.line == 0)
352 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
353 else
354 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
355 raw_spin_unlock_irqrestore(lock, flags);
356 }
357 }
358
359 static void octeon_irq_ciu_enable_all(struct irq_data *data)
360 {
361 unsigned long flags;
362 unsigned long *pen;
363 int cpu;
364 union octeon_ciu_chip_data cd;
365 raw_spinlock_t *lock;
366
367 cd.p = irq_data_get_irq_chip_data(data);
368
369 for_each_online_cpu(cpu) {
370 int coreid = octeon_coreid_for_cpu(cpu);
371 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
372 if (cd.s.line == 0)
373 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
374 else
375 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
376
377 raw_spin_lock_irqsave(lock, flags);
378 __set_bit(cd.s.bit, pen);
379 /*
380 * Must be visible to octeon_irq_ip{2,3}_ciu() before
381 * enabling the irq.
382 */
383 wmb();
384 if (cd.s.line == 0)
385 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
386 else
387 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
388 raw_spin_unlock_irqrestore(lock, flags);
389 }
390 }
391
392 /*
393 * Enable the irq on the next core in the affinity set for chips that
394 * have the EN*_W1{S,C} registers.
395 */
396 static void octeon_irq_ciu_enable_v2(struct irq_data *data)
397 {
398 u64 mask;
399 int cpu = next_cpu_for_irq(data);
400 union octeon_ciu_chip_data cd;
401
402 cd.p = irq_data_get_irq_chip_data(data);
403 mask = 1ull << (cd.s.bit);
404
405 /*
406 * Called under the desc lock, so these should never get out
407 * of sync.
408 */
409 if (cd.s.line == 0) {
410 int index = octeon_coreid_for_cpu(cpu) * 2;
411 set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
412 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
413 } else {
414 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
415 set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
416 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
417 }
418 }
419
420 /*
421 * Enable the irq on the current CPU for chips that
422 * have the EN*_W1{S,C} registers.
423 */
424 static void octeon_irq_ciu_enable_local_v2(struct irq_data *data)
425 {
426 u64 mask;
427 union octeon_ciu_chip_data cd;
428
429 cd.p = irq_data_get_irq_chip_data(data);
430 mask = 1ull << (cd.s.bit);
431
432 if (cd.s.line == 0) {
433 int index = cvmx_get_core_num() * 2;
434 set_bit(cd.s.bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror));
435 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
436 } else {
437 int index = cvmx_get_core_num() * 2 + 1;
438 set_bit(cd.s.bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror));
439 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
440 }
441 }
442
443 static void octeon_irq_ciu_disable_local_v2(struct irq_data *data)
444 {
445 u64 mask;
446 union octeon_ciu_chip_data cd;
447
448 cd.p = irq_data_get_irq_chip_data(data);
449 mask = 1ull << (cd.s.bit);
450
451 if (cd.s.line == 0) {
452 int index = cvmx_get_core_num() * 2;
453 clear_bit(cd.s.bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror));
454 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
455 } else {
456 int index = cvmx_get_core_num() * 2 + 1;
457 clear_bit(cd.s.bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror));
458 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
459 }
460 }
461
462 /*
463 * Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq.
464 */
465 static void octeon_irq_ciu_ack(struct irq_data *data)
466 {
467 u64 mask;
468 union octeon_ciu_chip_data cd;
469
470 cd.p = irq_data_get_irq_chip_data(data);
471 mask = 1ull << (cd.s.bit);
472
473 if (cd.s.line == 0) {
474 int index = cvmx_get_core_num() * 2;
475 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
476 } else {
477 cvmx_write_csr(CVMX_CIU_INT_SUM1, mask);
478 }
479 }
480
481 /*
482 * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
483 * registers.
484 */
485 static void octeon_irq_ciu_disable_all_v2(struct irq_data *data)
486 {
487 int cpu;
488 u64 mask;
489 union octeon_ciu_chip_data cd;
490
491 cd.p = irq_data_get_irq_chip_data(data);
492 mask = 1ull << (cd.s.bit);
493
494 if (cd.s.line == 0) {
495 for_each_online_cpu(cpu) {
496 int index = octeon_coreid_for_cpu(cpu) * 2;
497 clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
498 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
499 }
500 } else {
501 for_each_online_cpu(cpu) {
502 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
503 clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
504 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
505 }
506 }
507 }
508
509 /*
510 * Enable the irq on the all cores for chips that have the EN*_W1{S,C}
511 * registers.
512 */
513 static void octeon_irq_ciu_enable_all_v2(struct irq_data *data)
514 {
515 int cpu;
516 u64 mask;
517 union octeon_ciu_chip_data cd;
518
519 cd.p = irq_data_get_irq_chip_data(data);
520 mask = 1ull << (cd.s.bit);
521
522 if (cd.s.line == 0) {
523 for_each_online_cpu(cpu) {
524 int index = octeon_coreid_for_cpu(cpu) * 2;
525 set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
526 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
527 }
528 } else {
529 for_each_online_cpu(cpu) {
530 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
531 set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
532 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
533 }
534 }
535 }
536
537 static void octeon_irq_gpio_setup(struct irq_data *data)
538 {
539 union cvmx_gpio_bit_cfgx cfg;
540 union octeon_ciu_chip_data cd;
541 u32 t = irqd_get_trigger_type(data);
542
543 cd.p = irq_data_get_irq_chip_data(data);
544
545 cfg.u64 = 0;
546 cfg.s.int_en = 1;
547 cfg.s.int_type = (t & IRQ_TYPE_EDGE_BOTH) != 0;
548 cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0;
549
550 /* 140 nS glitch filter*/
551 cfg.s.fil_cnt = 7;
552 cfg.s.fil_sel = 3;
553
554 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), cfg.u64);
555 }
556
557 static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data)
558 {
559 octeon_irq_gpio_setup(data);
560 octeon_irq_ciu_enable_v2(data);
561 }
562
563 static void octeon_irq_ciu_enable_gpio(struct irq_data *data)
564 {
565 octeon_irq_gpio_setup(data);
566 octeon_irq_ciu_enable(data);
567 }
568
569 static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t)
570 {
571 irqd_set_trigger_type(data, t);
572 octeon_irq_gpio_setup(data);
573
574 return IRQ_SET_MASK_OK;
575 }
576
577 static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data)
578 {
579 union octeon_ciu_chip_data cd;
580
581 cd.p = irq_data_get_irq_chip_data(data);
582 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), 0);
583
584 octeon_irq_ciu_disable_all_v2(data);
585 }
586
587 static void octeon_irq_ciu_disable_gpio(struct irq_data *data)
588 {
589 union octeon_ciu_chip_data cd;
590
591 cd.p = irq_data_get_irq_chip_data(data);
592 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), 0);
593
594 octeon_irq_ciu_disable_all(data);
595 }
596
597 static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
598 {
599 union octeon_ciu_chip_data cd;
600 u64 mask;
601
602 cd.p = irq_data_get_irq_chip_data(data);
603 mask = 1ull << (cd.s.gpio_line);
604
605 cvmx_write_csr(CVMX_GPIO_INT_CLR, mask);
606 }
607
608 static void octeon_irq_handle_gpio(unsigned int irq, struct irq_desc *desc)
609 {
610 if (irq_get_trigger_type(irq) & IRQ_TYPE_EDGE_BOTH)
611 handle_edge_irq(irq, desc);
612 else
613 handle_level_irq(irq, desc);
614 }
615
616 #ifdef CONFIG_SMP
617
618 static void octeon_irq_cpu_offline_ciu(struct irq_data *data)
619 {
620 int cpu = smp_processor_id();
621 cpumask_t new_affinity;
622
623 if (!cpumask_test_cpu(cpu, data->affinity))
624 return;
625
626 if (cpumask_weight(data->affinity) > 1) {
627 /*
628 * It has multi CPU affinity, just remove this CPU
629 * from the affinity set.
630 */
631 cpumask_copy(&new_affinity, data->affinity);
632 cpumask_clear_cpu(cpu, &new_affinity);
633 } else {
634 /* Otherwise, put it on lowest numbered online CPU. */
635 cpumask_clear(&new_affinity);
636 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
637 }
638 irq_set_affinity_locked(data, &new_affinity, false);
639 }
640
641 static int octeon_irq_ciu_set_affinity(struct irq_data *data,
642 const struct cpumask *dest, bool force)
643 {
644 int cpu;
645 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
646 unsigned long flags;
647 union octeon_ciu_chip_data cd;
648 unsigned long *pen;
649 raw_spinlock_t *lock;
650
651 cd.p = irq_data_get_irq_chip_data(data);
652
653 /*
654 * For non-v2 CIU, we will allow only single CPU affinity.
655 * This removes the need to do locking in the .ack/.eoi
656 * functions.
657 */
658 if (cpumask_weight(dest) != 1)
659 return -EINVAL;
660
661 if (!enable_one)
662 return 0;
663
664
665 for_each_online_cpu(cpu) {
666 int coreid = octeon_coreid_for_cpu(cpu);
667
668 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
669 raw_spin_lock_irqsave(lock, flags);
670
671 if (cd.s.line == 0)
672 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
673 else
674 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
675
676 if (cpumask_test_cpu(cpu, dest) && enable_one) {
677 enable_one = 0;
678 __set_bit(cd.s.bit, pen);
679 } else {
680 __clear_bit(cd.s.bit, pen);
681 }
682 /*
683 * Must be visible to octeon_irq_ip{2,3}_ciu() before
684 * enabling the irq.
685 */
686 wmb();
687
688 if (cd.s.line == 0)
689 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
690 else
691 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
692
693 raw_spin_unlock_irqrestore(lock, flags);
694 }
695 return 0;
696 }
697
698 /*
699 * Set affinity for the irq for chips that have the EN*_W1{S,C}
700 * registers.
701 */
702 static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data,
703 const struct cpumask *dest,
704 bool force)
705 {
706 int cpu;
707 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
708 u64 mask;
709 union octeon_ciu_chip_data cd;
710
711 if (!enable_one)
712 return 0;
713
714 cd.p = irq_data_get_irq_chip_data(data);
715 mask = 1ull << cd.s.bit;
716
717 if (cd.s.line == 0) {
718 for_each_online_cpu(cpu) {
719 unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
720 int index = octeon_coreid_for_cpu(cpu) * 2;
721 if (cpumask_test_cpu(cpu, dest) && enable_one) {
722 enable_one = false;
723 set_bit(cd.s.bit, pen);
724 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
725 } else {
726 clear_bit(cd.s.bit, pen);
727 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
728 }
729 }
730 } else {
731 for_each_online_cpu(cpu) {
732 unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
733 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
734 if (cpumask_test_cpu(cpu, dest) && enable_one) {
735 enable_one = false;
736 set_bit(cd.s.bit, pen);
737 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
738 } else {
739 clear_bit(cd.s.bit, pen);
740 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
741 }
742 }
743 }
744 return 0;
745 }
746 #endif
747
748 /*
749 * Newer octeon chips have support for lockless CIU operation.
750 */
751 static struct irq_chip octeon_irq_chip_ciu_v2 = {
752 .name = "CIU",
753 .irq_enable = octeon_irq_ciu_enable_v2,
754 .irq_disable = octeon_irq_ciu_disable_all_v2,
755 .irq_ack = octeon_irq_ciu_ack,
756 .irq_mask = octeon_irq_ciu_disable_local_v2,
757 .irq_unmask = octeon_irq_ciu_enable_v2,
758 #ifdef CONFIG_SMP
759 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
760 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
761 #endif
762 };
763
764 static struct irq_chip octeon_irq_chip_ciu = {
765 .name = "CIU",
766 .irq_enable = octeon_irq_ciu_enable,
767 .irq_disable = octeon_irq_ciu_disable_all,
768 .irq_ack = octeon_irq_ciu_ack,
769 .irq_mask = octeon_irq_ciu_disable_local,
770 .irq_unmask = octeon_irq_ciu_enable,
771 #ifdef CONFIG_SMP
772 .irq_set_affinity = octeon_irq_ciu_set_affinity,
773 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
774 #endif
775 };
776
777 /* The mbox versions don't do any affinity or round-robin. */
778 static struct irq_chip octeon_irq_chip_ciu_mbox_v2 = {
779 .name = "CIU-M",
780 .irq_enable = octeon_irq_ciu_enable_all_v2,
781 .irq_disable = octeon_irq_ciu_disable_all_v2,
782 .irq_ack = octeon_irq_ciu_disable_local_v2,
783 .irq_eoi = octeon_irq_ciu_enable_local_v2,
784
785 .irq_cpu_online = octeon_irq_ciu_enable_local_v2,
786 .irq_cpu_offline = octeon_irq_ciu_disable_local_v2,
787 .flags = IRQCHIP_ONOFFLINE_ENABLED,
788 };
789
790 static struct irq_chip octeon_irq_chip_ciu_mbox = {
791 .name = "CIU-M",
792 .irq_enable = octeon_irq_ciu_enable_all,
793 .irq_disable = octeon_irq_ciu_disable_all,
794 .irq_ack = octeon_irq_ciu_disable_local,
795 .irq_eoi = octeon_irq_ciu_enable_local,
796
797 .irq_cpu_online = octeon_irq_ciu_enable_local,
798 .irq_cpu_offline = octeon_irq_ciu_disable_local,
799 .flags = IRQCHIP_ONOFFLINE_ENABLED,
800 };
801
802 static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = {
803 .name = "CIU-GPIO",
804 .irq_enable = octeon_irq_ciu_enable_gpio_v2,
805 .irq_disable = octeon_irq_ciu_disable_gpio_v2,
806 .irq_ack = octeon_irq_ciu_gpio_ack,
807 .irq_mask = octeon_irq_ciu_disable_local_v2,
808 .irq_unmask = octeon_irq_ciu_enable_v2,
809 .irq_set_type = octeon_irq_ciu_gpio_set_type,
810 #ifdef CONFIG_SMP
811 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
812 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
813 #endif
814 .flags = IRQCHIP_SET_TYPE_MASKED,
815 };
816
817 static struct irq_chip octeon_irq_chip_ciu_gpio = {
818 .name = "CIU-GPIO",
819 .irq_enable = octeon_irq_ciu_enable_gpio,
820 .irq_disable = octeon_irq_ciu_disable_gpio,
821 .irq_mask = octeon_irq_ciu_disable_local,
822 .irq_unmask = octeon_irq_ciu_enable,
823 .irq_ack = octeon_irq_ciu_gpio_ack,
824 .irq_set_type = octeon_irq_ciu_gpio_set_type,
825 #ifdef CONFIG_SMP
826 .irq_set_affinity = octeon_irq_ciu_set_affinity,
827 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
828 #endif
829 .flags = IRQCHIP_SET_TYPE_MASKED,
830 };
831
832 /*
833 * Watchdog interrupts are special. They are associated with a single
834 * core, so we hardwire the affinity to that core.
835 */
836 static void octeon_irq_ciu_wd_enable(struct irq_data *data)
837 {
838 unsigned long flags;
839 unsigned long *pen;
840 int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
841 int cpu = octeon_cpu_for_coreid(coreid);
842 raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
843
844 raw_spin_lock_irqsave(lock, flags);
845 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
846 __set_bit(coreid, pen);
847 /*
848 * Must be visible to octeon_irq_ip{2,3}_ciu() before enabling
849 * the irq.
850 */
851 wmb();
852 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
853 raw_spin_unlock_irqrestore(lock, flags);
854 }
855
856 /*
857 * Watchdog interrupts are special. They are associated with a single
858 * core, so we hardwire the affinity to that core.
859 */
860 static void octeon_irq_ciu1_wd_enable_v2(struct irq_data *data)
861 {
862 int coreid = data->irq - OCTEON_IRQ_WDOG0;
863 int cpu = octeon_cpu_for_coreid(coreid);
864
865 set_bit(coreid, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
866 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid);
867 }
868
869
870 static struct irq_chip octeon_irq_chip_ciu_wd_v2 = {
871 .name = "CIU-W",
872 .irq_enable = octeon_irq_ciu1_wd_enable_v2,
873 .irq_disable = octeon_irq_ciu_disable_all_v2,
874 .irq_mask = octeon_irq_ciu_disable_local_v2,
875 .irq_unmask = octeon_irq_ciu_enable_local_v2,
876 };
877
878 static struct irq_chip octeon_irq_chip_ciu_wd = {
879 .name = "CIU-W",
880 .irq_enable = octeon_irq_ciu_wd_enable,
881 .irq_disable = octeon_irq_ciu_disable_all,
882 .irq_mask = octeon_irq_ciu_disable_local,
883 .irq_unmask = octeon_irq_ciu_enable_local,
884 };
885
886 static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit)
887 {
888 bool edge = false;
889
890 if (line == 0)
891 switch (bit) {
892 case 48 ... 49: /* GMX DRP */
893 case 50: /* IPD_DRP */
894 case 52 ... 55: /* Timers */
895 case 58: /* MPI */
896 edge = true;
897 break;
898 default:
899 break;
900 }
901 else /* line == 1 */
902 switch (bit) {
903 case 47: /* PTP */
904 edge = true;
905 break;
906 default:
907 break;
908 }
909 return edge;
910 }
911
912 struct octeon_irq_gpio_domain_data {
913 unsigned int base_hwirq;
914 };
915
916 static int octeon_irq_gpio_xlat(struct irq_domain *d,
917 struct device_node *node,
918 const u32 *intspec,
919 unsigned int intsize,
920 unsigned long *out_hwirq,
921 unsigned int *out_type)
922 {
923 unsigned int type;
924 unsigned int pin;
925 unsigned int trigger;
926
927 if (d->of_node != node)
928 return -EINVAL;
929
930 if (intsize < 2)
931 return -EINVAL;
932
933 pin = intspec[0];
934 if (pin >= 16)
935 return -EINVAL;
936
937 trigger = intspec[1];
938
939 switch (trigger) {
940 case 1:
941 type = IRQ_TYPE_EDGE_RISING;
942 break;
943 case 2:
944 type = IRQ_TYPE_EDGE_FALLING;
945 break;
946 case 4:
947 type = IRQ_TYPE_LEVEL_HIGH;
948 break;
949 case 8:
950 type = IRQ_TYPE_LEVEL_LOW;
951 break;
952 default:
953 pr_err("Error: (%s) Invalid irq trigger specification: %x\n",
954 node->name,
955 trigger);
956 type = IRQ_TYPE_LEVEL_LOW;
957 break;
958 }
959 *out_type = type;
960 *out_hwirq = pin;
961
962 return 0;
963 }
964
965 static int octeon_irq_ciu_xlat(struct irq_domain *d,
966 struct device_node *node,
967 const u32 *intspec,
968 unsigned int intsize,
969 unsigned long *out_hwirq,
970 unsigned int *out_type)
971 {
972 unsigned int ciu, bit;
973
974 ciu = intspec[0];
975 bit = intspec[1];
976
977 if (ciu > 1 || bit > 63)
978 return -EINVAL;
979
980 *out_hwirq = (ciu << 6) | bit;
981 *out_type = 0;
982
983 return 0;
984 }
985
986 static struct irq_chip *octeon_irq_ciu_chip;
987 static struct irq_chip *octeon_irq_gpio_chip;
988
989 static bool octeon_irq_virq_in_range(unsigned int virq)
990 {
991 /* We cannot let it overflow the mapping array. */
992 if (virq < (1ul << 8 * sizeof(octeon_irq_ciu_to_irq[0][0])))
993 return true;
994
995 WARN_ONCE(true, "virq out of range %u.\n", virq);
996 return false;
997 }
998
999 static int octeon_irq_ciu_map(struct irq_domain *d,
1000 unsigned int virq, irq_hw_number_t hw)
1001 {
1002 unsigned int line = hw >> 6;
1003 unsigned int bit = hw & 63;
1004
1005 if (!octeon_irq_virq_in_range(virq))
1006 return -EINVAL;
1007
1008 /* Don't map irq if it is reserved for GPIO. */
1009 if (line == 0 && bit >= 16 && bit <32)
1010 return 0;
1011
1012 if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
1013 return -EINVAL;
1014
1015 if (octeon_irq_ciu_is_edge(line, bit))
1016 octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1017 octeon_irq_ciu_chip,
1018 handle_edge_irq);
1019 else
1020 octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1021 octeon_irq_ciu_chip,
1022 handle_level_irq);
1023
1024 return 0;
1025 }
1026
1027 static int octeon_irq_gpio_map_common(struct irq_domain *d,
1028 unsigned int virq, irq_hw_number_t hw,
1029 int line_limit, struct irq_chip *chip)
1030 {
1031 struct octeon_irq_gpio_domain_data *gpiod = d->host_data;
1032 unsigned int line, bit;
1033
1034 if (!octeon_irq_virq_in_range(virq))
1035 return -EINVAL;
1036
1037 line = (hw + gpiod->base_hwirq) >> 6;
1038 bit = (hw + gpiod->base_hwirq) & 63;
1039 if (line > line_limit || octeon_irq_ciu_to_irq[line][bit] != 0)
1040 return -EINVAL;
1041
1042 octeon_irq_set_ciu_mapping(virq, line, bit, hw,
1043 chip, octeon_irq_handle_gpio);
1044 return 0;
1045 }
1046
1047 static int octeon_irq_gpio_map(struct irq_domain *d,
1048 unsigned int virq, irq_hw_number_t hw)
1049 {
1050 return octeon_irq_gpio_map_common(d, virq, hw, 1, octeon_irq_gpio_chip);
1051 }
1052
1053 static struct irq_domain_ops octeon_irq_domain_ciu_ops = {
1054 .map = octeon_irq_ciu_map,
1055 .xlate = octeon_irq_ciu_xlat,
1056 };
1057
1058 static struct irq_domain_ops octeon_irq_domain_gpio_ops = {
1059 .map = octeon_irq_gpio_map,
1060 .xlate = octeon_irq_gpio_xlat,
1061 };
1062
1063 static void octeon_irq_ip2_ciu(void)
1064 {
1065 const unsigned long core_id = cvmx_get_core_num();
1066 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
1067
1068 ciu_sum &= __this_cpu_read(octeon_irq_ciu0_en_mirror);
1069 if (likely(ciu_sum)) {
1070 int bit = fls64(ciu_sum) - 1;
1071 int irq = octeon_irq_ciu_to_irq[0][bit];
1072 if (likely(irq))
1073 do_IRQ(irq);
1074 else
1075 spurious_interrupt();
1076 } else {
1077 spurious_interrupt();
1078 }
1079 }
1080
1081 static void octeon_irq_ip3_ciu(void)
1082 {
1083 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
1084
1085 ciu_sum &= __this_cpu_read(octeon_irq_ciu1_en_mirror);
1086 if (likely(ciu_sum)) {
1087 int bit = fls64(ciu_sum) - 1;
1088 int irq = octeon_irq_ciu_to_irq[1][bit];
1089 if (likely(irq))
1090 do_IRQ(irq);
1091 else
1092 spurious_interrupt();
1093 } else {
1094 spurious_interrupt();
1095 }
1096 }
1097
1098 static bool octeon_irq_use_ip4;
1099
1100 static void octeon_irq_local_enable_ip4(void *arg)
1101 {
1102 set_c0_status(STATUSF_IP4);
1103 }
1104
1105 static void octeon_irq_ip4_mask(void)
1106 {
1107 clear_c0_status(STATUSF_IP4);
1108 spurious_interrupt();
1109 }
1110
1111 static void (*octeon_irq_ip2)(void);
1112 static void (*octeon_irq_ip3)(void);
1113 static void (*octeon_irq_ip4)(void);
1114
1115 void (*octeon_irq_setup_secondary)(void);
1116
1117 void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t h)
1118 {
1119 octeon_irq_ip4 = h;
1120 octeon_irq_use_ip4 = true;
1121 on_each_cpu(octeon_irq_local_enable_ip4, NULL, 1);
1122 }
1123
1124 static void octeon_irq_percpu_enable(void)
1125 {
1126 irq_cpu_online();
1127 }
1128
1129 static void octeon_irq_init_ciu_percpu(void)
1130 {
1131 int coreid = cvmx_get_core_num();
1132
1133
1134 __this_cpu_write(octeon_irq_ciu0_en_mirror, 0);
1135 __this_cpu_write(octeon_irq_ciu1_en_mirror, 0);
1136 wmb();
1137 raw_spin_lock_init(this_cpu_ptr(&octeon_irq_ciu_spinlock));
1138 /*
1139 * Disable All CIU Interrupts. The ones we need will be
1140 * enabled later. Read the SUM register so we know the write
1141 * completed.
1142 */
1143 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
1144 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
1145 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
1146 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
1147 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
1148 }
1149
1150 static void octeon_irq_init_ciu2_percpu(void)
1151 {
1152 u64 regx, ipx;
1153 int coreid = cvmx_get_core_num();
1154 u64 base = CVMX_CIU2_EN_PPX_IP2_WRKQ(coreid);
1155
1156 /*
1157 * Disable All CIU2 Interrupts. The ones we need will be
1158 * enabled later. Read the SUM register so we know the write
1159 * completed.
1160 *
1161 * There are 9 registers and 3 IPX levels with strides 0x1000
1162 * and 0x200 respectivly. Use loops to clear them.
1163 */
1164 for (regx = 0; regx <= 0x8000; regx += 0x1000) {
1165 for (ipx = 0; ipx <= 0x400; ipx += 0x200)
1166 cvmx_write_csr(base + regx + ipx, 0);
1167 }
1168
1169 cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid));
1170 }
1171
1172 static void octeon_irq_setup_secondary_ciu(void)
1173 {
1174 octeon_irq_init_ciu_percpu();
1175 octeon_irq_percpu_enable();
1176
1177 /* Enable the CIU lines */
1178 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1179 clear_c0_status(STATUSF_IP4);
1180 }
1181
1182 static void octeon_irq_setup_secondary_ciu2(void)
1183 {
1184 octeon_irq_init_ciu2_percpu();
1185 octeon_irq_percpu_enable();
1186
1187 /* Enable the CIU lines */
1188 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1189 if (octeon_irq_use_ip4)
1190 set_c0_status(STATUSF_IP4);
1191 else
1192 clear_c0_status(STATUSF_IP4);
1193 }
1194
1195 static void __init octeon_irq_init_ciu(void)
1196 {
1197 unsigned int i;
1198 struct irq_chip *chip;
1199 struct irq_chip *chip_mbox;
1200 struct irq_chip *chip_wd;
1201 struct device_node *gpio_node;
1202 struct device_node *ciu_node;
1203 struct irq_domain *ciu_domain = NULL;
1204
1205 octeon_irq_init_ciu_percpu();
1206 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
1207
1208 octeon_irq_ip2 = octeon_irq_ip2_ciu;
1209 octeon_irq_ip3 = octeon_irq_ip3_ciu;
1210 if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
1211 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
1212 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
1213 OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
1214 chip = &octeon_irq_chip_ciu_v2;
1215 chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
1216 chip_wd = &octeon_irq_chip_ciu_wd_v2;
1217 octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2;
1218 } else {
1219 chip = &octeon_irq_chip_ciu;
1220 chip_mbox = &octeon_irq_chip_ciu_mbox;
1221 chip_wd = &octeon_irq_chip_ciu_wd;
1222 octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio;
1223 }
1224 octeon_irq_ciu_chip = chip;
1225 octeon_irq_ip4 = octeon_irq_ip4_mask;
1226
1227 /* Mips internal */
1228 octeon_irq_init_core();
1229
1230 gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio");
1231 if (gpio_node) {
1232 struct octeon_irq_gpio_domain_data *gpiod;
1233
1234 gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL);
1235 if (gpiod) {
1236 /* gpio domain host_data is the base hwirq number. */
1237 gpiod->base_hwirq = 16;
1238 irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_gpio_ops, gpiod);
1239 of_node_put(gpio_node);
1240 } else
1241 pr_warn("Cannot allocate memory for GPIO irq_domain.\n");
1242 } else
1243 pr_warn("Cannot find device node for cavium,octeon-3860-gpio.\n");
1244
1245 ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu");
1246 if (ciu_node) {
1247 ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL);
1248 irq_set_default_host(ciu_domain);
1249 of_node_put(ciu_node);
1250 } else
1251 panic("Cannot find device node for cavium,octeon-3860-ciu.");
1252
1253 /* CIU_0 */
1254 for (i = 0; i < 16; i++)
1255 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0);
1256
1257 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, 0, chip_mbox, handle_percpu_irq);
1258 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq);
1259
1260 for (i = 0; i < 4; i++)
1261 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36);
1262 for (i = 0; i < 4; i++)
1263 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40);
1264
1265 octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI, 0, 45);
1266 octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46);
1267 for (i = 0; i < 4; i++)
1268 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);
1269
1270 octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56);
1271 octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI2, 0, 59);
1272
1273 /* CIU_1 */
1274 for (i = 0; i < 16; i++)
1275 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, 0, chip_wd, handle_level_irq);
1276
1277 octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB1, 1, 17);
1278
1279 /* Enable the CIU lines */
1280 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1281 clear_c0_status(STATUSF_IP4);
1282 }
1283
1284 /*
1285 * Watchdog interrupts are special. They are associated with a single
1286 * core, so we hardwire the affinity to that core.
1287 */
1288 static void octeon_irq_ciu2_wd_enable(struct irq_data *data)
1289 {
1290 u64 mask;
1291 u64 en_addr;
1292 int coreid = data->irq - OCTEON_IRQ_WDOG0;
1293 union octeon_ciu_chip_data cd;
1294
1295 cd.p = irq_data_get_irq_chip_data(data);
1296 mask = 1ull << (cd.s.bit);
1297
1298 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + (0x1000ull * cd.s.line);
1299 cvmx_write_csr(en_addr, mask);
1300
1301 }
1302
1303 static void octeon_irq_ciu2_enable(struct irq_data *data)
1304 {
1305 u64 mask;
1306 u64 en_addr;
1307 int cpu = next_cpu_for_irq(data);
1308 int coreid = octeon_coreid_for_cpu(cpu);
1309 union octeon_ciu_chip_data cd;
1310
1311 cd.p = irq_data_get_irq_chip_data(data);
1312 mask = 1ull << (cd.s.bit);
1313
1314 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + (0x1000ull * cd.s.line);
1315 cvmx_write_csr(en_addr, mask);
1316 }
1317
1318 static void octeon_irq_ciu2_enable_local(struct irq_data *data)
1319 {
1320 u64 mask;
1321 u64 en_addr;
1322 int coreid = cvmx_get_core_num();
1323 union octeon_ciu_chip_data cd;
1324
1325 cd.p = irq_data_get_irq_chip_data(data);
1326 mask = 1ull << (cd.s.bit);
1327
1328 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + (0x1000ull * cd.s.line);
1329 cvmx_write_csr(en_addr, mask);
1330
1331 }
1332
1333 static void octeon_irq_ciu2_disable_local(struct irq_data *data)
1334 {
1335 u64 mask;
1336 u64 en_addr;
1337 int coreid = cvmx_get_core_num();
1338 union octeon_ciu_chip_data cd;
1339
1340 cd.p = irq_data_get_irq_chip_data(data);
1341 mask = 1ull << (cd.s.bit);
1342
1343 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(coreid) + (0x1000ull * cd.s.line);
1344 cvmx_write_csr(en_addr, mask);
1345
1346 }
1347
1348 static void octeon_irq_ciu2_ack(struct irq_data *data)
1349 {
1350 u64 mask;
1351 u64 en_addr;
1352 int coreid = cvmx_get_core_num();
1353 union octeon_ciu_chip_data cd;
1354
1355 cd.p = irq_data_get_irq_chip_data(data);
1356 mask = 1ull << (cd.s.bit);
1357
1358 en_addr = CVMX_CIU2_RAW_PPX_IP2_WRKQ(coreid) + (0x1000ull * cd.s.line);
1359 cvmx_write_csr(en_addr, mask);
1360
1361 }
1362
1363 static void octeon_irq_ciu2_disable_all(struct irq_data *data)
1364 {
1365 int cpu;
1366 u64 mask;
1367 union octeon_ciu_chip_data cd;
1368
1369 cd.p = irq_data_get_irq_chip_data(data);
1370 mask = 1ull << (cd.s.bit);
1371
1372 for_each_online_cpu(cpu) {
1373 u64 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd.s.line);
1374 cvmx_write_csr(en_addr, mask);
1375 }
1376 }
1377
1378 static void octeon_irq_ciu2_mbox_enable_all(struct irq_data *data)
1379 {
1380 int cpu;
1381 u64 mask;
1382
1383 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1384
1385 for_each_online_cpu(cpu) {
1386 u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(octeon_coreid_for_cpu(cpu));
1387 cvmx_write_csr(en_addr, mask);
1388 }
1389 }
1390
1391 static void octeon_irq_ciu2_mbox_disable_all(struct irq_data *data)
1392 {
1393 int cpu;
1394 u64 mask;
1395
1396 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1397
1398 for_each_online_cpu(cpu) {
1399 u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(octeon_coreid_for_cpu(cpu));
1400 cvmx_write_csr(en_addr, mask);
1401 }
1402 }
1403
1404 static void octeon_irq_ciu2_mbox_enable_local(struct irq_data *data)
1405 {
1406 u64 mask;
1407 u64 en_addr;
1408 int coreid = cvmx_get_core_num();
1409
1410 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1411 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(coreid);
1412 cvmx_write_csr(en_addr, mask);
1413 }
1414
1415 static void octeon_irq_ciu2_mbox_disable_local(struct irq_data *data)
1416 {
1417 u64 mask;
1418 u64 en_addr;
1419 int coreid = cvmx_get_core_num();
1420
1421 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
1422 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(coreid);
1423 cvmx_write_csr(en_addr, mask);
1424 }
1425
1426 #ifdef CONFIG_SMP
1427 static int octeon_irq_ciu2_set_affinity(struct irq_data *data,
1428 const struct cpumask *dest, bool force)
1429 {
1430 int cpu;
1431 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
1432 u64 mask;
1433 union octeon_ciu_chip_data cd;
1434
1435 if (!enable_one)
1436 return 0;
1437
1438 cd.p = irq_data_get_irq_chip_data(data);
1439 mask = 1ull << cd.s.bit;
1440
1441 for_each_online_cpu(cpu) {
1442 u64 en_addr;
1443 if (cpumask_test_cpu(cpu, dest) && enable_one) {
1444 enable_one = false;
1445 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd.s.line);
1446 } else {
1447 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd.s.line);
1448 }
1449 cvmx_write_csr(en_addr, mask);
1450 }
1451
1452 return 0;
1453 }
1454 #endif
1455
1456 static void octeon_irq_ciu2_enable_gpio(struct irq_data *data)
1457 {
1458 octeon_irq_gpio_setup(data);
1459 octeon_irq_ciu2_enable(data);
1460 }
1461
1462 static void octeon_irq_ciu2_disable_gpio(struct irq_data *data)
1463 {
1464 union octeon_ciu_chip_data cd;
1465 cd.p = irq_data_get_irq_chip_data(data);
1466
1467 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), 0);
1468
1469 octeon_irq_ciu2_disable_all(data);
1470 }
1471
1472 static struct irq_chip octeon_irq_chip_ciu2 = {
1473 .name = "CIU2-E",
1474 .irq_enable = octeon_irq_ciu2_enable,
1475 .irq_disable = octeon_irq_ciu2_disable_all,
1476 .irq_ack = octeon_irq_ciu2_ack,
1477 .irq_mask = octeon_irq_ciu2_disable_local,
1478 .irq_unmask = octeon_irq_ciu2_enable,
1479 #ifdef CONFIG_SMP
1480 .irq_set_affinity = octeon_irq_ciu2_set_affinity,
1481 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1482 #endif
1483 };
1484
1485 static struct irq_chip octeon_irq_chip_ciu2_mbox = {
1486 .name = "CIU2-M",
1487 .irq_enable = octeon_irq_ciu2_mbox_enable_all,
1488 .irq_disable = octeon_irq_ciu2_mbox_disable_all,
1489 .irq_ack = octeon_irq_ciu2_mbox_disable_local,
1490 .irq_eoi = octeon_irq_ciu2_mbox_enable_local,
1491
1492 .irq_cpu_online = octeon_irq_ciu2_mbox_enable_local,
1493 .irq_cpu_offline = octeon_irq_ciu2_mbox_disable_local,
1494 .flags = IRQCHIP_ONOFFLINE_ENABLED,
1495 };
1496
1497 static struct irq_chip octeon_irq_chip_ciu2_wd = {
1498 .name = "CIU2-W",
1499 .irq_enable = octeon_irq_ciu2_wd_enable,
1500 .irq_disable = octeon_irq_ciu2_disable_all,
1501 .irq_mask = octeon_irq_ciu2_disable_local,
1502 .irq_unmask = octeon_irq_ciu2_enable_local,
1503 };
1504
1505 static struct irq_chip octeon_irq_chip_ciu2_gpio = {
1506 .name = "CIU-GPIO",
1507 .irq_enable = octeon_irq_ciu2_enable_gpio,
1508 .irq_disable = octeon_irq_ciu2_disable_gpio,
1509 .irq_ack = octeon_irq_ciu_gpio_ack,
1510 .irq_mask = octeon_irq_ciu2_disable_local,
1511 .irq_unmask = octeon_irq_ciu2_enable,
1512 .irq_set_type = octeon_irq_ciu_gpio_set_type,
1513 #ifdef CONFIG_SMP
1514 .irq_set_affinity = octeon_irq_ciu2_set_affinity,
1515 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
1516 #endif
1517 .flags = IRQCHIP_SET_TYPE_MASKED,
1518 };
1519
1520 static int octeon_irq_ciu2_xlat(struct irq_domain *d,
1521 struct device_node *node,
1522 const u32 *intspec,
1523 unsigned int intsize,
1524 unsigned long *out_hwirq,
1525 unsigned int *out_type)
1526 {
1527 unsigned int ciu, bit;
1528
1529 ciu = intspec[0];
1530 bit = intspec[1];
1531
1532 *out_hwirq = (ciu << 6) | bit;
1533 *out_type = 0;
1534
1535 return 0;
1536 }
1537
1538 static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit)
1539 {
1540 bool edge = false;
1541
1542 if (line == 3) /* MIO */
1543 switch (bit) {
1544 case 2: /* IPD_DRP */
1545 case 8 ... 11: /* Timers */
1546 case 48: /* PTP */
1547 edge = true;
1548 break;
1549 default:
1550 break;
1551 }
1552 else if (line == 6) /* PKT */
1553 switch (bit) {
1554 case 52 ... 53: /* ILK_DRP */
1555 case 8 ... 12: /* GMX_DRP */
1556 edge = true;
1557 break;
1558 default:
1559 break;
1560 }
1561 return edge;
1562 }
1563
1564 static int octeon_irq_ciu2_map(struct irq_domain *d,
1565 unsigned int virq, irq_hw_number_t hw)
1566 {
1567 unsigned int line = hw >> 6;
1568 unsigned int bit = hw & 63;
1569
1570 if (!octeon_irq_virq_in_range(virq))
1571 return -EINVAL;
1572
1573 /*
1574 * Don't map irq if it is reserved for GPIO.
1575 * (Line 7 are the GPIO lines.)
1576 */
1577 if (line == 7)
1578 return 0;
1579
1580 if (line > 7 || octeon_irq_ciu_to_irq[line][bit] != 0)
1581 return -EINVAL;
1582
1583 if (octeon_irq_ciu2_is_edge(line, bit))
1584 octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1585 &octeon_irq_chip_ciu2,
1586 handle_edge_irq);
1587 else
1588 octeon_irq_set_ciu_mapping(virq, line, bit, 0,
1589 &octeon_irq_chip_ciu2,
1590 handle_level_irq);
1591
1592 return 0;
1593 }
1594 static int octeon_irq_ciu2_gpio_map(struct irq_domain *d,
1595 unsigned int virq, irq_hw_number_t hw)
1596 {
1597 return octeon_irq_gpio_map_common(d, virq, hw, 7, &octeon_irq_chip_ciu2_gpio);
1598 }
1599
1600 static struct irq_domain_ops octeon_irq_domain_ciu2_ops = {
1601 .map = octeon_irq_ciu2_map,
1602 .xlate = octeon_irq_ciu2_xlat,
1603 };
1604
1605 static struct irq_domain_ops octeon_irq_domain_ciu2_gpio_ops = {
1606 .map = octeon_irq_ciu2_gpio_map,
1607 .xlate = octeon_irq_gpio_xlat,
1608 };
1609
1610 static void octeon_irq_ciu2(void)
1611 {
1612 int line;
1613 int bit;
1614 int irq;
1615 u64 src_reg, src, sum;
1616 const unsigned long core_id = cvmx_get_core_num();
1617
1618 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core_id)) & 0xfful;
1619
1620 if (unlikely(!sum))
1621 goto spurious;
1622
1623 line = fls64(sum) - 1;
1624 src_reg = CVMX_CIU2_SRC_PPX_IP2_WRKQ(core_id) + (0x1000 * line);
1625 src = cvmx_read_csr(src_reg);
1626
1627 if (unlikely(!src))
1628 goto spurious;
1629
1630 bit = fls64(src) - 1;
1631 irq = octeon_irq_ciu_to_irq[line][bit];
1632 if (unlikely(!irq))
1633 goto spurious;
1634
1635 do_IRQ(irq);
1636 goto out;
1637
1638 spurious:
1639 spurious_interrupt();
1640 out:
1641 /* CN68XX pass 1.x has an errata that accessing the ACK registers
1642 can stop interrupts from propagating */
1643 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1644 cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
1645 else
1646 cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core_id));
1647 return;
1648 }
1649
1650 static void octeon_irq_ciu2_mbox(void)
1651 {
1652 int line;
1653
1654 const unsigned long core_id = cvmx_get_core_num();
1655 u64 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP3(core_id)) >> 60;
1656
1657 if (unlikely(!sum))
1658 goto spurious;
1659
1660 line = fls64(sum) - 1;
1661
1662 do_IRQ(OCTEON_IRQ_MBOX0 + line);
1663 goto out;
1664
1665 spurious:
1666 spurious_interrupt();
1667 out:
1668 /* CN68XX pass 1.x has an errata that accessing the ACK registers
1669 can stop interrupts from propagating */
1670 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1671 cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
1672 else
1673 cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP3(core_id));
1674 return;
1675 }
1676
1677 static void __init octeon_irq_init_ciu2(void)
1678 {
1679 unsigned int i;
1680 struct device_node *gpio_node;
1681 struct device_node *ciu_node;
1682 struct irq_domain *ciu_domain = NULL;
1683
1684 octeon_irq_init_ciu2_percpu();
1685 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu2;
1686
1687 octeon_irq_ip2 = octeon_irq_ciu2;
1688 octeon_irq_ip3 = octeon_irq_ciu2_mbox;
1689 octeon_irq_ip4 = octeon_irq_ip4_mask;
1690
1691 /* Mips internal */
1692 octeon_irq_init_core();
1693
1694 gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio");
1695 if (gpio_node) {
1696 struct octeon_irq_gpio_domain_data *gpiod;
1697
1698 gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL);
1699 if (gpiod) {
1700 /* gpio domain host_data is the base hwirq number. */
1701 gpiod->base_hwirq = 7 << 6;
1702 irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_ciu2_gpio_ops, gpiod);
1703 of_node_put(gpio_node);
1704 } else
1705 pr_warn("Cannot allocate memory for GPIO irq_domain.\n");
1706 } else
1707 pr_warn("Cannot find device node for cavium,octeon-3860-gpio.\n");
1708
1709 ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-6880-ciu2");
1710 if (ciu_node) {
1711 ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu2_ops, NULL);
1712 irq_set_default_host(ciu_domain);
1713 of_node_put(ciu_node);
1714 } else
1715 panic("Cannot find device node for cavium,octeon-6880-ciu2.");
1716
1717 /* CUI2 */
1718 for (i = 0; i < 64; i++)
1719 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i);
1720
1721 for (i = 0; i < 32; i++)
1722 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i, 0,
1723 &octeon_irq_chip_ciu2_wd, handle_level_irq);
1724
1725 for (i = 0; i < 4; i++)
1726 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 3, i + 8);
1727
1728 octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 3, 44);
1729
1730 for (i = 0; i < 4; i++)
1731 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_INT0, 4, i);
1732
1733 for (i = 0; i < 4; i++)
1734 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 4, i + 8);
1735
1736 irq_set_chip_and_handler(OCTEON_IRQ_MBOX0, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
1737 irq_set_chip_and_handler(OCTEON_IRQ_MBOX1, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
1738 irq_set_chip_and_handler(OCTEON_IRQ_MBOX2, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
1739 irq_set_chip_and_handler(OCTEON_IRQ_MBOX3, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
1740
1741 /* Enable the CIU lines */
1742 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1743 clear_c0_status(STATUSF_IP4);
1744 }
1745
1746 void __init arch_init_irq(void)
1747 {
1748 #ifdef CONFIG_SMP
1749 /* Set the default affinity to the boot cpu. */
1750 cpumask_clear(irq_default_affinity);
1751 cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
1752 #endif
1753 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1754 octeon_irq_init_ciu2();
1755 else
1756 octeon_irq_init_ciu();
1757 }
1758
1759 asmlinkage void plat_irq_dispatch(void)
1760 {
1761 unsigned long cop0_cause;
1762 unsigned long cop0_status;
1763
1764 while (1) {
1765 cop0_cause = read_c0_cause();
1766 cop0_status = read_c0_status();
1767 cop0_cause &= cop0_status;
1768 cop0_cause &= ST0_IM;
1769
1770 if (unlikely(cop0_cause & STATUSF_IP2))
1771 octeon_irq_ip2();
1772 else if (unlikely(cop0_cause & STATUSF_IP3))
1773 octeon_irq_ip3();
1774 else if (unlikely(cop0_cause & STATUSF_IP4))
1775 octeon_irq_ip4();
1776 else if (likely(cop0_cause))
1777 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
1778 else
1779 break;
1780 }
1781 }
1782
1783 #ifdef CONFIG_HOTPLUG_CPU
1784
1785 void octeon_fixup_irqs(void)
1786 {
1787 irq_cpu_offline();
1788 }
1789
1790 #endif /* CONFIG_HOTPLUG_CPU */
Linux kernel - Deliverables
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