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Get rid of early_init. There's more need to make this form of
[deliverable/linux.git] / arch / mips / dec / setup.c
1 /*
2 * Setup the interrupt stuff.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Harald Koerfgen
9 * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki
10 */
11 #include <linux/sched.h>
12 #include <linux/interrupt.h>
13 #include <linux/param.h>
14 #include <linux/console.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/types.h>
19
20 #include <asm/bootinfo.h>
21 #include <asm/cpu.h>
22 #include <asm/cpu-features.h>
23 #include <asm/irq.h>
24 #include <asm/irq_cpu.h>
25 #include <asm/mipsregs.h>
26 #include <asm/reboot.h>
27 #include <asm/time.h>
28 #include <asm/traps.h>
29 #include <asm/wbflush.h>
30
31 #include <asm/dec/interrupts.h>
32 #include <asm/dec/ioasic.h>
33 #include <asm/dec/ioasic_addrs.h>
34 #include <asm/dec/ioasic_ints.h>
35 #include <asm/dec/kn01.h>
36 #include <asm/dec/kn02.h>
37 #include <asm/dec/kn02ba.h>
38 #include <asm/dec/kn02ca.h>
39 #include <asm/dec/kn03.h>
40 #include <asm/dec/kn230.h>
41
42
43 extern void dec_machine_restart(char *command);
44 extern void dec_machine_halt(void);
45 extern void dec_machine_power_off(void);
46 extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
47
48 extern asmlinkage void decstation_handle_int(void);
49
50 spinlock_t ioasic_ssr_lock;
51
52 volatile u32 *ioasic_base;
53 unsigned long dec_kn_slot_size;
54
55 /*
56 * IRQ routing and priority tables. Priorites are set as follows:
57 *
58 * KN01 KN230 KN02 KN02-BA KN02-CA KN03
59 *
60 * MEMORY CPU CPU CPU ASIC CPU CPU
61 * RTC CPU CPU CPU ASIC CPU CPU
62 * DMA - - - ASIC ASIC ASIC
63 * SERIAL0 CPU CPU CSR ASIC ASIC ASIC
64 * SERIAL1 - - - ASIC - ASIC
65 * SCSI CPU CPU CSR ASIC ASIC ASIC
66 * ETHERNET CPU * CSR ASIC ASIC ASIC
67 * other - - - ASIC - -
68 * TC2 - - CSR CPU ASIC ASIC
69 * TC1 - - CSR CPU ASIC ASIC
70 * TC0 - - CSR CPU ASIC ASIC
71 * other - CPU - CPU ASIC ASIC
72 * other - - - - CPU CPU
73 *
74 * * -- shared with SCSI
75 */
76
77 int dec_interrupt[DEC_NR_INTS] = {
78 [0 ... DEC_NR_INTS - 1] = -1
79 };
80 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
81 { { .i = ~0 }, { .p = dec_intr_unimplemented } },
82 };
83 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
84 { { .i = ~0 }, { .p = asic_intr_unimplemented } },
85 };
86 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
87
88 static struct irqaction ioirq = {
89 .handler = no_action,
90 .name = "cascade",
91 };
92 static struct irqaction fpuirq = {
93 .handler = no_action,
94 .name = "fpu",
95 };
96
97 static struct irqaction busirq = {
98 .flags = SA_INTERRUPT,
99 .name = "bus error",
100 };
101
102 static struct irqaction haltirq = {
103 .handler = dec_intr_halt,
104 .name = "halt",
105 };
106
107
108 /*
109 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
110 */
111 void __init dec_be_init(void)
112 {
113 switch (mips_machtype) {
114 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
115 busirq.flags |= SA_SHIRQ;
116 break;
117 case MACH_DS5000_200: /* DS5000/200 3max */
118 case MACH_DS5000_2X0: /* DS5000/240 3max+ */
119 case MACH_DS5900: /* DS5900 bigmax */
120 board_be_handler = dec_ecc_be_handler;
121 busirq.handler = dec_ecc_be_interrupt;
122 dec_ecc_be_init();
123 break;
124 }
125 }
126
127
128 extern void dec_time_init(void);
129 extern void dec_timer_setup(struct irqaction *);
130
131 void __init plat_setup(void)
132 {
133 board_be_init = dec_be_init;
134 board_time_init = dec_time_init;
135 board_timer_setup = dec_timer_setup;
136
137 wbflush_setup();
138
139 _machine_restart = dec_machine_restart;
140 _machine_halt = dec_machine_halt;
141 _machine_power_off = dec_machine_power_off;
142 }
143
144 /*
145 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
146 * or DS3100 (aka Pmax).
147 */
148 static int kn01_interrupt[DEC_NR_INTS] __initdata = {
149 [DEC_IRQ_CASCADE] = -1,
150 [DEC_IRQ_AB_RECV] = -1,
151 [DEC_IRQ_AB_XMIT] = -1,
152 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
153 [DEC_IRQ_ASC] = -1,
154 [DEC_IRQ_FLOPPY] = -1,
155 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
156 [DEC_IRQ_HALT] = -1,
157 [DEC_IRQ_ISDN] = -1,
158 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
159 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
160 [DEC_IRQ_PSU] = -1,
161 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
162 [DEC_IRQ_SCC0] = -1,
163 [DEC_IRQ_SCC1] = -1,
164 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
165 [DEC_IRQ_TC0] = -1,
166 [DEC_IRQ_TC1] = -1,
167 [DEC_IRQ_TC2] = -1,
168 [DEC_IRQ_TIMER] = -1,
169 [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
170 [DEC_IRQ_ASC_MERR] = -1,
171 [DEC_IRQ_ASC_ERR] = -1,
172 [DEC_IRQ_ASC_DMA] = -1,
173 [DEC_IRQ_FLOPPY_ERR] = -1,
174 [DEC_IRQ_ISDN_ERR] = -1,
175 [DEC_IRQ_ISDN_RXDMA] = -1,
176 [DEC_IRQ_ISDN_TXDMA] = -1,
177 [DEC_IRQ_LANCE_MERR] = -1,
178 [DEC_IRQ_SCC0A_RXERR] = -1,
179 [DEC_IRQ_SCC0A_RXDMA] = -1,
180 [DEC_IRQ_SCC0A_TXERR] = -1,
181 [DEC_IRQ_SCC0A_TXDMA] = -1,
182 [DEC_IRQ_AB_RXERR] = -1,
183 [DEC_IRQ_AB_RXDMA] = -1,
184 [DEC_IRQ_AB_TXERR] = -1,
185 [DEC_IRQ_AB_TXDMA] = -1,
186 [DEC_IRQ_SCC1A_RXERR] = -1,
187 [DEC_IRQ_SCC1A_RXDMA] = -1,
188 [DEC_IRQ_SCC1A_TXERR] = -1,
189 [DEC_IRQ_SCC1A_TXDMA] = -1,
190 };
191
192 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
193 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
194 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
195 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
196 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
197 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
198 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
199 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
200 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
201 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
202 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
203 { { .i = DEC_CPU_IRQ_ALL },
204 { .p = cpu_all_int } },
205 };
206
207 void __init dec_init_kn01(void)
208 {
209 /* IRQ routing. */
210 memcpy(&dec_interrupt, &kn01_interrupt,
211 sizeof(kn01_interrupt));
212
213 /* CPU IRQ priorities. */
214 memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
215 sizeof(kn01_cpu_mask_nr_tbl));
216
217 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
218
219 } /* dec_init_kn01 */
220
221
222 /*
223 * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
224 */
225 static int kn230_interrupt[DEC_NR_INTS] __initdata = {
226 [DEC_IRQ_CASCADE] = -1,
227 [DEC_IRQ_AB_RECV] = -1,
228 [DEC_IRQ_AB_XMIT] = -1,
229 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
230 [DEC_IRQ_ASC] = -1,
231 [DEC_IRQ_FLOPPY] = -1,
232 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
233 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
234 [DEC_IRQ_ISDN] = -1,
235 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
236 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
237 [DEC_IRQ_PSU] = -1,
238 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
239 [DEC_IRQ_SCC0] = -1,
240 [DEC_IRQ_SCC1] = -1,
241 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
242 [DEC_IRQ_TC0] = -1,
243 [DEC_IRQ_TC1] = -1,
244 [DEC_IRQ_TC2] = -1,
245 [DEC_IRQ_TIMER] = -1,
246 [DEC_IRQ_VIDEO] = -1,
247 [DEC_IRQ_ASC_MERR] = -1,
248 [DEC_IRQ_ASC_ERR] = -1,
249 [DEC_IRQ_ASC_DMA] = -1,
250 [DEC_IRQ_FLOPPY_ERR] = -1,
251 [DEC_IRQ_ISDN_ERR] = -1,
252 [DEC_IRQ_ISDN_RXDMA] = -1,
253 [DEC_IRQ_ISDN_TXDMA] = -1,
254 [DEC_IRQ_LANCE_MERR] = -1,
255 [DEC_IRQ_SCC0A_RXERR] = -1,
256 [DEC_IRQ_SCC0A_RXDMA] = -1,
257 [DEC_IRQ_SCC0A_TXERR] = -1,
258 [DEC_IRQ_SCC0A_TXDMA] = -1,
259 [DEC_IRQ_AB_RXERR] = -1,
260 [DEC_IRQ_AB_RXDMA] = -1,
261 [DEC_IRQ_AB_TXERR] = -1,
262 [DEC_IRQ_AB_TXDMA] = -1,
263 [DEC_IRQ_SCC1A_RXERR] = -1,
264 [DEC_IRQ_SCC1A_RXDMA] = -1,
265 [DEC_IRQ_SCC1A_TXERR] = -1,
266 [DEC_IRQ_SCC1A_TXDMA] = -1,
267 };
268
269 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
270 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
271 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
272 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
273 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
274 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
275 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
276 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
277 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
278 { { .i = DEC_CPU_IRQ_ALL },
279 { .p = cpu_all_int } },
280 };
281
282 void __init dec_init_kn230(void)
283 {
284 /* IRQ routing. */
285 memcpy(&dec_interrupt, &kn230_interrupt,
286 sizeof(kn230_interrupt));
287
288 /* CPU IRQ priorities. */
289 memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
290 sizeof(kn230_cpu_mask_nr_tbl));
291
292 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
293
294 } /* dec_init_kn230 */
295
296
297 /*
298 * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
299 */
300 static int kn02_interrupt[DEC_NR_INTS] __initdata = {
301 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
302 [DEC_IRQ_AB_RECV] = -1,
303 [DEC_IRQ_AB_XMIT] = -1,
304 [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
305 [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC),
306 [DEC_IRQ_FLOPPY] = -1,
307 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
308 [DEC_IRQ_HALT] = -1,
309 [DEC_IRQ_ISDN] = -1,
310 [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
311 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
312 [DEC_IRQ_PSU] = -1,
313 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
314 [DEC_IRQ_SCC0] = -1,
315 [DEC_IRQ_SCC1] = -1,
316 [DEC_IRQ_SII] = -1,
317 [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0),
318 [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1),
319 [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2),
320 [DEC_IRQ_TIMER] = -1,
321 [DEC_IRQ_VIDEO] = -1,
322 [DEC_IRQ_ASC_MERR] = -1,
323 [DEC_IRQ_ASC_ERR] = -1,
324 [DEC_IRQ_ASC_DMA] = -1,
325 [DEC_IRQ_FLOPPY_ERR] = -1,
326 [DEC_IRQ_ISDN_ERR] = -1,
327 [DEC_IRQ_ISDN_RXDMA] = -1,
328 [DEC_IRQ_ISDN_TXDMA] = -1,
329 [DEC_IRQ_LANCE_MERR] = -1,
330 [DEC_IRQ_SCC0A_RXERR] = -1,
331 [DEC_IRQ_SCC0A_RXDMA] = -1,
332 [DEC_IRQ_SCC0A_TXERR] = -1,
333 [DEC_IRQ_SCC0A_TXDMA] = -1,
334 [DEC_IRQ_AB_RXERR] = -1,
335 [DEC_IRQ_AB_RXDMA] = -1,
336 [DEC_IRQ_AB_TXERR] = -1,
337 [DEC_IRQ_AB_TXDMA] = -1,
338 [DEC_IRQ_SCC1A_RXERR] = -1,
339 [DEC_IRQ_SCC1A_RXDMA] = -1,
340 [DEC_IRQ_SCC1A_TXERR] = -1,
341 [DEC_IRQ_SCC1A_TXDMA] = -1,
342 };
343
344 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
345 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
346 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
347 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
348 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
349 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
350 { .p = kn02_io_int } },
351 { { .i = DEC_CPU_IRQ_ALL },
352 { .p = cpu_all_int } },
353 };
354
355 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
356 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
357 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
358 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
359 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
360 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
361 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
362 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
363 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
364 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
365 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
366 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
367 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
368 { { .i = KN02_IRQ_ALL },
369 { .p = kn02_all_int } },
370 };
371
372 void __init dec_init_kn02(void)
373 {
374 /* IRQ routing. */
375 memcpy(&dec_interrupt, &kn02_interrupt,
376 sizeof(kn02_interrupt));
377
378 /* CPU IRQ priorities. */
379 memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
380 sizeof(kn02_cpu_mask_nr_tbl));
381
382 /* KN02 CSR IRQ priorities. */
383 memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
384 sizeof(kn02_asic_mask_nr_tbl));
385
386 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
387 init_kn02_irqs(KN02_IRQ_BASE);
388
389 } /* dec_init_kn02 */
390
391
392 /*
393 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
394 * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka
395 * DS5000/150, aka 4min.
396 */
397 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
398 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
399 [DEC_IRQ_AB_RECV] = -1,
400 [DEC_IRQ_AB_XMIT] = -1,
401 [DEC_IRQ_DZ11] = -1,
402 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC),
403 [DEC_IRQ_FLOPPY] = -1,
404 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
405 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
406 [DEC_IRQ_ISDN] = -1,
407 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
408 [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS),
409 [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU),
410 [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC),
411 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
412 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
413 [DEC_IRQ_SII] = -1,
414 [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
415 [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
416 [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
417 [DEC_IRQ_TIMER] = -1,
418 [DEC_IRQ_VIDEO] = -1,
419 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
420 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
421 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
422 [DEC_IRQ_FLOPPY_ERR] = -1,
423 [DEC_IRQ_ISDN_ERR] = -1,
424 [DEC_IRQ_ISDN_RXDMA] = -1,
425 [DEC_IRQ_ISDN_TXDMA] = -1,
426 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
427 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
428 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
429 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
430 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
431 [DEC_IRQ_AB_RXERR] = -1,
432 [DEC_IRQ_AB_RXDMA] = -1,
433 [DEC_IRQ_AB_TXERR] = -1,
434 [DEC_IRQ_AB_TXDMA] = -1,
435 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
436 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
437 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
438 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
439 };
440
441 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
442 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
443 { .p = kn02xa_io_int } },
444 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
445 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
446 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
447 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
448 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
449 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
450 { { .i = DEC_CPU_IRQ_ALL },
451 { .p = cpu_all_int } },
452 };
453
454 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
455 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
456 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
457 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
458 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
459 { { .i = IO_IRQ_DMA },
460 { .p = asic_dma_int } },
461 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
462 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
463 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
464 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
465 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
466 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
467 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
468 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
469 { { .i = IO_IRQ_ALL },
470 { .p = asic_all_int } },
471 };
472
473 void __init dec_init_kn02ba(void)
474 {
475 /* IRQ routing. */
476 memcpy(&dec_interrupt, &kn02ba_interrupt,
477 sizeof(kn02ba_interrupt));
478
479 /* CPU IRQ priorities. */
480 memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
481 sizeof(kn02ba_cpu_mask_nr_tbl));
482
483 /* I/O ASIC IRQ priorities. */
484 memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
485 sizeof(kn02ba_asic_mask_nr_tbl));
486
487 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
488 init_ioasic_irqs(IO_IRQ_BASE);
489
490 } /* dec_init_kn02ba */
491
492
493 /*
494 * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
495 * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka
496 * DS5000/50, aka 4MAXine.
497 */
498 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
499 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
500 [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
501 [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
502 [DEC_IRQ_DZ11] = -1,
503 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC),
504 [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
505 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
506 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
507 [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
508 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
509 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
510 [DEC_IRQ_PSU] = -1,
511 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
512 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
513 [DEC_IRQ_SCC1] = -1,
514 [DEC_IRQ_SII] = -1,
515 [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0),
516 [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1),
517 [DEC_IRQ_TC2] = -1,
518 [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
519 [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
520 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
521 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
522 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
523 [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
524 [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR),
525 [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
526 [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
527 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
528 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
529 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
530 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
531 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
532 [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR),
533 [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA),
534 [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR),
535 [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA),
536 [DEC_IRQ_SCC1A_RXERR] = -1,
537 [DEC_IRQ_SCC1A_RXDMA] = -1,
538 [DEC_IRQ_SCC1A_TXERR] = -1,
539 [DEC_IRQ_SCC1A_TXDMA] = -1,
540 };
541
542 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
543 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
544 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
545 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
546 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
547 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
548 { .p = kn02xa_io_int } },
549 { { .i = DEC_CPU_IRQ_ALL },
550 { .p = cpu_all_int } },
551 };
552
553 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
554 { { .i = IO_IRQ_DMA },
555 { .p = asic_dma_int } },
556 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
557 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
558 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
559 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
560 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
561 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
562 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
563 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
564 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
565 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
566 { { .i = IO_IRQ_ALL },
567 { .p = asic_all_int } },
568 };
569
570 void __init dec_init_kn02ca(void)
571 {
572 /* IRQ routing. */
573 memcpy(&dec_interrupt, &kn02ca_interrupt,
574 sizeof(kn02ca_interrupt));
575
576 /* CPU IRQ priorities. */
577 memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
578 sizeof(kn02ca_cpu_mask_nr_tbl));
579
580 /* I/O ASIC IRQ priorities. */
581 memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
582 sizeof(kn02ca_asic_mask_nr_tbl));
583
584 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
585 init_ioasic_irqs(IO_IRQ_BASE);
586
587 } /* dec_init_kn02ca */
588
589
590 /*
591 * Machine-specific initialisation for KN03, aka DS5000/240,
592 * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka
593 * DS5000/260, aka 4max+ and DS5900/260.
594 */
595 static int kn03_interrupt[DEC_NR_INTS] __initdata = {
596 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
597 [DEC_IRQ_AB_RECV] = -1,
598 [DEC_IRQ_AB_XMIT] = -1,
599 [DEC_IRQ_DZ11] = -1,
600 [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC),
601 [DEC_IRQ_FLOPPY] = -1,
602 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
603 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
604 [DEC_IRQ_ISDN] = -1,
605 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE),
606 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
607 [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU),
608 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
609 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0),
610 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1),
611 [DEC_IRQ_SII] = -1,
612 [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0),
613 [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1),
614 [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2),
615 [DEC_IRQ_TIMER] = -1,
616 [DEC_IRQ_VIDEO] = -1,
617 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
618 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
619 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
620 [DEC_IRQ_FLOPPY_ERR] = -1,
621 [DEC_IRQ_ISDN_ERR] = -1,
622 [DEC_IRQ_ISDN_RXDMA] = -1,
623 [DEC_IRQ_ISDN_TXDMA] = -1,
624 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
625 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
626 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
627 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
628 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
629 [DEC_IRQ_AB_RXERR] = -1,
630 [DEC_IRQ_AB_RXDMA] = -1,
631 [DEC_IRQ_AB_TXERR] = -1,
632 [DEC_IRQ_AB_TXDMA] = -1,
633 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
634 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
635 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
636 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
637 };
638
639 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
640 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
641 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
642 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
643 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
644 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
645 { .p = kn03_io_int } },
646 { { .i = DEC_CPU_IRQ_ALL },
647 { .p = cpu_all_int } },
648 };
649
650 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
651 { { .i = IO_IRQ_DMA },
652 { .p = asic_dma_int } },
653 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
654 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
655 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
656 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
657 { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
658 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
659 { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
660 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
661 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
662 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
663 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
664 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
665 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
666 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
667 { { .i = IO_IRQ_ALL },
668 { .p = asic_all_int } },
669 };
670
671 void __init dec_init_kn03(void)
672 {
673 /* IRQ routing. */
674 memcpy(&dec_interrupt, &kn03_interrupt,
675 sizeof(kn03_interrupt));
676
677 /* CPU IRQ priorities. */
678 memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
679 sizeof(kn03_cpu_mask_nr_tbl));
680
681 /* I/O ASIC IRQ priorities. */
682 memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
683 sizeof(kn03_asic_mask_nr_tbl));
684
685 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
686 init_ioasic_irqs(IO_IRQ_BASE);
687
688 } /* dec_init_kn03 */
689
690
691 void __init arch_init_irq(void)
692 {
693 switch (mips_machtype) {
694 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
695 dec_init_kn01();
696 break;
697 case MACH_DS5100: /* DS5100 MIPSmate */
698 dec_init_kn230();
699 break;
700 case MACH_DS5000_200: /* DS5000/200 3max */
701 dec_init_kn02();
702 break;
703 case MACH_DS5000_1XX: /* DS5000/1xx 3min */
704 dec_init_kn02ba();
705 break;
706 case MACH_DS5000_2X0: /* DS5000/240 3max+ */
707 case MACH_DS5900: /* DS5900 bigmax */
708 dec_init_kn03();
709 break;
710 case MACH_DS5000_XX: /* Personal DS5000/xx */
711 dec_init_kn02ca();
712 break;
713 case MACH_DS5800: /* DS5800 Isis */
714 panic("Don't know how to set this up!");
715 break;
716 case MACH_DS5400: /* DS5400 MIPSfair */
717 panic("Don't know how to set this up!");
718 break;
719 case MACH_DS5500: /* DS5500 MIPSfair-2 */
720 panic("Don't know how to set this up!");
721 break;
722 }
723 set_except_vector(0, decstation_handle_int);
724
725 /* Free the FPU interrupt if the exception is present. */
726 if (!cpu_has_nofpuex) {
727 cpu_fpu_mask = 0;
728 dec_interrupt[DEC_IRQ_FPU] = -1;
729 }
730
731 /* Register board interrupts: FPU and cascade. */
732 if (dec_interrupt[DEC_IRQ_FPU] >= 0)
733 setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq);
734 if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
735 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
736
737 /* Register the bus error interrupt. */
738 if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
739 setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
740
741 /* Register the HALT interrupt. */
742 if (dec_interrupt[DEC_IRQ_HALT] >= 0)
743 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
744 }
745
746 EXPORT_SYMBOL(ioasic_base);
747 EXPORT_SYMBOL(dec_kn_slot_size);
748 EXPORT_SYMBOL(dec_interrupt);
Linux kernel - Deliverables
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