2 * arch/mips/emma2rh/markeins/irq.c
3 * This file defines the irq handler for EMMA2RH.
5 * Copyright (C) NEC Electronics Corporation 2004-2006
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
9 * Copyright 2001 MontaVista Software Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/types.h>
29 #include <linux/ptrace.h>
30 #include <linux/delay.h>
32 #include <asm/irq_cpu.h>
33 #include <asm/system.h>
34 #include <asm/mipsregs.h>
35 #include <asm/addrspace.h>
36 #include <asm/bootinfo.h>
38 #include <asm/emma/emma2rh.h>
40 static void emma2rh_irq_enable(unsigned int irq
)
46 irq
-= EMMA2RH_IRQ_BASE
;
48 reg_index
= EMMA2RH_BHIF_INT_EN_0
+
49 (EMMA2RH_BHIF_INT_EN_1
- EMMA2RH_BHIF_INT_EN_0
) * (irq
/ 32);
50 reg_value
= emma2rh_in32(reg_index
);
51 reg_bitmask
= 0x1 << (irq
% 32);
52 emma2rh_out32(reg_index
, reg_value
| reg_bitmask
);
55 static void emma2rh_irq_disable(unsigned int irq
)
61 irq
-= EMMA2RH_IRQ_BASE
;
63 reg_index
= EMMA2RH_BHIF_INT_EN_0
+
64 (EMMA2RH_BHIF_INT_EN_1
- EMMA2RH_BHIF_INT_EN_0
) * (irq
/ 32);
65 reg_value
= emma2rh_in32(reg_index
);
66 reg_bitmask
= 0x1 << (irq
% 32);
67 emma2rh_out32(reg_index
, reg_value
& ~reg_bitmask
);
70 struct irq_chip emma2rh_irq_controller
= {
71 .name
= "emma2rh_irq",
72 .ack
= emma2rh_irq_disable
,
73 .mask
= emma2rh_irq_disable
,
74 .mask_ack
= emma2rh_irq_disable
,
75 .unmask
= emma2rh_irq_enable
,
78 void emma2rh_irq_init(void)
82 for (i
= 0; i
< NUM_EMMA2RH_IRQ
; i
++)
83 set_irq_chip_and_handler(EMMA2RH_IRQ_BASE
+ i
,
84 &emma2rh_irq_controller
,
88 static void emma2rh_sw_irq_enable(unsigned int irq
)
92 irq
-= EMMA2RH_SW_IRQ_BASE
;
94 reg
= emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN
);
96 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN
, reg
);
99 static void emma2rh_sw_irq_disable(unsigned int irq
)
103 irq
-= EMMA2RH_SW_IRQ_BASE
;
105 reg
= emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN
);
107 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN
, reg
);
110 struct irq_chip emma2rh_sw_irq_controller
= {
111 .name
= "emma2rh_sw_irq",
112 .ack
= emma2rh_sw_irq_disable
,
113 .mask
= emma2rh_sw_irq_disable
,
114 .mask_ack
= emma2rh_sw_irq_disable
,
115 .unmask
= emma2rh_sw_irq_enable
,
118 void emma2rh_sw_irq_init(void)
122 for (i
= 0; i
< NUM_EMMA2RH_IRQ_SW
; i
++)
123 set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE
+ i
,
124 &emma2rh_sw_irq_controller
,
128 static void emma2rh_gpio_irq_enable(unsigned int irq
)
132 irq
-= EMMA2RH_GPIO_IRQ_BASE
;
134 reg
= emma2rh_in32(EMMA2RH_GPIO_INT_MASK
);
136 emma2rh_out32(EMMA2RH_GPIO_INT_MASK
, reg
);
139 static void emma2rh_gpio_irq_disable(unsigned int irq
)
143 irq
-= EMMA2RH_GPIO_IRQ_BASE
;
145 reg
= emma2rh_in32(EMMA2RH_GPIO_INT_MASK
);
147 emma2rh_out32(EMMA2RH_GPIO_INT_MASK
, reg
);
150 static void emma2rh_gpio_irq_ack(unsigned int irq
)
154 irq
-= EMMA2RH_GPIO_IRQ_BASE
;
155 emma2rh_out32(EMMA2RH_GPIO_INT_ST
, ~(1 << irq
));
157 reg
= emma2rh_in32(EMMA2RH_GPIO_INT_MASK
);
159 emma2rh_out32(EMMA2RH_GPIO_INT_MASK
, reg
);
162 static void emma2rh_gpio_irq_end(unsigned int irq
)
166 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
))) {
168 irq
-= EMMA2RH_GPIO_IRQ_BASE
;
170 reg
= emma2rh_in32(EMMA2RH_GPIO_INT_MASK
);
172 emma2rh_out32(EMMA2RH_GPIO_INT_MASK
, reg
);
176 struct irq_chip emma2rh_gpio_irq_controller
= {
177 .name
= "emma2rh_gpio_irq",
178 .ack
= emma2rh_gpio_irq_ack
,
179 .mask
= emma2rh_gpio_irq_disable
,
180 .mask_ack
= emma2rh_gpio_irq_ack
,
181 .unmask
= emma2rh_gpio_irq_enable
,
182 .end
= emma2rh_gpio_irq_end
,
185 void emma2rh_gpio_irq_init(void)
189 for (i
= 0; i
< NUM_EMMA2RH_IRQ_GPIO
; i
++)
190 set_irq_chip(EMMA2RH_GPIO_IRQ_BASE
+ i
,
191 &emma2rh_gpio_irq_controller
);
194 static struct irqaction irq_cascade
= {
195 .handler
= no_action
,
197 .mask
= CPU_MASK_NONE
,
204 * the first level int-handler will jump here if it is a emma2rh irq
206 void emma2rh_irq_dispatch(void)
212 intStatus
= emma2rh_in32(EMMA2RH_BHIF_INT_ST_0
) &
213 emma2rh_in32(EMMA2RH_BHIF_INT_EN_0
);
215 #ifdef EMMA2RH_SW_CASCADE
217 (1 << ((EMMA2RH_SW_CASCADE
- EMMA2RH_IRQ_INT0
) & (32 - 1)))) {
219 swIntStatus
= emma2rh_in32(EMMA2RH_BHIF_SW_INT
)
220 & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN
);
221 for (i
= 0, bitmask
= 1; i
< 32; i
++, bitmask
<<= 1) {
222 if (swIntStatus
& bitmask
) {
223 do_IRQ(EMMA2RH_SW_IRQ_BASE
+ i
);
230 for (i
= 0, bitmask
= 1; i
< 32; i
++, bitmask
<<= 1) {
231 if (intStatus
& bitmask
) {
232 do_IRQ(EMMA2RH_IRQ_BASE
+ i
);
237 intStatus
= emma2rh_in32(EMMA2RH_BHIF_INT_ST_1
) &
238 emma2rh_in32(EMMA2RH_BHIF_INT_EN_1
);
240 #ifdef EMMA2RH_GPIO_CASCADE
242 (1 << ((EMMA2RH_GPIO_CASCADE
- EMMA2RH_IRQ_INT0
) & (32 - 1)))) {
244 gpioIntStatus
= emma2rh_in32(EMMA2RH_GPIO_INT_ST
)
245 & emma2rh_in32(EMMA2RH_GPIO_INT_MASK
);
246 for (i
= 0, bitmask
= 1; i
< 32; i
++, bitmask
<<= 1) {
247 if (gpioIntStatus
& bitmask
) {
248 do_IRQ(EMMA2RH_GPIO_IRQ_BASE
+ i
);
255 for (i
= 32, bitmask
= 1; i
< 64; i
++, bitmask
<<= 1) {
256 if (intStatus
& bitmask
) {
257 do_IRQ(EMMA2RH_IRQ_BASE
+ i
);
262 intStatus
= emma2rh_in32(EMMA2RH_BHIF_INT_ST_2
) &
263 emma2rh_in32(EMMA2RH_BHIF_INT_EN_2
);
265 for (i
= 64, bitmask
= 1; i
< 96; i
++, bitmask
<<= 1) {
266 if (intStatus
& bitmask
) {
267 do_IRQ(EMMA2RH_IRQ_BASE
+ i
);
273 void __init
arch_init_irq(void)
277 /* by default, interrupts are disabled. */
278 emma2rh_out32(EMMA2RH_BHIF_INT_EN_0
, 0);
279 emma2rh_out32(EMMA2RH_BHIF_INT_EN_1
, 0);
280 emma2rh_out32(EMMA2RH_BHIF_INT_EN_2
, 0);
281 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0
, 0);
282 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1
, 0);
283 emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2
, 0);
284 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN
, 0);
286 clear_c0_status(0xff00);
287 set_c0_status(0x0400);
289 #define GPIO_PCI (0xf<<15)
290 /* setup GPIO interrupt for PCI interface */
291 /* direction input */
292 reg
= emma2rh_in32(EMMA2RH_GPIO_DIR
);
293 emma2rh_out32(EMMA2RH_GPIO_DIR
, reg
& ~GPIO_PCI
);
294 /* disable interrupt */
295 reg
= emma2rh_in32(EMMA2RH_GPIO_INT_MASK
);
296 emma2rh_out32(EMMA2RH_GPIO_INT_MASK
, reg
& ~GPIO_PCI
);
298 reg
= emma2rh_in32(EMMA2RH_GPIO_INT_MODE
);
299 emma2rh_out32(EMMA2RH_GPIO_INT_MODE
, reg
| GPIO_PCI
);
300 reg
= emma2rh_in32(EMMA2RH_GPIO_INT_CND_A
);
301 emma2rh_out32(EMMA2RH_GPIO_INT_CND_A
, reg
& (~GPIO_PCI
));
302 /* interrupt clear */
303 emma2rh_out32(EMMA2RH_GPIO_INT_ST
, ~GPIO_PCI
);
305 /* init all controllers */
307 emma2rh_sw_irq_init();
308 emma2rh_gpio_irq_init();
311 /* setup cascade interrupts */
312 setup_irq(EMMA2RH_IRQ_BASE
+ EMMA2RH_SW_CASCADE
, &irq_cascade
);
313 setup_irq(EMMA2RH_IRQ_BASE
+ EMMA2RH_GPIO_CASCADE
, &irq_cascade
);
314 setup_irq(CPU_IRQ_BASE
+ CPU_EMMA2RH_CASCADE
, &irq_cascade
);
317 asmlinkage
void plat_irq_dispatch(void)
319 unsigned int pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
321 if (pending
& STATUSF_IP7
)
322 do_IRQ(CPU_IRQ_BASE
+ 7);
323 else if (pending
& STATUSF_IP2
)
324 emma2rh_irq_dispatch();
325 else if (pending
& STATUSF_IP1
)
326 do_IRQ(CPU_IRQ_BASE
+ 1);
327 else if (pending
& STATUSF_IP0
)
328 do_IRQ(CPU_IRQ_BASE
+ 0);
330 spurious_interrupt();