2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
8 #ifndef __ASM_BARRIER_H
9 #define __ASM_BARRIER_H
11 #include <asm/addrspace.h>
13 #define read_barrier_depends() do { } while(0)
14 #define smp_read_barrier_depends() do { } while(0)
16 #ifdef CONFIG_CPU_HAS_SYNC
18 __asm__ __volatile__( \
20 ".set noreorder\n\t" \
28 #define __sync() do { } while(0)
31 #define __fast_iob() \
32 __asm__ __volatile__( \
34 ".set noreorder\n\t" \
39 : "m" (*(int *)CKSEG1) \
41 #ifdef CONFIG_CPU_CAVIUM_OCTEON
42 # define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
43 # define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
45 # define fast_wmb() __syncw()
46 # define fast_rmb() barrier()
47 # define fast_mb() __sync()
48 # define fast_iob() do { } while (0)
49 #else /* ! CONFIG_CPU_CAVIUM_OCTEON */
50 # define fast_wmb() __sync()
51 # define fast_rmb() __sync()
52 # define fast_mb() __sync()
53 # ifdef CONFIG_SGI_IP28
55 __asm__ __volatile__( \
57 ".set noreorder\n\t" \
63 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
72 #endif /* CONFIG_CPU_CAVIUM_OCTEON */
74 #ifdef CONFIG_CPU_HAS_WB
76 #include <asm/wbflush.h>
78 #define wmb() fast_wmb()
79 #define rmb() fast_rmb()
80 #define mb() wbflush()
81 #define iob() wbflush()
83 #else /* !CONFIG_CPU_HAS_WB */
85 #define wmb() fast_wmb()
86 #define rmb() fast_rmb()
87 #define mb() fast_mb()
88 #define iob() fast_iob()
90 #endif /* !CONFIG_CPU_HAS_WB */
92 #if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP)
93 # ifdef CONFIG_CPU_CAVIUM_OCTEON
94 # define smp_mb() __sync()
95 # define smp_rmb() barrier()
96 # define smp_wmb() __syncw()
98 # define smp_mb() __asm__ __volatile__("sync" : : :"memory")
99 # define smp_rmb() __asm__ __volatile__("sync" : : :"memory")
100 # define smp_wmb() __asm__ __volatile__("sync" : : :"memory")
103 #define smp_mb() barrier()
104 #define smp_rmb() barrier()
105 #define smp_wmb() barrier()
108 #if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
109 #define __WEAK_LLSC_MB " sync \n"
111 #define __WEAK_LLSC_MB " \n"
114 #define set_mb(var, value) \
115 do { var = value; smp_mb(); } while (0)
117 #define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
119 #ifdef CONFIG_CPU_CAVIUM_OCTEON
120 #define smp_mb__before_llsc() smp_wmb()
121 /* Cause previous writes to become visible on all CPUs as soon as possible */
122 #define nudge_writes() __asm__ __volatile__(".set push\n\t" \
123 ".set arch=octeon\n\t" \
125 ".set pop" : : : "memory")
127 #define smp_mb__before_llsc() smp_llsc_mb()
128 #define nudge_writes() mb()
131 #define smp_store_release(p, v) \
133 compiletime_assert_atomic_type(*p); \
135 ACCESS_ONCE(*p) = (v); \
138 #define smp_load_acquire(p) \
140 typeof(*p) ___p1 = ACCESS_ONCE(*p); \
141 compiletime_assert_atomic_type(*p); \
146 #define smp_mb__before_atomic() smp_mb__before_llsc()
147 #define smp_mb__after_atomic() smp_llsc_mb()
149 #endif /* __ASM_BARRIER_H */
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