arch/mips/include/asm/fpu.h

   1 /*
   2  * Copyright (C) 2002 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10 #ifndef _ASM_FPU_H
  11 #define _ASM_FPU_H
  12
  13 #include <linux/sched.h>
  14 #include <linux/thread_info.h>
  15 #include <linux/bitops.h>
  16
  17 #include <asm/mipsregs.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpu-features.h>
  20 #include <asm/fpu_emulator.h>
  21 #include <asm/hazards.h>
  22 #include <asm/processor.h>
  23 #include <asm/current.h>
  24 #include <asm/msa.h>
  25
  26 #ifdef CONFIG_MIPS_MT_FPAFF
  27 #include <asm/mips_mt.h>
  28 #endif
  29
  30 struct sigcontext;
  31 struct sigcontext32;
  32
  33 extern void _init_fpu(void);
  34 extern void _save_fp(struct task_struct *);
  35 extern void _restore_fp(struct task_struct *);
  36
  37 /*
  38  * This enum specifies a mode in which we want the FPU to operate, for cores
  39  * which implement the Status.FR bit. Note that the bottom bit of the value
  40  * purposefully matches the desired value of the Status.FR bit.
  41  */
  42 enum fpu_mode {
  43         FPU_32BIT = 0,          /* FR = 0 */
  44         FPU_64BIT,              /* FR = 1, FRE = 0 */
  45         FPU_AS_IS,
  46         FPU_HYBRID,             /* FR = 1, FRE = 1 */
  47
  48 #define FPU_FR_MASK             0x1
  49 };
  50
  51 static inline int __enable_fpu(enum fpu_mode mode)
  52 {
  53         int fr;
  54
  55         switch (mode) {
  56         case FPU_AS_IS:
  57                 /* just enable the FPU in its current mode */
  58                 set_c0_status(ST0_CU1);
  59                 enable_fpu_hazard();
  60                 return 0;
  61
  62         case FPU_HYBRID:
  63                 if (!cpu_has_fre)
  64                         return SIGFPE;
  65
  66                 /* set FRE */
  67                 write_c0_config5(read_c0_config5() | MIPS_CONF5_FRE);
  68                 goto fr_common;
  69
  70         case FPU_64BIT:
  71 #if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT))
  72                 /* we only have a 32-bit FPU */
  73                 return SIGFPE;
  74 #endif
  75                 /* fall through */
  76         case FPU_32BIT:
  77                 if (cpu_has_fre) {
  78                         /* clear FRE */
  79                         write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE);
  80                 }
  81 fr_common:
  82                 /* set CU1 & change FR appropriately */
  83                 fr = (int)mode & FPU_FR_MASK;
  84                 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
  85                 enable_fpu_hazard();
  86
  87                 /* check FR has the desired value */
  88                 return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;
  89
  90         default:
  91                 BUG();
  92         }
  93
  94         return SIGFPE;
  95 }
  96
  97 #define __disable_fpu()                                                 \
  98 do {                                                                    \
  99         clear_c0_status(ST0_CU1);                                       \
 100         disable_fpu_hazard();                                           \
 101 } while (0)
 102
 103 #define clear_fpu_owner()       clear_thread_flag(TIF_USEDFPU)
 104
 105 static inline int __is_fpu_owner(void)
 106 {
 107         return test_thread_flag(TIF_USEDFPU);
 108 }
 109
 110 static inline int is_fpu_owner(void)
 111 {
 112         return cpu_has_fpu && __is_fpu_owner();
 113 }
 114
 115 static inline int __own_fpu(void)
 116 {
 117         enum fpu_mode mode;
 118         int ret;
 119
 120         if (test_thread_flag(TIF_HYBRID_FPREGS))
 121                 mode = FPU_HYBRID;
 122         else
 123                 mode = !test_thread_flag(TIF_32BIT_FPREGS);
 124
 125         ret = __enable_fpu(mode);
 126         if (ret)
 127                 return ret;
 128
 129         KSTK_STATUS(current) |= ST0_CU1;
 130         if (mode == FPU_64BIT || mode == FPU_HYBRID)
 131                 KSTK_STATUS(current) |= ST0_FR;
 132         else /* mode == FPU_32BIT */
 133                 KSTK_STATUS(current) &= ~ST0_FR;
 134
 135         set_thread_flag(TIF_USEDFPU);
 136         return 0;
 137 }
 138
 139 static inline int own_fpu_inatomic(int restore)
 140 {
 141         int ret = 0;
 142
 143         if (cpu_has_fpu && !__is_fpu_owner()) {
 144                 ret = __own_fpu();
 145                 if (restore && !ret)
 146                         _restore_fp(current);
 147         }
 148         return ret;
 149 }
 150
 151 static inline int own_fpu(int restore)
 152 {
 153         int ret;
 154
 155         preempt_disable();
 156         ret = own_fpu_inatomic(restore);
 157         preempt_enable();
 158         return ret;
 159 }
 160
 161 static inline void lose_fpu(int save)
 162 {
 163         preempt_disable();
 164         if (is_msa_enabled()) {
 165                 if (save) {
 166                         save_msa(current);
 167                         current->thread.fpu.fcr31 =
 168                                         read_32bit_cp1_register(CP1_STATUS);
 169                 }
 170                 disable_msa();
 171                 clear_thread_flag(TIF_USEDMSA);
 172         } else if (is_fpu_owner()) {
 173                 if (save)
 174                         _save_fp(current);
 175                 __disable_fpu();
 176         }
 177         KSTK_STATUS(current) &= ~ST0_CU1;
 178         clear_thread_flag(TIF_USEDFPU);
 179         preempt_enable();
 180 }
 181
 182 static inline int init_fpu(void)
 183 {
 184         int ret = 0;
 185
 186         if (cpu_has_fpu) {
 187                 unsigned int config5;
 188
 189                 ret = __own_fpu();
 190                 if (ret)
 191                         return ret;
 192
 193                 if (!cpu_has_fre) {
 194                         _init_fpu();
 195
 196                         return 0;
 197                 }
 198
 199                 config5 = read_c0_config5();
 200
 201                 /*
 202                  * Ensure FRE is clear whilst running _init_fpu, since
 203                  * single precision FP instructions are used. If FRE
 204                  * was set then we'll just end up initialising all 32
 205                  * 64b registers.
 206                  */
 207                 write_c0_config5(config5 & ~MIPS_CONF5_FRE);
 208                 enable_fpu_hazard();
 209
 210                 _init_fpu();
 211
 212                 /* Restore FRE */
 213                 write_c0_config5(config5);
 214                 enable_fpu_hazard();
 215         } else
 216                 fpu_emulator_init_fpu();
 217
 218         return ret;
 219 }
 220
 221 static inline void save_fp(struct task_struct *tsk)
 222 {
 223         if (cpu_has_fpu)
 224                 _save_fp(tsk);
 225 }
 226
 227 static inline void restore_fp(struct task_struct *tsk)
 228 {
 229         if (cpu_has_fpu)
 230                 _restore_fp(tsk);
 231 }
 232
 233 static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
 234 {
 235         if (tsk == current) {
 236                 preempt_disable();
 237                 if (is_fpu_owner())
 238                         _save_fp(current);
 239                 preempt_enable();
 240         }
 241
 242         return tsk->thread.fpu.fpr;
 243 }
 244
 245 #endif /* _ASM_FPU_H */