arch/mips/include/asm/fpu.h

   1 /*
   2  * Copyright (C) 2002 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10 #ifndef _ASM_FPU_H
  11 #define _ASM_FPU_H
  12
  13 #include <linux/sched.h>
  14 #include <linux/thread_info.h>
  15 #include <linux/bitops.h>
  16
  17 #include <asm/mipsregs.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpu-features.h>
  20 #include <asm/fpu_emulator.h>
  21 #include <asm/hazards.h>
  22 #include <asm/processor.h>
  23 #include <asm/current.h>
  24 #include <asm/msa.h>
  25
  26 #ifdef CONFIG_MIPS_MT_FPAFF
  27 #include <asm/mips_mt.h>
  28 #endif
  29
  30 struct sigcontext;
  31 struct sigcontext32;
  32
  33 extern void _init_fpu(void);
  34 extern void _save_fp(struct task_struct *);
  35 extern void _restore_fp(struct task_struct *);
  36
  37 /*
  38  * This enum specifies a mode in which we want the FPU to operate, for cores
  39  * which implement the Status.FR bit. Note that the bottom bit of the value
  40  * purposefully matches the desired value of the Status.FR bit.
  41  */
  42 enum fpu_mode {
  43         FPU_32BIT = 0,          /* FR = 0 */
  44         FPU_64BIT,              /* FR = 1, FRE = 0 */
  45         FPU_AS_IS,
  46         FPU_HYBRID,             /* FR = 1, FRE = 1 */
  47
  48 #define FPU_FR_MASK             0x1
  49 };
  50
  51 static inline int __enable_fpu(enum fpu_mode mode)
  52 {
  53         int fr;
  54
  55         switch (mode) {
  56         case FPU_AS_IS:
  57                 /* just enable the FPU in its current mode */
  58                 set_c0_status(ST0_CU1);
  59                 enable_fpu_hazard();
  60                 return 0;
  61
  62         case FPU_HYBRID:
  63                 if (!cpu_has_fre)
  64                         return SIGFPE;
  65
  66                 /* set FRE */
  67                 write_c0_config5(read_c0_config5() | MIPS_CONF5_FRE);
  68                 goto fr_common;
  69
  70         case FPU_64BIT:
  71 #if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT))
  72                 /* we only have a 32-bit FPU */
  73                 return SIGFPE;
  74 #endif
  75                 /* fall through */
  76         case FPU_32BIT:
  77                 /* clear FRE */
  78                 write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE);
  79 fr_common:
  80                 /* set CU1 & change FR appropriately */
  81                 fr = (int)mode & FPU_FR_MASK;
  82                 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
  83                 enable_fpu_hazard();
  84
  85                 /* check FR has the desired value */
  86                 return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;
  87
  88         default:
  89                 BUG();
  90         }
  91
  92         return SIGFPE;
  93 }
  94
  95 #define __disable_fpu()                                                 \
  96 do {                                                                    \
  97         clear_c0_status(ST0_CU1);                                       \
  98         disable_fpu_hazard();                                           \
  99 } while (0)
 100
 101 #define clear_fpu_owner()       clear_thread_flag(TIF_USEDFPU)
 102
 103 static inline int __is_fpu_owner(void)
 104 {
 105         return test_thread_flag(TIF_USEDFPU);
 106 }
 107
 108 static inline int is_fpu_owner(void)
 109 {
 110         return cpu_has_fpu && __is_fpu_owner();
 111 }
 112
 113 static inline int __own_fpu(void)
 114 {
 115         enum fpu_mode mode;
 116         int ret;
 117
 118         if (test_thread_flag(TIF_HYBRID_FPREGS))
 119                 mode = FPU_HYBRID;
 120         else
 121                 mode = !test_thread_flag(TIF_32BIT_FPREGS);
 122
 123         ret = __enable_fpu(mode);
 124         if (ret)
 125                 return ret;
 126
 127         KSTK_STATUS(current) |= ST0_CU1;
 128         if (mode == FPU_64BIT || mode == FPU_HYBRID)
 129                 KSTK_STATUS(current) |= ST0_FR;
 130         else /* mode == FPU_32BIT */
 131                 KSTK_STATUS(current) &= ~ST0_FR;
 132
 133         set_thread_flag(TIF_USEDFPU);
 134         return 0;
 135 }
 136
 137 static inline int own_fpu_inatomic(int restore)
 138 {
 139         int ret = 0;
 140
 141         if (cpu_has_fpu && !__is_fpu_owner()) {
 142                 ret = __own_fpu();
 143                 if (restore && !ret)
 144                         _restore_fp(current);
 145         }
 146         return ret;
 147 }
 148
 149 static inline int own_fpu(int restore)
 150 {
 151         int ret;
 152
 153         preempt_disable();
 154         ret = own_fpu_inatomic(restore);
 155         preempt_enable();
 156         return ret;
 157 }
 158
 159 static inline void lose_fpu(int save)
 160 {
 161         preempt_disable();
 162         if (is_msa_enabled()) {
 163                 if (save) {
 164                         save_msa(current);
 165                         current->thread.fpu.fcr31 =
 166                                         read_32bit_cp1_register(CP1_STATUS);
 167                 }
 168                 disable_msa();
 169                 clear_thread_flag(TIF_USEDMSA);
 170         } else if (is_fpu_owner()) {
 171                 if (save)
 172                         _save_fp(current);
 173                 __disable_fpu();
 174         }
 175         KSTK_STATUS(current) &= ~ST0_CU1;
 176         clear_thread_flag(TIF_USEDFPU);
 177         preempt_enable();
 178 }
 179
 180 static inline int init_fpu(void)
 181 {
 182         int ret = 0;
 183
 184         if (cpu_has_fpu) {
 185                 ret = __own_fpu();
 186                 if (!ret) {
 187                         unsigned int config5 = read_c0_config5();
 188
 189                         /*
 190                          * Ensure FRE is clear whilst running _init_fpu, since
 191                          * single precision FP instructions are used. If FRE
 192                          * was set then we'll just end up initialising all 32
 193                          * 64b registers.
 194                          */
 195                         write_c0_config5(config5 & ~MIPS_CONF5_FRE);
 196                         enable_fpu_hazard();
 197
 198                         _init_fpu();
 199
 200                         /* Restore FRE */
 201                         write_c0_config5(config5);
 202                         enable_fpu_hazard();
 203                 }
 204         } else
 205                 fpu_emulator_init_fpu();
 206
 207         return ret;
 208 }
 209
 210 static inline void save_fp(struct task_struct *tsk)
 211 {
 212         if (cpu_has_fpu)
 213                 _save_fp(tsk);
 214 }
 215
 216 static inline void restore_fp(struct task_struct *tsk)
 217 {
 218         if (cpu_has_fpu)
 219                 _restore_fp(tsk);
 220 }
 221
 222 static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
 223 {
 224         if (tsk == current) {
 225                 preempt_disable();
 226                 if (is_fpu_owner())
 227                         _save_fp(current);
 228                 preempt_enable();
 229         }
 230
 231         return tsk->thread.fpu.fpr;
 232 }
 233
 234 #endif /* _ASM_FPU_H */