2 * Copyright (C) 2002 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
13 #include <linux/sched.h>
14 #include <linux/thread_info.h>
15 #include <linux/bitops.h>
17 #include <asm/mipsregs.h>
19 #include <asm/cpu-features.h>
20 #include <asm/fpu_emulator.h>
21 #include <asm/hazards.h>
22 #include <asm/processor.h>
23 #include <asm/current.h>
26 #ifdef CONFIG_MIPS_MT_FPAFF
27 #include <asm/mips_mt.h>
33 extern void _init_fpu(void);
34 extern void _save_fp(struct task_struct
*);
35 extern void _restore_fp(struct task_struct
*);
38 * This enum specifies a mode in which we want the FPU to operate, for cores
39 * which implement the Status.FR bit. Note that the bottom bit of the value
40 * purposefully matches the desired value of the Status.FR bit.
43 FPU_32BIT
= 0, /* FR = 0 */
44 FPU_64BIT
, /* FR = 1, FRE = 0 */
46 FPU_HYBRID
, /* FR = 1, FRE = 1 */
48 #define FPU_FR_MASK 0x1
51 static inline int __enable_fpu(enum fpu_mode mode
)
57 /* just enable the FPU in its current mode */
58 set_c0_status(ST0_CU1
);
67 write_c0_config5(read_c0_config5() | MIPS_CONF5_FRE
);
71 #if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT))
72 /* we only have a 32-bit FPU */
78 write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE
);
80 /* set CU1 & change FR appropriately */
81 fr
= (int)mode
& FPU_FR_MASK
;
82 change_c0_status(ST0_CU1
| ST0_FR
, ST0_CU1
| (fr
? ST0_FR
: 0));
85 /* check FR has the desired value */
86 return (!!(read_c0_status() & ST0_FR
) == !!fr
) ? 0 : SIGFPE
;
95 #define __disable_fpu() \
97 clear_c0_status(ST0_CU1); \
98 disable_fpu_hazard(); \
101 #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
103 static inline int __is_fpu_owner(void)
105 return test_thread_flag(TIF_USEDFPU
);
108 static inline int is_fpu_owner(void)
110 return cpu_has_fpu
&& __is_fpu_owner();
113 static inline int __own_fpu(void)
118 if (test_thread_flag(TIF_HYBRID_FPREGS
))
121 mode
= !test_thread_flag(TIF_32BIT_FPREGS
);
123 ret
= __enable_fpu(mode
);
127 KSTK_STATUS(current
) |= ST0_CU1
;
128 if (mode
== FPU_64BIT
|| mode
== FPU_HYBRID
)
129 KSTK_STATUS(current
) |= ST0_FR
;
130 else /* mode == FPU_32BIT */
131 KSTK_STATUS(current
) &= ~ST0_FR
;
133 set_thread_flag(TIF_USEDFPU
);
137 static inline int own_fpu_inatomic(int restore
)
141 if (cpu_has_fpu
&& !__is_fpu_owner()) {
144 _restore_fp(current
);
149 static inline int own_fpu(int restore
)
154 ret
= own_fpu_inatomic(restore
);
159 static inline void lose_fpu(int save
)
162 if (is_msa_enabled()) {
165 current
->thread
.fpu
.fcr31
=
166 read_32bit_cp1_register(CP1_STATUS
);
169 clear_thread_flag(TIF_USEDMSA
);
170 } else if (is_fpu_owner()) {
175 KSTK_STATUS(current
) &= ~ST0_CU1
;
176 clear_thread_flag(TIF_USEDFPU
);
180 static inline int init_fpu(void)
187 unsigned int config5
= read_c0_config5();
190 * Ensure FRE is clear whilst running _init_fpu, since
191 * single precision FP instructions are used. If FRE
192 * was set then we'll just end up initialising all 32
195 write_c0_config5(config5
& ~MIPS_CONF5_FRE
);
201 write_c0_config5(config5
);
205 fpu_emulator_init_fpu();
210 static inline void save_fp(struct task_struct
*tsk
)
216 static inline void restore_fp(struct task_struct
*tsk
)
222 static inline union fpureg
*get_fpu_regs(struct task_struct
*tsk
)
224 if (tsk
== current
) {
231 return tsk
->thread
.fpu
.fpr
;
234 #endif /* _ASM_FPU_H */
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