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[deliverable/linux.git] / arch / mips / include / asm / mach-au1x00 / gpio-au1000.h
1 /*
2 * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
3 *
4 * Copyright (c) 2009 Manuel Lauss.
5 *
6 * Licensed under the terms outlined in the file COPYING.
7 */
8
9 #ifndef _ALCHEMY_GPIO_AU1000_H_
10 #define _ALCHEMY_GPIO_AU1000_H_
11
12 #include <asm/mach-au1x00/au1000.h>
13
14 /* The default GPIO numberspace as documented in the Alchemy manuals.
15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
16 */
17 #define ALCHEMY_GPIO1_BASE 0
18 #define ALCHEMY_GPIO2_BASE 200
19
20 #define ALCHEMY_GPIO1_NUM 32
21 #define ALCHEMY_GPIO2_NUM 16
22 #define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23 #define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
24
25 #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
26
27
28 static inline int au1000_gpio1_to_irq(int gpio)
29 {
30 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
31 }
32
33 static inline int au1000_gpio2_to_irq(int gpio)
34 {
35 return -ENXIO;
36 }
37
38 #ifdef CONFIG_SOC_AU1000
39 static inline int au1000_irq_to_gpio(int irq)
40 {
41 if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31))
42 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
43
44 return -ENXIO;
45 }
46 #endif
47
48 static inline int au1500_gpio1_to_irq(int gpio)
49 {
50 gpio -= ALCHEMY_GPIO1_BASE;
51
52 switch (gpio) {
53 case 0 ... 15:
54 case 20:
55 case 23 ... 28: return MAKE_IRQ(1, gpio);
56 }
57
58 return -ENXIO;
59 }
60
61 static inline int au1500_gpio2_to_irq(int gpio)
62 {
63 gpio -= ALCHEMY_GPIO2_BASE;
64
65 switch (gpio) {
66 case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0);
67 case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4);
68 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
69 }
70
71 return -ENXIO;
72 }
73
74 #ifdef CONFIG_SOC_AU1500
75 static inline int au1500_irq_to_gpio(int irq)
76 {
77 switch (irq) {
78 case AU1000_GPIO_0 ... AU1000_GPIO_15:
79 case AU1500_GPIO_20:
80 case AU1500_GPIO_23 ... AU1500_GPIO_28:
81 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
82 case AU1500_GPIO_200 ... AU1500_GPIO_203:
83 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0;
84 case AU1500_GPIO_204 ... AU1500_GPIO_205:
85 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4;
86 case AU1500_GPIO_206 ... AU1500_GPIO_207:
87 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
88 case AU1500_GPIO_208_215:
89 return ALCHEMY_GPIO2_BASE + 8;
90 }
91
92 return -ENXIO;
93 }
94 #endif
95
96 static inline int au1100_gpio1_to_irq(int gpio)
97 {
98 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
99 }
100
101 static inline int au1100_gpio2_to_irq(int gpio)
102 {
103 gpio -= ALCHEMY_GPIO2_BASE;
104
105 if ((gpio >= 8) && (gpio <= 15))
106 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
107 }
108
109 #ifdef CONFIG_SOC_AU1100
110 static inline int au1100_irq_to_gpio(int irq)
111 {
112 switch (irq) {
113 case AU1000_GPIO_0 ... AU1000_GPIO_31:
114 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
115 case AU1100_GPIO_208_215:
116 return ALCHEMY_GPIO2_BASE + 8;
117 }
118
119 return -ENXIO;
120 }
121 #endif
122
123 static inline int au1550_gpio1_to_irq(int gpio)
124 {
125 gpio -= ALCHEMY_GPIO1_BASE;
126
127 switch (gpio) {
128 case 0 ... 15:
129 case 20 ... 28: return MAKE_IRQ(1, gpio);
130 case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
131 }
132
133 return -ENXIO;
134 }
135
136 static inline int au1550_gpio2_to_irq(int gpio)
137 {
138 gpio -= ALCHEMY_GPIO2_BASE;
139
140 switch (gpio) {
141 case 0: return MAKE_IRQ(1, 16);
142 case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
143 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
144 case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
145 }
146
147 return -ENXIO;
148 }
149
150 #ifdef CONFIG_SOC_AU1550
151 static inline int au1550_irq_to_gpio(int irq)
152 {
153 switch (irq) {
154 case AU1000_GPIO_0 ... AU1000_GPIO_15:
155 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
156 case AU1550_GPIO_200:
157 case AU1500_GPIO_201_205:
158 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0;
159 case AU1500_GPIO_16 ... AU1500_GPIO_28:
160 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16;
161 case AU1500_GPIO_206 ... AU1500_GPIO_208_218:
162 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
163 }
164
165 return -ENXIO;
166 }
167 #endif
168
169 static inline int au1200_gpio1_to_irq(int gpio)
170 {
171 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
172 }
173
174 static inline int au1200_gpio2_to_irq(int gpio)
175 {
176 gpio -= ALCHEMY_GPIO2_BASE;
177
178 switch (gpio) {
179 case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0);
180 case 3: return MAKE_IRQ(0, 22);
181 case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4);
182 case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
183 }
184
185 return -ENXIO;
186 }
187
188 #ifdef CONFIG_SOC_AU1200
189 static inline int au1200_irq_to_gpio(int irq)
190 {
191 switch (irq) {
192 case AU1000_GPIO_0 ... AU1000_GPIO_31:
193 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
194 case AU1200_GPIO_200 ... AU1200_GPIO_202:
195 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0;
196 case AU1200_GPIO_203:
197 return ALCHEMY_GPIO2_BASE + 3;
198 case AU1200_GPIO_204 ... AU1200_GPIO_208_215:
199 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4;
200 }
201
202 return -ENXIO;
203 }
204 #endif
205
206 /*
207 * GPIO1 block macros for common linux gpio functions.
208 */
209 static inline void alchemy_gpio1_set_value(int gpio, int v)
210 {
211 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
212 unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
213 au_writel(mask, r);
214 au_sync();
215 }
216
217 static inline int alchemy_gpio1_get_value(int gpio)
218 {
219 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
220 return au_readl(SYS_PINSTATERD) & mask;
221 }
222
223 static inline int alchemy_gpio1_direction_input(int gpio)
224 {
225 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
226 au_writel(mask, SYS_TRIOUTCLR);
227 au_sync();
228 return 0;
229 }
230
231 static inline int alchemy_gpio1_direction_output(int gpio, int v)
232 {
233 /* hardware switches to "output" mode when one of the two
234 * "set_value" registers is accessed.
235 */
236 alchemy_gpio1_set_value(gpio, v);
237 return 0;
238 }
239
240 static inline int alchemy_gpio1_is_valid(int gpio)
241 {
242 return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
243 }
244
245 static inline int alchemy_gpio1_to_irq(int gpio)
246 {
247 #if defined(CONFIG_SOC_AU1000)
248 return au1000_gpio1_to_irq(gpio);
249 #elif defined(CONFIG_SOC_AU1100)
250 return au1100_gpio1_to_irq(gpio);
251 #elif defined(CONFIG_SOC_AU1500)
252 return au1500_gpio1_to_irq(gpio);
253 #elif defined(CONFIG_SOC_AU1550)
254 return au1550_gpio1_to_irq(gpio);
255 #elif defined(CONFIG_SOC_AU1200)
256 return au1200_gpio1_to_irq(gpio);
257 #else
258 return -ENXIO;
259 #endif
260 }
261
262 /*
263 * GPIO2 block macros for common linux GPIO functions. The 'gpio'
264 * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
265 */
266 static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
267 {
268 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
269 unsigned long d = au_readl(GPIO2_DIR);
270 if (to_out)
271 d |= mask;
272 else
273 d &= ~mask;
274 au_writel(d, GPIO2_DIR);
275 au_sync();
276 }
277
278 static inline void alchemy_gpio2_set_value(int gpio, int v)
279 {
280 unsigned long mask;
281 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
282 au_writel(mask, GPIO2_OUTPUT);
283 au_sync();
284 }
285
286 static inline int alchemy_gpio2_get_value(int gpio)
287 {
288 return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
289 }
290
291 static inline int alchemy_gpio2_direction_input(int gpio)
292 {
293 unsigned long flags;
294 local_irq_save(flags);
295 __alchemy_gpio2_mod_dir(gpio, 0);
296 local_irq_restore(flags);
297 return 0;
298 }
299
300 static inline int alchemy_gpio2_direction_output(int gpio, int v)
301 {
302 unsigned long flags;
303 alchemy_gpio2_set_value(gpio, v);
304 local_irq_save(flags);
305 __alchemy_gpio2_mod_dir(gpio, 1);
306 local_irq_restore(flags);
307 return 0;
308 }
309
310 static inline int alchemy_gpio2_is_valid(int gpio)
311 {
312 return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
313 }
314
315 static inline int alchemy_gpio2_to_irq(int gpio)
316 {
317 #if defined(CONFIG_SOC_AU1000)
318 return au1000_gpio2_to_irq(gpio);
319 #elif defined(CONFIG_SOC_AU1100)
320 return au1100_gpio2_to_irq(gpio);
321 #elif defined(CONFIG_SOC_AU1500)
322 return au1500_gpio2_to_irq(gpio);
323 #elif defined(CONFIG_SOC_AU1550)
324 return au1550_gpio2_to_irq(gpio);
325 #elif defined(CONFIG_SOC_AU1200)
326 return au1200_gpio2_to_irq(gpio);
327 #else
328 return -ENXIO;
329 #endif
330 }
331
332 /**********************************************************************/
333
334 /* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
335 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this
336 * register enables use of GPIOs as wake source.
337 */
338 static inline void alchemy_gpio1_input_enable(void)
339 {
340 au_writel(0, SYS_PININPUTEN); /* the write op is key */
341 au_sync();
342 }
343
344 /* GPIO2 shared interrupts and control */
345
346 static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
347 {
348 unsigned long r = au_readl(GPIO2_INTENABLE);
349 if (en)
350 r |= 1 << gpio2;
351 else
352 r &= ~(1 << gpio2);
353 au_writel(r, GPIO2_INTENABLE);
354 au_sync();
355 }
356
357 /**
358 * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
359 * @gpio2: The GPIO2 pin to activate (200...215).
360 *
361 * GPIO208-215 have one shared interrupt line to the INTC. They are
362 * and'ed with a per-pin enable bit and finally or'ed together to form
363 * a single irq request (useful for active-high sources).
364 * With this function, a pins' individual contribution to the int request
365 * can be enabled. As with all other GPIO-based interrupts, the INTC
366 * must be programmed to accept the GPIO208_215 interrupt as well.
367 *
368 * NOTE: Calling this macro is only necessary for GPIO208-215; all other
369 * GPIO2-based interrupts have their own request to the INTC. Please
370 * consult your Alchemy databook for more information!
371 *
372 * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
373 * line to the INTC, GPIO201_205. This function can be used for those
374 * as well.
375 *
376 * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
377 * (200-215 by default). No sanity checks are made,
378 */
379 static inline void alchemy_gpio2_enable_int(int gpio2)
380 {
381 unsigned long flags;
382
383 gpio2 -= ALCHEMY_GPIO2_BASE;
384
385 #if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
386 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
387 gpio2 -= 8;
388 #endif
389 local_irq_save(flags);
390 __alchemy_gpio2_mod_int(gpio2, 1);
391 local_irq_restore(flags);
392 }
393
394 /**
395 * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
396 * @gpio2: The GPIO2 pin to activate (200...215).
397 *
398 * see function alchemy_gpio2_enable_int() for more information.
399 */
400 static inline void alchemy_gpio2_disable_int(int gpio2)
401 {
402 unsigned long flags;
403
404 gpio2 -= ALCHEMY_GPIO2_BASE;
405
406 #if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
407 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
408 gpio2 -= 8;
409 #endif
410 local_irq_save(flags);
411 __alchemy_gpio2_mod_int(gpio2, 0);
412 local_irq_restore(flags);
413 }
414
415 /**
416 * alchemy_gpio2_enable - Activate GPIO2 block.
417 *
418 * The GPIO2 block must be enabled excplicitly to work. On systems
419 * where this isn't done by the bootloader, this macro can be used.
420 */
421 static inline void alchemy_gpio2_enable(void)
422 {
423 au_writel(3, GPIO2_ENABLE); /* reset, clock enabled */
424 au_sync();
425 au_writel(1, GPIO2_ENABLE); /* clock enabled */
426 au_sync();
427 }
428
429 /**
430 * alchemy_gpio2_disable - disable GPIO2 block.
431 *
432 * Disable and put GPIO2 block in low-power mode.
433 */
434 static inline void alchemy_gpio2_disable(void)
435 {
436 au_writel(2, GPIO2_ENABLE); /* reset, clock disabled */
437 au_sync();
438 }
439
440 /**********************************************************************/
441
442 /* wrappers for on-chip gpios; can be used before gpio chips have been
443 * registered with gpiolib.
444 */
445 static inline int alchemy_gpio_direction_input(int gpio)
446 {
447 return (gpio >= ALCHEMY_GPIO2_BASE) ?
448 alchemy_gpio2_direction_input(gpio) :
449 alchemy_gpio1_direction_input(gpio);
450 }
451
452 static inline int alchemy_gpio_direction_output(int gpio, int v)
453 {
454 return (gpio >= ALCHEMY_GPIO2_BASE) ?
455 alchemy_gpio2_direction_output(gpio, v) :
456 alchemy_gpio1_direction_output(gpio, v);
457 }
458
459 static inline int alchemy_gpio_get_value(int gpio)
460 {
461 return (gpio >= ALCHEMY_GPIO2_BASE) ?
462 alchemy_gpio2_get_value(gpio) :
463 alchemy_gpio1_get_value(gpio);
464 }
465
466 static inline void alchemy_gpio_set_value(int gpio, int v)
467 {
468 if (gpio >= ALCHEMY_GPIO2_BASE)
469 alchemy_gpio2_set_value(gpio, v);
470 else
471 alchemy_gpio1_set_value(gpio, v);
472 }
473
474 static inline int alchemy_gpio_is_valid(int gpio)
475 {
476 return (gpio >= ALCHEMY_GPIO2_BASE) ?
477 alchemy_gpio2_is_valid(gpio) :
478 alchemy_gpio1_is_valid(gpio);
479 }
480
481 static inline int alchemy_gpio_cansleep(int gpio)
482 {
483 return 0; /* Alchemy never gets tired */
484 }
485
486 static inline int alchemy_gpio_to_irq(int gpio)
487 {
488 return (gpio >= ALCHEMY_GPIO2_BASE) ?
489 alchemy_gpio2_to_irq(gpio) :
490 alchemy_gpio1_to_irq(gpio);
491 }
492
493 static inline int alchemy_irq_to_gpio(int irq)
494 {
495 #if defined(CONFIG_SOC_AU1000)
496 return au1000_irq_to_gpio(irq);
497 #elif defined(CONFIG_SOC_AU1100)
498 return au1100_irq_to_gpio(irq);
499 #elif defined(CONFIG_SOC_AU1500)
500 return au1500_irq_to_gpio(irq);
501 #elif defined(CONFIG_SOC_AU1550)
502 return au1550_irq_to_gpio(irq);
503 #elif defined(CONFIG_SOC_AU1200)
504 return au1200_irq_to_gpio(irq);
505 #else
506 return -ENXIO;
507 #endif
508 }
509
510 /**********************************************************************/
511
512 /* Linux gpio framework integration.
513 *
514 * 4 use cases of Au1000-Au1200 GPIOS:
515 *(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
516 * Board must register gpiochips.
517 *(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
518 * 2 (1 for Au1000) gpio_chips are registered.
519 *
520 *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
521 * the boards' gpio.h must provide the linux gpio wrapper functions,
522 *
523 *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
524 * inlinable gpio functions are provided which enable access to the
525 * Au1000 gpios only by using the numbers straight out of the data-
526 * sheets.
527
528 * Cases 1 and 3 are intended for boards which want to provide their own
529 * GPIO namespace and -operations (i.e. for example you have 8 GPIOs
530 * which are in part provided by spare Au1000 GPIO pins and in part by
531 * an external FPGA but you still want them to be accssible in linux
532 * as gpio0-7. The board can of course use the alchemy_gpioX_* functions
533 * as required).
534 */
535
536 #ifndef CONFIG_GPIOLIB
537
538
539 #ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
540
541 static inline int gpio_direction_input(int gpio)
542 {
543 return alchemy_gpio_direction_input(gpio);
544 }
545
546 static inline int gpio_direction_output(int gpio, int v)
547 {
548 return alchemy_gpio_direction_output(gpio, v);
549 }
550
551 static inline int gpio_get_value(int gpio)
552 {
553 return alchemy_gpio_get_value(gpio);
554 }
555
556 static inline void gpio_set_value(int gpio, int v)
557 {
558 alchemy_gpio_set_value(gpio, v);
559 }
560
561 static inline int gpio_is_valid(int gpio)
562 {
563 return alchemy_gpio_is_valid(gpio);
564 }
565
566 static inline int gpio_cansleep(int gpio)
567 {
568 return alchemy_gpio_cansleep(gpio);
569 }
570
571 static inline int gpio_to_irq(int gpio)
572 {
573 return alchemy_gpio_to_irq(gpio);
574 }
575
576 static inline int irq_to_gpio(int irq)
577 {
578 return alchemy_irq_to_gpio(irq);
579 }
580
581 #endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
582
583
584 #else /* CONFIG GPIOLIB */
585
586
587 /* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
588 #ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
589
590 /* get everything through gpiolib */
591 #define gpio_to_irq __gpio_to_irq
592 #define gpio_get_value __gpio_get_value
593 #define gpio_set_value __gpio_set_value
594 #define gpio_cansleep __gpio_cansleep
595 #define irq_to_gpio alchemy_irq_to_gpio
596
597 #include <asm-generic/gpio.h>
598
599 #endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
600
601
602 #endif /* !CONFIG_GPIOLIB */
603
604 #endif /* _ALCHEMY_GPIO_AU1000_H_ */
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