2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2008 Cavium Networks
8 #ifndef __OCTEON_IRQ_H__
9 #define __OCTEON_IRQ_H__
11 #define NR_IRQS OCTEON_IRQ_LAST
12 #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
15 /* 1 - 8 represent the 8 MIPS standard interrupt sources */
18 /* CIU0, CUI2, CIU4 are 3, 4, 5 */
22 /* sources in CIU_INTX_EN0 */
24 OCTEON_IRQ_GPIO0
= OCTEON_IRQ_WORKQ0
+ 16,
25 OCTEON_IRQ_WDOG0
= OCTEON_IRQ_GPIO0
+ 16,
26 OCTEON_IRQ_WDOG15
= OCTEON_IRQ_WDOG0
+ 15,
27 OCTEON_IRQ_MBOX0
= OCTEON_IRQ_WDOG0
+ 16,
53 #ifndef CONFIG_PCI_MSI
59 /* 256 - 511 represent the MSI interrupts 0-255 */
60 #define OCTEON_IRQ_MSI_BIT0 (256)
62 #define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
63 #define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
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