arch/mips/include/asm/mach-loongson/loongson.h

   1 /*
   2  * Copyright (C) 2009 Lemote, Inc.
   3  * Author: Wu Zhangjin <wuzj@lemote.com>
   4  *
   5  * This program is free software; you can redistribute  it and/or modify it
   6  * under  the terms of  the GNU General  Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  *
  10  */
  11
  12 #ifndef __ASM_MACH_LOONGSON_LOONGSON_H
  13 #define __ASM_MACH_LOONGSON_LOONGSON_H
  14
  15 #include <linux/io.h>
  16 #include <linux/init.h>
  17
  18 /* loongson internal northbridge initialization */
  19 extern void bonito_irq_init(void);
  20
  21 /* machine-specific reboot/halt operation */
  22 extern void mach_prepare_reboot(void);
  23 extern void mach_prepare_shutdown(void);
  24
  25 /* environment arguments from bootloader */
  26 extern unsigned long bus_clock, cpu_clock_freq;
  27 extern unsigned long memsize, highmemsize;
  28
  29 /* loongson-specific command line, env and memory initialization */
  30 extern void __init prom_init_memory(void);
  31 extern void __init prom_init_cmdline(void);
  32 extern void __init prom_init_machtype(void);
  33 extern void __init prom_init_env(void);
  34 extern unsigned long _loongson_uart_base;
  35 extern unsigned long uart8250_base[];
  36 extern void prom_init_uart_base(void);
  37
  38 /* irq operation functions */
  39 extern void bonito_irqdispatch(void);
  40 extern void __init bonito_irq_init(void);
  41 extern void __init set_irq_trigger_mode(void);
  42 extern void __init mach_init_irq(void);
  43 extern void mach_irq_dispatch(unsigned int pending);
  44 extern int mach_i8259_irq(void);
  45
  46 /* We need this in some places... */
  47 #define delay() ({              \
  48         int x;                          \
  49         for (x = 0; x < 100000; x++)    \
  50                 __asm__ __volatile__(""); \
  51 })
  52
  53 #define LOONGSON_REG(x) \
  54         (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
  55
  56 #define LOONGSON_IRQ_BASE       32
  57 #define LOONGSON2_PERFCNT_IRQ   (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
  58
  59 #define LOONGSON_FLASH_BASE     0x1c000000
  60 #define LOONGSON_FLASH_SIZE     0x02000000      /* 32M */
  61 #define LOONGSON_FLASH_TOP      (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
  62
  63 #define LOONGSON_LIO0_BASE      0x1e000000
  64 #define LOONGSON_LIO0_SIZE      0x01C00000      /* 28M */
  65 #define LOONGSON_LIO0_TOP       (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
  66
  67 #define LOONGSON_BOOT_BASE      0x1fc00000
  68 #define LOONGSON_BOOT_SIZE      0x00100000      /* 1M */
  69 #define LOONGSON_BOOT_TOP       (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
  70 #define LOONGSON_REG_BASE       0x1fe00000
  71 #define LOONGSON_REG_SIZE       0x00100000      /* 256Bytes + 256Bytes + ??? */
  72 #define LOONGSON_REG_TOP        (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
  73
  74 #define LOONGSON_LIO1_BASE      0x1ff00000
  75 #define LOONGSON_LIO1_SIZE      0x00100000      /* 1M */
  76 #define LOONGSON_LIO1_TOP       (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
  77
  78 #define LOONGSON_PCILO0_BASE    0x10000000
  79 #define LOONGSON_PCILO1_BASE    0x14000000
  80 #define LOONGSON_PCILO2_BASE    0x18000000
  81 #define LOONGSON_PCILO_BASE     LOONGSON_PCILO0_BASE
  82 #define LOONGSON_PCILO_SIZE     0x0c000000      /* 64M * 3 */
  83 #define LOONGSON_PCILO_TOP      (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
  84
  85 #define LOONGSON_PCICFG_BASE    0x1fe80000
  86 #define LOONGSON_PCICFG_SIZE    0x00000800      /* 2K */
  87 #define LOONGSON_PCICFG_TOP     (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
  88 #define LOONGSON_PCIIO_BASE     0x1fd00000
  89 #define LOONGSON_PCIIO_SIZE     0x00100000      /* 1M */
  90 #define LOONGSON_PCIIO_TOP      (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
  91
  92 /* Loongson Register Bases */
  93
  94 #define LOONGSON_PCICONFIGBASE  0x00
  95 #define LOONGSON_REGBASE        0x100
  96
  97 /* PCI Configuration Registers */
  98
  99 #define LOONGSON_PCI_REG(x)     LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
 100 #define LOONGSON_PCIDID         LOONGSON_PCI_REG(0x00)
 101 #define LOONGSON_PCICMD         LOONGSON_PCI_REG(0x04)
 102 #define LOONGSON_PCICLASS       LOONGSON_PCI_REG(0x08)
 103 #define LOONGSON_PCILTIMER      LOONGSON_PCI_REG(0x0c)
 104 #define LOONGSON_PCIBASE0       LOONGSON_PCI_REG(0x10)
 105 #define LOONGSON_PCIBASE1       LOONGSON_PCI_REG(0x14)
 106 #define LOONGSON_PCIBASE2       LOONGSON_PCI_REG(0x18)
 107 #define LOONGSON_PCIBASE3       LOONGSON_PCI_REG(0x1c)
 108 #define LOONGSON_PCIBASE4       LOONGSON_PCI_REG(0x20)
 109 #define LOONGSON_PCIEXPRBASE    LOONGSON_PCI_REG(0x30)
 110 #define LOONGSON_PCIINT         LOONGSON_PCI_REG(0x3c)
 111
 112 #define LOONGSON_PCI_ISR4C      LOONGSON_PCI_REG(0x4c)
 113
 114 #define LOONGSON_PCICMD_PERR_CLR        0x80000000
 115 #define LOONGSON_PCICMD_SERR_CLR        0x40000000
 116 #define LOONGSON_PCICMD_MABORT_CLR      0x20000000
 117 #define LOONGSON_PCICMD_MTABORT_CLR     0x10000000
 118 #define LOONGSON_PCICMD_TABORT_CLR      0x08000000
 119 #define LOONGSON_PCICMD_MPERR_CLR       0x01000000
 120 #define LOONGSON_PCICMD_PERRRESPEN      0x00000040
 121 #define LOONGSON_PCICMD_ASTEPEN         0x00000080
 122 #define LOONGSON_PCICMD_SERREN          0x00000100
 123 #define LOONGSON_PCILTIMER_BUSLATENCY   0x0000ff00
 124 #define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT     8
 125
 126 /* Loongson h/w Configuration */
 127
 128 #define LOONGSON_GENCFG_OFFSET          0x4
 129 #define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
 130
 131 #define LOONGSON_GENCFG_DEBUGMODE       0x00000001
 132 #define LOONGSON_GENCFG_SNOOPEN         0x00000002
 133 #define LOONGSON_GENCFG_CPUSELFRESET    0x00000004
 134
 135 #define LOONGSON_GENCFG_FORCE_IRQA      0x00000008
 136 #define LOONGSON_GENCFG_IRQA_ISOUT      0x00000010
 137 #define LOONGSON_GENCFG_IRQA_FROM_INT1  0x00000020
 138 #define LOONGSON_GENCFG_BYTESWAP        0x00000040
 139
 140 #define LOONGSON_GENCFG_UNCACHED        0x00000080
 141 #define LOONGSON_GENCFG_PREFETCHEN      0x00000100
 142 #define LOONGSON_GENCFG_WBEHINDEN       0x00000200
 143 #define LOONGSON_GENCFG_CACHEALG        0x00000c00
 144 #define LOONGSON_GENCFG_CACHEALG_SHIFT  10
 145 #define LOONGSON_GENCFG_PCIQUEUE        0x00001000
 146 #define LOONGSON_GENCFG_CACHESTOP       0x00002000
 147 #define LOONGSON_GENCFG_MSTRBYTESWAP    0x00004000
 148 #define LOONGSON_GENCFG_BUSERREN        0x00008000
 149 #define LOONGSON_GENCFG_NORETRYTIMEOUT  0x00010000
 150 #define LOONGSON_GENCFG_SHORTCOPYTIMEOUT        0x00020000
 151
 152 /* PCI address map control */
 153
 154 #define LOONGSON_PCIMAP                 LOONGSON_REG(LOONGSON_REGBASE + 0x10)
 155 #define LOONGSON_PCIMEMBASECFG          LOONGSON_REG(LOONGSON_REGBASE + 0x14)
 156 #define LOONGSON_PCIMAP_CFG             LOONGSON_REG(LOONGSON_REGBASE + 0x18)
 157
 158 /* GPIO Regs - r/w */
 159
 160 #define LOONGSON_GPIODATA               LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
 161 #define LOONGSON_GPIOIE                 LOONGSON_REG(LOONGSON_REGBASE + 0x20)
 162
 163 /* ICU Configuration Regs - r/w */
 164
 165 #define LOONGSON_INTEDGE                LOONGSON_REG(LOONGSON_REGBASE + 0x24)
 166 #define LOONGSON_INTSTEER               LOONGSON_REG(LOONGSON_REGBASE + 0x28)
 167 #define LOONGSON_INTPOL                 LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
 168
 169 /* ICU Enable Regs - IntEn & IntISR are r/o. */
 170
 171 #define LOONGSON_INTENSET               LOONGSON_REG(LOONGSON_REGBASE + 0x30)
 172 #define LOONGSON_INTENCLR               LOONGSON_REG(LOONGSON_REGBASE + 0x34)
 173 #define LOONGSON_INTEN                  LOONGSON_REG(LOONGSON_REGBASE + 0x38)
 174 #define LOONGSON_INTISR                 LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
 175
 176 /* ICU */
 177 #define LOONGSON_ICU_MBOXES             0x0000000f
 178 #define LOONGSON_ICU_MBOXES_SHIFT       0
 179 #define LOONGSON_ICU_DMARDY             0x00000010
 180 #define LOONGSON_ICU_DMAEMPTY           0x00000020
 181 #define LOONGSON_ICU_COPYRDY            0x00000040
 182 #define LOONGSON_ICU_COPYEMPTY          0x00000080
 183 #define LOONGSON_ICU_COPYERR            0x00000100
 184 #define LOONGSON_ICU_PCIIRQ             0x00000200
 185 #define LOONGSON_ICU_MASTERERR          0x00000400
 186 #define LOONGSON_ICU_SYSTEMERR          0x00000800
 187 #define LOONGSON_ICU_DRAMPERR           0x00001000
 188 #define LOONGSON_ICU_RETRYERR           0x00002000
 189 #define LOONGSON_ICU_GPIOS              0x01ff0000
 190 #define LOONGSON_ICU_GPIOS_SHIFT                16
 191 #define LOONGSON_ICU_GPINS              0x7e000000
 192 #define LOONGSON_ICU_GPINS_SHIFT                25
 193 #define LOONGSON_ICU_MBOX(N)            (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
 194 #define LOONGSON_ICU_GPIO(N)            (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
 195 #define LOONGSON_ICU_GPIN(N)            (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
 196
 197 /* PCI prefetch window base & mask */
 198
 199 #define LOONGSON_MEM_WIN_BASE_L         LOONGSON_REG(LOONGSON_REGBASE + 0x40)
 200 #define LOONGSON_MEM_WIN_BASE_H         LOONGSON_REG(LOONGSON_REGBASE + 0x44)
 201 #define LOONGSON_MEM_WIN_MASK_L         LOONGSON_REG(LOONGSON_REGBASE + 0x48)
 202 #define LOONGSON_MEM_WIN_MASK_H         LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
 203
 204 /* PCI_Hit*_Sel_* */
 205
 206 #define LOONGSON_PCI_HIT0_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x50)
 207 #define LOONGSON_PCI_HIT0_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x54)
 208 #define LOONGSON_PCI_HIT1_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x58)
 209 #define LOONGSON_PCI_HIT1_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
 210 #define LOONGSON_PCI_HIT2_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x60)
 211 #define LOONGSON_PCI_HIT2_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x64)
 212
 213 /* PXArb Config & Status */
 214
 215 #define LOONGSON_PXARB_CFG              LOONGSON_REG(LOONGSON_REGBASE + 0x68)
 216 #define LOONGSON_PXARB_STATUS           LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
 217
 218 /* pcimap */
 219
 220 #define LOONGSON_PCIMAP_PCIMAP_LO0      0x0000003f
 221 #define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT        0
 222 #define LOONGSON_PCIMAP_PCIMAP_LO1      0x00000fc0
 223 #define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT        6
 224 #define LOONGSON_PCIMAP_PCIMAP_LO2      0x0003f000
 225 #define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT        12
 226 #define LOONGSON_PCIMAP_PCIMAP_2        0x00040000
 227 #define LOONGSON_PCIMAP_WIN(WIN, ADDR)  \
 228         ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
 229
 230 #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
 231 #include <linux/cpufreq.h>
 232 extern void loongson2_cpu_wait(void);
 233 extern struct cpufreq_frequency_table loongson2_clockmod_table[];
 234
 235 /* Chip Config */
 236 #define LOONGSON_CHIPCFG0               LOONGSON_REG(LOONGSON_REGBASE + 0x80)
 237 #endif
 238
 239 /*
 240  * address windows configuration module
 241  *
 242  * loongson2e do not have this module
 243  */
 244 #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
 245
 246 /* address window config module base address */
 247 #define LOONGSON_ADDRWINCFG_BASE                0x3ff00000ul
 248 #define LOONGSON_ADDRWINCFG_SIZE                0x180
 249
 250 extern unsigned long _loongson_addrwincfg_base;
 251 #define LOONGSON_ADDRWINCFG(offset) \
 252         (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
 253
 254 #define CPU_WIN0_BASE   LOONGSON_ADDRWINCFG(0x00)
 255 #define CPU_WIN1_BASE   LOONGSON_ADDRWINCFG(0x08)
 256 #define CPU_WIN2_BASE   LOONGSON_ADDRWINCFG(0x10)
 257 #define CPU_WIN3_BASE   LOONGSON_ADDRWINCFG(0x18)
 258
 259 #define CPU_WIN0_MASK   LOONGSON_ADDRWINCFG(0x20)
 260 #define CPU_WIN1_MASK   LOONGSON_ADDRWINCFG(0x28)
 261 #define CPU_WIN2_MASK   LOONGSON_ADDRWINCFG(0x30)
 262 #define CPU_WIN3_MASK   LOONGSON_ADDRWINCFG(0x38)
 263
 264 #define CPU_WIN0_MMAP   LOONGSON_ADDRWINCFG(0x40)
 265 #define CPU_WIN1_MMAP   LOONGSON_ADDRWINCFG(0x48)
 266 #define CPU_WIN2_MMAP   LOONGSON_ADDRWINCFG(0x50)
 267 #define CPU_WIN3_MMAP   LOONGSON_ADDRWINCFG(0x58)
 268
 269 #define PCIDMA_WIN0_BASE        LOONGSON_ADDRWINCFG(0x60)
 270 #define PCIDMA_WIN1_BASE        LOONGSON_ADDRWINCFG(0x68)
 271 #define PCIDMA_WIN2_BASE        LOONGSON_ADDRWINCFG(0x70)
 272 #define PCIDMA_WIN3_BASE        LOONGSON_ADDRWINCFG(0x78)
 273
 274 #define PCIDMA_WIN0_MASK        LOONGSON_ADDRWINCFG(0x80)
 275 #define PCIDMA_WIN1_MASK        LOONGSON_ADDRWINCFG(0x88)
 276 #define PCIDMA_WIN2_MASK        LOONGSON_ADDRWINCFG(0x90)
 277 #define PCIDMA_WIN3_MASK        LOONGSON_ADDRWINCFG(0x98)
 278
 279 #define PCIDMA_WIN0_MMAP        LOONGSON_ADDRWINCFG(0xa0)
 280 #define PCIDMA_WIN1_MMAP        LOONGSON_ADDRWINCFG(0xa8)
 281 #define PCIDMA_WIN2_MMAP        LOONGSON_ADDRWINCFG(0xb0)
 282 #define PCIDMA_WIN3_MMAP        LOONGSON_ADDRWINCFG(0xb8)
 283
 284 #define ADDRWIN_WIN0    0
 285 #define ADDRWIN_WIN1    1
 286 #define ADDRWIN_WIN2    2
 287 #define ADDRWIN_WIN3    3
 288
 289 #define ADDRWIN_MAP_DST_DDR     0
 290 #define ADDRWIN_MAP_DST_PCI     1
 291 #define ADDRWIN_MAP_DST_LIO     1
 292
 293 /*
 294  * s: CPU, PCIDMA
 295  * d: DDR, PCI, LIO
 296  * win: 0, 1, 2, 3
 297  * src: map source
 298  * dst: map destination
 299  * size: ~mask + 1
 300  */
 301 #define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
 302         s##_WIN##w##_BASE = (src); \
 303         s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \
 304         s##_WIN##w##_MASK = ~(size-1); \
 305 } while (0)
 306
 307 #define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
 308         LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
 309 #define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
 310         LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
 311 #define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
 312         LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
 313
 314 #endif  /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
 315
 316 #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */