MIPS: PowerTV: Streamline access to platform device registers
[deliverable/linux.git] / arch / mips / include / asm / mach-powertv / asic_regs.h
1 /*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19 #ifndef __ASM_MACH_POWERTV_ASIC_H_
20 #define __ASM_MACH_POWERTV_ASIC_H_
21 #include <linux/io.h>
22
23 /* ASIC types */
24 enum asic_type {
25 ASIC_UNKNOWN,
26 ASIC_ZEUS,
27 ASIC_CALLIOPE,
28 ASIC_CRONUS,
29 ASIC_CRONUSLITE,
30 ASICS
31 };
32
33 /* hardcoded values read from Chip Version registers */
34 #define CRONUS_10 0x0B4C1C20
35 #define CRONUS_11 0x0B4C1C21
36 #define CRONUSLITE_10 0x0B4C1C40
37
38 #define NAND_FLASH_BASE 0x03000000
39 #define CALLIOPE_IO_BASE 0x08000000
40 #define CRONUS_IO_BASE 0x09000000
41 #define ZEUS_IO_BASE 0x09000000
42
43 #define ASIC_IO_SIZE 0x01000000
44
45 /* Definitions for backward compatibility */
46 #define UART1_INTSTAT uart1_intstat
47 #define UART1_INTEN uart1_inten
48 #define UART1_CONFIG1 uart1_config1
49 #define UART1_CONFIG2 uart1_config2
50 #define UART1_DIVISORHI uart1_divisorhi
51 #define UART1_DIVISORLO uart1_divisorlo
52 #define UART1_DATA uart1_data
53 #define UART1_STATUS uart1_status
54
55 /* ASIC register enumeration */
56 union register_map_entry {
57 unsigned long phys;
58 u32 *virt;
59 };
60
61 #define REGISTER_MAP_ELEMENT(x) union register_map_entry x;
62 struct register_map {
63 #include <asm/mach-powertv/asic_reg_map.h>
64 };
65 #undef REGISTER_MAP_ELEMENT
66
67 /**
68 * register_map_offset_phys - add an offset to the physical address
69 * @map: Pointer to the &struct register_map
70 * @offset: Value to add
71 *
72 * Only adds the base to non-zero physical addresses
73 */
74 static inline void register_map_offset_phys(struct register_map *map,
75 unsigned long offset)
76 {
77 #define REGISTER_MAP_ELEMENT(x) do { \
78 if (map->x.phys != 0) \
79 map->x.phys += offset; \
80 } while (false);
81
82 #include <asm/mach-powertv/asic_reg_map.h>
83 #undef REGISTER_MAP_ELEMENT
84 }
85
86 /**
87 * register_map_virtualize - Convert &register_map to virtual addresses
88 * @map: Pointer to &register_map to virtualize
89 */
90 static inline void register_map_virtualize(struct register_map *map)
91 {
92 #define REGISTER_MAP_ELEMENT(x) do { \
93 map->x.virt = (!map->x.phys) ? NULL : \
94 UNCAC_ADDR(phys_to_virt(map->x.phys)); \
95 } while (false);
96
97 #include <asm/mach-powertv/asic_reg_map.h>
98 #undef REGISTER_MAP_ELEMENT
99 }
100
101 extern struct register_map _asic_register_map;
102
103 /*
104 * Macros to interface to registers through their ioremapped address
105 * asic_reg_phys_addr Returns the physical address of the given register
106 * asic_reg_addr Returns the iomapped virtual address of the given
107 * register.
108 */
109 #define asic_reg_addr(x) (_asic_register_map.x.virt)
110 #define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \
111 (unsigned long) asic_reg_addr(x))))
112
113 /*
114 * The asic_reg macro is gone. It should be replaced by either asic_read or
115 * asic_write, as appropriate.
116 */
117
118 #define asic_read(x) readl(asic_reg_addr(x))
119 #define asic_write(v, x) writel(v, asic_reg_addr(x))
120
121 extern void asic_irq_init(void);
122 #endif
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